From 2be39c079d692a07b55c8795051d40c0c94a3633 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 4 Oct 2012 14:24:09 -0600 Subject: ARM: tegra: move iomap.h to mach-tegra Nothing outside mach-tegra uses this file, so there's no need for it to be in . Since uncompress.h and debug-macro.S remain in include/mach, they need to include "../../iomap.h" becaue of this change. uncompress.h will soon be deleted in later multi-platform/single-zImage patches. debug-macro.S will need to continue to include this header using an explicit relative path, to avoid duplicating the physical->virtual address mapping that iomap.h dictates. Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/headsmp.S | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm/mach-tegra/headsmp.S') diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 6addc78cb6b2..93f0370cc95b 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -3,9 +3,8 @@ #include -#include - #include "flowctrl.h" +#include "iomap.h" #include "reset.h" #include "sleep.h" -- cgit v1.2.1 From d3f293656c07a1147c11e8c8774d7955a903cee0 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Wed, 31 Oct 2012 17:41:16 +0800 Subject: ARM: tegra: cpuidle: add CPU resume function The CPU suspending on Tegra means CPU power gating. We add a resume function for taking care the CPUs that resume from power gating status. This function was been hooked to the reset handler. We take care everything here before go into kernel. Be aware of that, you may see the legacy power status "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Scott Williams Colin Cross Gary King Signed-off-by: Joseph Lo Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/headsmp.S | 60 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'arch/arm/mach-tegra/headsmp.S') diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 93f0370cc95b..82dc84b6b868 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -68,6 +68,55 @@ ENTRY(tegra_secondary_startup) b secondary_startup ENDPROC(tegra_secondary_startup) +#ifdef CONFIG_PM_SLEEP +/* + * tegra_resume + * + * CPU boot vector when restarting the a CPU following + * an LP2 transition. Also branched to by LP0 and LP1 resume after + * re-enabling sdram. + */ +ENTRY(tegra_resume) + bl v7_invalidate_l1 + /* Enable coresight */ + mov32 r0, 0xC5ACCE55 + mcr p14, 0, r0, c7, c12, 6 + + cpu_id r0 + cmp r0, #0 @ CPU0? + bne cpu_resume @ no + +#ifdef CONFIG_ARCH_TEGRA_3x_SOC + /* Are we on Tegra20? */ + mov32 r6, TEGRA_APB_MISC_BASE + ldr r0, [r6, #APB_MISC_GP_HIDREV] + and r0, r0, #0xff00 + cmp r0, #(0x20 << 8) + beq 1f @ Yes + /* Clear the flow controller flags for this CPU. */ + mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR + ldr r1, [r2] + /* Clear event & intr flag */ + orr r1, r1, \ + #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG + movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps + bic r1, r1, r0 + str r1, [r2] +1: +#endif + +#ifdef CONFIG_HAVE_ARM_SCU + /* enable SCU */ + mov32 r0, TEGRA_ARM_PERIF_BASE + ldr r1, [r0] + orr r1, r1, #1 + str r1, [r0] +#endif + + b cpu_resume +ENDPROC(tegra_resume) +#endif + .align L1_CACHE_SHIFT ENTRY(__tegra_cpu_reset_handler_start) @@ -121,6 +170,17 @@ ENTRY(__tegra_cpu_reset_handler) 1: #endif + /* Waking up from LP2? */ + ldr r9, [r12, #RESET_DATA(MASK_LP2)] + tst r9, r11 @ if in_lp2 + beq __is_not_lp2 + ldr lr, [r12, #RESET_DATA(STARTUP_LP2)] + cmp lr, #0 + bleq __die @ no LP2 startup handler + bx lr + +__is_not_lp2: + #ifdef CONFIG_SMP /* * Can only be secondary boot (initial or hotplug) but CPU 0 -- cgit v1.2.1 From 29a0e7beab8e05be53d5b9c050253a4dc417041e Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Tue, 13 Nov 2012 10:04:48 +0800 Subject: ARM: tegra: retain L2 content over CPU suspend/resume The L2 RAM is in different power domain from the CPU cluster. So the L2 content can be retained over CPU suspend/resume. To do that, we need to disable L2 after the MMU is disabled, and enable L2 before the MMU is enabled. But the L2 controller is in the same power domain with the CPU cluster. We need to restore it's settings and re-enable it after the power be resumed. Signed-off-by: Joseph Lo Acked-by: Peter De Schrijver Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/headsmp.S | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/mach-tegra/headsmp.S') diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 82dc84b6b868..4a317fae6860 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -2,6 +2,8 @@ #include #include +#include +#include #include "flowctrl.h" #include "iomap.h" @@ -113,10 +115,19 @@ ENTRY(tegra_resume) str r1, [r0] #endif + /* L2 cache resume & re-enable */ + l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr + b cpu_resume ENDPROC(tegra_resume) #endif +#ifdef CONFIG_CACHE_L2X0 + .globl l2x0_saved_regs_addr +l2x0_saved_regs_addr: + .long 0 +#endif + .align L1_CACHE_SHIFT ENTRY(__tegra_cpu_reset_handler_start) -- cgit v1.2.1