From e8a3931d5fb862c0bd21c81b363b729a263dc8d3 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 18 May 2010 16:43:45 +0900 Subject: ARM: S5P6442: Define SPI platform devices Define SPI platform devices for the SoC. Signed-off-by: Jassi Brar Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6442/dev-spi.c | 123 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 arch/arm/mach-s5p6442/dev-spi.c (limited to 'arch/arm/mach-s5p6442/dev-spi.c') diff --git a/arch/arm/mach-s5p6442/dev-spi.c b/arch/arm/mach-s5p6442/dev-spi.c new file mode 100644 index 000000000000..30199525daca --- /dev/null +++ b/arch/arm/mach-s5p6442/dev-spi.c @@ -0,0 +1,123 @@ +/* linux/arch/arm/mach-s5p6442/dev-spi.c + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +static char *spi_src_clks[] = { + [S5P6442_SPI_SRCCLK_PCLK] = "pclk", + [S5P6442_SPI_SRCCLK_SCLK] = "spi_epll", +}; + +/* SPI Controller platform_devices */ + +/* Since we emulate multi-cs capability, we do not touch the CS. + * The emulated CS is toggled by board specific mechanism, as it can + * be either some immediate GPIO or some signal out of some other + * chip in between ... or some yet another way. + * We simply do not assume anything about CS. + */ +static int s5p6442_spi_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin(S5P6442_GPB(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6442_GPB(2), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6442_GPB(3), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5P6442_GPB(0), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5P6442_GPB(2), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5P6442_GPB(3), S3C_GPIO_PULL_UP); + break; + + default: + dev_err(&pdev->dev, "Invalid SPI Controller number!"); + return -EINVAL; + } + + return 0; +} + +static struct resource s5p6442_spi0_resource[] = { + [0] = { + .start = S5P6442_PA_SPI, + .end = S5P6442_PA_SPI + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPI0_TX, + .end = DMACH_SPI0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_SPI0_RX, + .end = DMACH_SPI0_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = IRQ_SPI0, + .end = IRQ_SPI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c64xx_spi_info s5p6442_spi0_pdata = { + .cfg_gpio = s5p6442_spi_cfg_gpio, + .fifo_lvl_mask = 0x1ff, + .rx_lvl_offset = 15, +}; + +static u64 spi_dmamask = DMA_BIT_MASK(32); + +struct platform_device s5p6442_device_spi = { + .name = "s3c64xx-spi", + .id = 0, + .num_resources = ARRAY_SIZE(s5p6442_spi0_resource), + .resource = s5p6442_spi0_resource, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5p6442_spi0_pdata, + }, +}; + +void __init s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) +{ + struct s3c64xx_spi_info *pd; + + /* Reject invalid configuration */ + if (!num_cs || src_clk_nr < 0 + || src_clk_nr > S5P6442_SPI_SRCCLK_SCLK) { + printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); + return; + } + + switch (cntrlr) { + case 0: + pd = &s5p6442_spi0_pdata; + break; + default: + printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", + __func__, cntrlr); + return; + } + + pd->num_cs = num_cs; + pd->src_clk_nr = src_clk_nr; + pd->src_clk_name = spi_src_clks[src_clk_nr]; +} -- cgit v1.2.1