From 6e01478ae8a4322c9a2b2d6efed50196265ed5f2 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Dec 2010 20:01:20 -0700 Subject: OMAP2+: powerdomains: move powerdomain static data to .c files Static data should be declared in .c files, not .h files. It should be possible to #include .h files at any point without creating multiple copies of the same data. We converted the clock data to .c files some time ago. This patch does the same for the powerdomain data. Signed-off-by: Paul Walmsley Cc: Rajendra Nayak Cc: Santosh Shilimkar Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Tested-by: Santosh Shilimkar Tested-by: Rajendra Nayak --- arch/arm/mach-omap2/Makefile | 13 +- arch/arm/mach-omap2/io.c | 21 +- arch/arm/mach-omap2/powerdomain2xxx_3xxx.c | 7 +- arch/arm/mach-omap2/powerdomain44xx.c | 1 + arch/arm/mach-omap2/powerdomains.h | 9 +- arch/arm/mach-omap2/powerdomains24xx.h | 115 -------- arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c | 81 ++++++ arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h | 22 ++ arch/arm/mach-omap2/powerdomains2xxx_data.c | 126 +++++++++ arch/arm/mach-omap2/powerdomains34xx.h | 267 ------------------ arch/arm/mach-omap2/powerdomains3xxx_data.c | 288 +++++++++++++++++++ arch/arm/mach-omap2/powerdomains44xx.h | 319 --------------------- arch/arm/mach-omap2/powerdomains44xx_data.c | 340 +++++++++++++++++++++++ arch/arm/mach-omap2/powerdomains_data.c | 159 ----------- 14 files changed, 893 insertions(+), 875 deletions(-) delete mode 100644 arch/arm/mach-omap2/powerdomains24xx.h create mode 100644 arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c create mode 100644 arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h create mode 100644 arch/arm/mach-omap2/powerdomains2xxx_data.c delete mode 100644 arch/arm/mach-omap2/powerdomains34xx.h create mode 100644 arch/arm/mach-omap2/powerdomains3xxx_data.c delete mode 100644 arch/arm/mach-omap2/powerdomains44xx.h create mode 100644 arch/arm/mach-omap2/powerdomains44xx_data.c delete mode 100644 arch/arm/mach-omap2/powerdomains_data.c (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 1a1e978cd4bf..4d6fa15f3b62 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -78,13 +78,18 @@ obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm.o obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm4xxx.o # OMAP powerdomain framework -powerdomain-common += powerdomain.o powerdomains_data.o powerdomain-common.o +powerdomain-common += powerdomain.o powerdomain-common.o obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common) \ - powerdomain2xxx_3xxx.o + powerdomain2xxx_3xxx.o \ + powerdomains2xxx_data.o \ + powerdomains2xxx_3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common) \ - powerdomain2xxx_3xxx.o + powerdomain2xxx_3xxx.o \ + powerdomains3xxx_data.o \ + powerdomains2xxx_3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \ - powerdomain44xx.o + powerdomain44xx.o \ + powerdomains44xx_data.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \ diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 80a8e0e4d038..40a548b203e3 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -339,18 +339,25 @@ void __init omap2_init_common_infrastructure(void) { u8 postsetup_state; - pwrdm_fw_init(); - clkdm_init(clockdomains_omap, clkdm_autodeps); - if (cpu_is_omap242x()) + if (cpu_is_omap242x()) { + omap2xxx_powerdomains_init(); + clkdm_init(clockdomains_omap, clkdm_autodeps); omap2420_hwmod_init(); - else if (cpu_is_omap243x()) + } else if (cpu_is_omap243x()) { + omap2xxx_powerdomains_init(); + clkdm_init(clockdomains_omap, clkdm_autodeps); omap2430_hwmod_init(); - else if (cpu_is_omap34xx()) + } else if (cpu_is_omap34xx()) { + omap3xxx_powerdomains_init(); + clkdm_init(clockdomains_omap, clkdm_autodeps); omap3xxx_hwmod_init(); - else if (cpu_is_omap44xx()) + } else if (cpu_is_omap44xx()) { + omap44xx_powerdomains_init(); + clkdm_init(clockdomains_omap, clkdm_autodeps); omap44xx_hwmod_init(); - else + } else { pr_err("Could not init hwmod data - unknown SoC\n"); + } /* Set the default postsetup state for all hwmods */ #ifdef CONFIG_PM_RUNTIME diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c index 6cdf67860cb3..838ac758c513 100644 --- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c @@ -15,10 +15,15 @@ #include #include #include + #include -#include "prm.h" + #include "prm-regbits-34xx.h" #include "powerdomains.h" +#include "prm.h" +#include "prm-regbits-24xx.h" +#include "prm-regbits-34xx.h" + /* Common functions across OMAP2 and OMAP3 */ static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c index 2903c7cb2d5e..366e8693ba56 100644 --- a/arch/arm/mach-omap2/powerdomain44xx.c +++ b/arch/arm/mach-omap2/powerdomain44xx.c @@ -15,6 +15,7 @@ #include #include #include + #include #include #include "prm.h" diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h index 55cd8e6aa104..f83adaf889ee 100644 --- a/arch/arm/mach-omap2/powerdomains.h +++ b/arch/arm/mach-omap2/powerdomains.h @@ -10,8 +10,8 @@ * published by the Free Software Foundation. */ -#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS -#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS +#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS_H +#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS_H #include @@ -24,4 +24,7 @@ extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank); extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank); extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); -#endif /* ARCH_ARM_MACH_OMAP2_POWERDOMAINS */ +extern struct powerdomain wkup_omap2_pwrdm; +extern struct powerdomain gfx_omap2_pwrdm; + +#endif diff --git a/arch/arm/mach-omap2/powerdomains24xx.h b/arch/arm/mach-omap2/powerdomains24xx.h deleted file mode 100644 index 775093add9b6..000000000000 --- a/arch/arm/mach-omap2/powerdomains24xx.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * OMAP24XX powerdomain definitions - * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2009 Nokia Corporation - * - * Written by Paul Walmsley - * Debugging and integration fixes by Jouni Högander - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX -#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX - -/* - * N.B. If powerdomains are added or removed from this file, update - * the array in mach-omap2/powerdomains.h. - */ - -#include - -#include "prcm-common.h" -#include "prm.h" -#include "prm-regbits-24xx.h" -#include "cm.h" -#include "cm-regbits-24xx.h" - -/* 24XX powerdomains and dependencies */ - -#ifdef CONFIG_ARCH_OMAP2 - -/* Powerdomains */ - -static struct powerdomain dsp_pwrdm = { - .name = "dsp_pwrdm", - .prcm_offs = OMAP24XX_DSP_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRDM_POWER_RET, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_RET, - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, - }, -}; - -static struct powerdomain mpu_24xx_pwrdm = { - .name = "mpu_pwrdm", - .prcm_offs = MPU_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_RET, - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, - }, -}; - -static struct powerdomain core_24xx_pwrdm = { - .name = "core_pwrdm", - .prcm_offs = CORE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), - .pwrsts = PWRSTS_OFF_RET_ON, - .banks = 3, - .pwrsts_mem_ret = { - [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ - [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ - [2] = PWRSTS_OFF_RET, /* MEM3RETSTATE */ - }, - .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ - [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ - [2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */ - }, -}; - -#endif /* CONFIG_ARCH_OMAP2 */ - - - -/* - * 2430-specific powerdomains - */ - -#ifdef CONFIG_ARCH_OMAP2430 - -/* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */ - -static struct powerdomain mdm_pwrdm = { - .name = "mdm_pwrdm", - .prcm_offs = OMAP2430_MDM_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRDM_POWER_RET, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* MEMONSTATE */ - }, -}; - -#endif /* CONFIG_ARCH_OMAP2430 */ - - -#endif diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c new file mode 100644 index 000000000000..14c6ef7e01e3 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c @@ -0,0 +1,81 @@ +/* + * OMAP2/3 common powerdomain definitions + * + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2010 Nokia Corporation + * + * Paul Walmsley, Jouni Högander + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * To Do List + * -> Move the Sleep/Wakeup dependencies from Power Domain framework to + * Clock Domain Framework + */ + +/* + * This file contains all of the powerdomains that have some element + * of software control for the OMAP24xx and OMAP34xx chips. + * + * This is not an exhaustive listing of powerdomains on the chips; only + * powerdomains that can be controlled in software. + */ + +/* + * The names for the DSP/IVA2 powerdomains are confusing. + * + * Most OMAP chips have an on-board DSP. + * + * On the 2420, this is a 'C55 DSP called, simply, the DSP. Its + * powerdomain is called the "DSP power domain." On the 2430, the + * on-board DSP is a 'C64 DSP, now called (along with its hardware + * accelerators) the IVA2 or IVA2.1. Its powerdomain is still called + * the "DSP power domain." On the 3430, the DSP is a 'C64 DSP like the + * 2430, also known as the IVA2; but its powerdomain is now called the + * "IVA2 power domain." + * + * The 2420 also has something called the IVA, which is a separate ARM + * core, and has nothing to do with the DSP/IVA2. + * + * Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM + * address offset is different between the C55 and C64 DSPs. + */ + +#include + +#include "prcm-common.h" +#include "prm.h" + +#include "powerdomains.h" + +/* OMAP2/3-common powerdomains */ + +/* + * The GFX powerdomain is not present on 3430ES2, but currently we do not + * have a macro to filter it out at compile-time. + */ +struct powerdomain gfx_omap2_pwrdm = { + .name = "gfx_pwrdm", + .prcm_offs = GFX_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | + CHIP_IS_OMAP3430ES1), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRDM_POWER_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* MEMONSTATE */ + }, +}; + +struct powerdomain wkup_omap2_pwrdm = { + .name = "wkup_pwrdm", + .prcm_offs = WKUP_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), +}; diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h new file mode 100644 index 000000000000..45d684a3bf2b --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h @@ -0,0 +1,22 @@ +/* + * OMAP2/3 common powerdomains - prototypes + * + * Copyright (C) 2008 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H +#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H + +#include + +extern struct powerdomain gfx_omap2_pwrdm; +extern struct powerdomain wkup_omap2_pwrdm; + +#endif diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c new file mode 100644 index 000000000000..adc85d359289 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c @@ -0,0 +1,126 @@ +/* + * OMAP2XXX powerdomain definitions + * + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2010 Nokia Corporation + * + * Paul Walmsley, Jouni Högander + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +#include +#include "powerdomains2xxx_3xxx_data.h" +#include "powerdomains.h" + +#include "prcm-common.h" +#include "prm.h" +#include "prm-regbits-24xx.h" +#include "cm.h" +#include "cm-regbits-24xx.h" + +/* 24XX powerdomains and dependencies */ + +/* Powerdomains */ + +static struct powerdomain dsp_pwrdm = { + .name = "dsp_pwrdm", + .prcm_offs = OMAP24XX_DSP_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRDM_POWER_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, + }, +}; + +static struct powerdomain mpu_24xx_pwrdm = { + .name = "mpu_pwrdm", + .prcm_offs = MPU_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, + }, +}; + +static struct powerdomain core_24xx_pwrdm = { + .name = "core_pwrdm", + .prcm_offs = CORE_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), + .pwrsts = PWRSTS_OFF_RET_ON, + .banks = 3, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ + [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ + [2] = PWRSTS_OFF_RET, /* MEM3RETSTATE */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ + [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ + [2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */ + }, +}; + + +/* + * 2430-specific powerdomains + */ + +#ifdef CONFIG_ARCH_OMAP2430 + +/* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */ + +static struct powerdomain mdm_pwrdm = { + .name = "mdm_pwrdm", + .prcm_offs = OMAP2430_MDM_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRDM_POWER_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* MEMONSTATE */ + }, +}; + +#endif /* CONFIG_ARCH_OMAP2430 */ + +/* As powerdomains are added or removed above, this list must also be changed */ +static struct powerdomain *powerdomains_omap2xxx[] __initdata = { + + &wkup_omap2_pwrdm, + &gfx_omap2_pwrdm, + +#ifdef CONFIG_ARCH_OMAP2 + &dsp_pwrdm, + &mpu_24xx_pwrdm, + &core_24xx_pwrdm, +#endif + +#ifdef CONFIG_ARCH_OMAP2430 + &mdm_pwrdm, +#endif + NULL +}; + +void __init omap2xxx_powerdomains_init(void) +{ + pwrdm_init(powerdomains_omap2xxx, &omap2_pwrdm_operations); +} diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h deleted file mode 100644 index ce5c15bc41b8..000000000000 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ /dev/null @@ -1,267 +0,0 @@ -/* - * OMAP3 powerdomain definitions - * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2010 Nokia Corporation - * - * Written by Paul Walmsley - * Debugging and integration fixes by Jouni Högander - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX -#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX - -/* - * N.B. If powerdomains are added or removed from this file, update - * the array in mach-omap2/powerdomains.h. - */ - -#include - -#include "prcm-common.h" -#include "prm.h" -#include "prm-regbits-34xx.h" -#include "cm.h" -#include "cm-regbits-34xx.h" - -/* - * 34XX-specific powerdomains, dependencies - */ - -#ifdef CONFIG_ARCH_OMAP3 - -/* - * Powerdomains - */ - -static struct powerdomain iva2_pwrdm = { - .name = "iva2_pwrdm", - .prcm_offs = OMAP3430_IVA2_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .banks = 4, - .pwrsts_mem_ret = { - [0] = PWRSTS_OFF_RET, - [1] = PWRSTS_OFF_RET, - [2] = PWRSTS_OFF_RET, - [3] = PWRSTS_OFF_RET, - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, - [1] = PWRDM_POWER_ON, - [2] = PWRSTS_OFF_ON, - [3] = PWRDM_POWER_ON, - }, -}; - -static struct powerdomain mpu_3xxx_pwrdm = { - .name = "mpu_pwrdm", - .prcm_offs = MPU_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .flags = PWRDM_HAS_MPU_QUIRK, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRSTS_OFF_RET, - }, - .pwrsts_mem_on = { - [0] = PWRSTS_OFF_ON, - }, -}; - -/* - * The USBTLL Save-and-Restore mechanism is broken on - * 3430s upto ES3.0 and 3630ES1.0. Hence this feature - * needs to be disabled on these chips. - * Refer: 3430 errata ID i459 and 3630 errata ID i579 - * - * Note: setting the SAR flag could help for errata ID i478 - * which applies to 3430 <= ES3.1, but since the SAR feature - * is broken, do not use it. - */ -static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { - .name = "core_pwrdm", - .prcm_offs = CORE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | - CHIP_IS_OMAP3430ES2 | - CHIP_IS_OMAP3430ES3_0 | - CHIP_IS_OMAP3630ES1), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .banks = 2, - .pwrsts_mem_ret = { - [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ - [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ - }, - .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ - [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ - }, -}; - -static struct powerdomain core_3xxx_es3_1_pwrdm = { - .name = "core_pwrdm", - .prcm_offs = CORE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 | - CHIP_GE_OMAP3630ES1_1), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - /* - * Setting the SAR flag for errata ID i478 which applies - * to 3430 <= ES3.1 - */ - .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ - .banks = 2, - .pwrsts_mem_ret = { - [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ - [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ - }, - .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ - [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ - }, -}; - -static struct powerdomain dss_pwrdm = { - .name = "dss_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), - .prcm_offs = OMAP3430_DSS_MOD, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRDM_POWER_RET, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* MEMONSTATE */ - }, -}; - -/* - * Although the 34XX TRM Rev K Table 4-371 notes that retention is a - * possible SGX powerstate, the SGX device itself does not support - * retention. - */ -static struct powerdomain sgx_pwrdm = { - .name = "sgx_pwrdm", - .prcm_offs = OMAP3430ES2_SGX_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), - /* XXX This is accurate for 3430 SGX, but what about GFX? */ - .pwrsts = PWRSTS_OFF_ON, - .pwrsts_logic_ret = PWRDM_POWER_RET, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* MEMONSTATE */ - }, -}; - -static struct powerdomain cam_pwrdm = { - .name = "cam_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), - .prcm_offs = OMAP3430_CAM_MOD, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRDM_POWER_RET, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* MEMONSTATE */ - }, -}; - -static struct powerdomain per_pwrdm = { - .name = "per_pwrdm", - .prcm_offs = OMAP3430_PER_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* MEMONSTATE */ - }, -}; - -static struct powerdomain emu_pwrdm = { - .name = "emu_pwrdm", - .prcm_offs = OMAP3430_EMU_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct powerdomain neon_pwrdm = { - .name = "neon_pwrdm", - .prcm_offs = OMAP3430_NEON_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRDM_POWER_RET, -}; - -static struct powerdomain usbhost_pwrdm = { - .name = "usbhost_pwrdm", - .prcm_offs = OMAP3430ES2_USBHOST_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRDM_POWER_RET, - /* - * REVISIT: Enabling usb host save and restore mechanism seems to - * leave the usb host domain permanently in ACTIVE mode after - * changing the usb host power domain state from OFF to active once. - * Disabling for now. - */ - /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */ - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* MEMONSTATE */ - }, -}; - -static struct powerdomain dpll1_pwrdm = { - .name = "dpll1_pwrdm", - .prcm_offs = MPU_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct powerdomain dpll2_pwrdm = { - .name = "dpll2_pwrdm", - .prcm_offs = OMAP3430_IVA2_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct powerdomain dpll3_pwrdm = { - .name = "dpll3_pwrdm", - .prcm_offs = PLL_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct powerdomain dpll4_pwrdm = { - .name = "dpll4_pwrdm", - .prcm_offs = PLL_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct powerdomain dpll5_pwrdm = { - .name = "dpll5_pwrdm", - .prcm_offs = PLL_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), -}; - - -#endif /* CONFIG_ARCH_OMAP3 */ - - -#endif diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c new file mode 100644 index 000000000000..1ddc040d7bc0 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -0,0 +1,288 @@ +/* + * OMAP3 powerdomain definitions + * + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2010 Nokia Corporation + * + * Paul Walmsley, Jouni Högander + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +#include +#include "powerdomains2xxx_3xxx_data.h" +#include "powerdomains.h" + +#include "prcm-common.h" +#include "prm.h" +#include "prm-regbits-34xx.h" +#include "cm.h" +#include "cm-regbits-34xx.h" + +/* + * 34XX-specific powerdomains, dependencies + */ + +#ifdef CONFIG_ARCH_OMAP3 + +/* + * Powerdomains + */ + +static struct powerdomain iva2_pwrdm = { + .name = "iva2_pwrdm", + .prcm_offs = OMAP3430_IVA2_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 4, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, + [1] = PWRSTS_OFF_RET, + [2] = PWRSTS_OFF_RET, + [3] = PWRSTS_OFF_RET, + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, + [1] = PWRDM_POWER_ON, + [2] = PWRSTS_OFF_ON, + [3] = PWRDM_POWER_ON, + }, +}; + +static struct powerdomain mpu_3xxx_pwrdm = { + .name = "mpu_pwrdm", + .prcm_offs = MPU_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .flags = PWRDM_HAS_MPU_QUIRK, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_ON, + }, +}; + +/* + * The USBTLL Save-and-Restore mechanism is broken on + * 3430s upto ES3.0 and 3630ES1.0. Hence this feature + * needs to be disabled on these chips. + * Refer: 3430 errata ID i459 and 3630 errata ID i579 + * + * Note: setting the SAR flag could help for errata ID i478 + * which applies to 3430 <= ES3.1, but since the SAR feature + * is broken, do not use it. + */ +static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { + .name = "core_pwrdm", + .prcm_offs = CORE_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_IS_OMAP3430ES2 | + CHIP_IS_OMAP3430ES3_0 | + CHIP_IS_OMAP3630ES1), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ + [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ + [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ + }, +}; + +static struct powerdomain core_3xxx_es3_1_pwrdm = { + .name = "core_pwrdm", + .prcm_offs = CORE_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 | + CHIP_GE_OMAP3630ES1_1), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + /* + * Setting the SAR flag for errata ID i478 which applies + * to 3430 <= ES3.1 + */ + .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ + [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ + [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ + }, +}; + +static struct powerdomain dss_pwrdm = { + .name = "dss_pwrdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .prcm_offs = OMAP3430_DSS_MOD, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRDM_POWER_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* MEMONSTATE */ + }, +}; + +/* + * Although the 34XX TRM Rev K Table 4-371 notes that retention is a + * possible SGX powerstate, the SGX device itself does not support + * retention. + */ +static struct powerdomain sgx_pwrdm = { + .name = "sgx_pwrdm", + .prcm_offs = OMAP3430ES2_SGX_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), + /* XXX This is accurate for 3430 SGX, but what about GFX? */ + .pwrsts = PWRSTS_OFF_ON, + .pwrsts_logic_ret = PWRDM_POWER_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* MEMONSTATE */ + }, +}; + +static struct powerdomain cam_pwrdm = { + .name = "cam_pwrdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .prcm_offs = OMAP3430_CAM_MOD, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRDM_POWER_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* MEMONSTATE */ + }, +}; + +static struct powerdomain per_pwrdm = { + .name = "per_pwrdm", + .prcm_offs = OMAP3430_PER_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* MEMONSTATE */ + }, +}; + +static struct powerdomain emu_pwrdm = { + .name = "emu_pwrdm", + .prcm_offs = OMAP3430_EMU_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +static struct powerdomain neon_pwrdm = { + .name = "neon_pwrdm", + .prcm_offs = OMAP3430_NEON_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRDM_POWER_RET, +}; + +static struct powerdomain usbhost_pwrdm = { + .name = "usbhost_pwrdm", + .prcm_offs = OMAP3430ES2_USBHOST_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRDM_POWER_RET, + /* + * REVISIT: Enabling usb host save and restore mechanism seems to + * leave the usb host domain permanently in ACTIVE mode after + * changing the usb host power domain state from OFF to active once. + * Disabling for now. + */ + /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */ + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* MEMONSTATE */ + }, +}; + +static struct powerdomain dpll1_pwrdm = { + .name = "dpll1_pwrdm", + .prcm_offs = MPU_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +static struct powerdomain dpll2_pwrdm = { + .name = "dpll2_pwrdm", + .prcm_offs = OMAP3430_IVA2_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +static struct powerdomain dpll3_pwrdm = { + .name = "dpll3_pwrdm", + .prcm_offs = PLL_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +static struct powerdomain dpll4_pwrdm = { + .name = "dpll4_pwrdm", + .prcm_offs = PLL_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +static struct powerdomain dpll5_pwrdm = { + .name = "dpll5_pwrdm", + .prcm_offs = PLL_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), +}; + +/* As powerdomains are added or removed above, this list must also be changed */ +static struct powerdomain *powerdomains_omap3xxx[] __initdata = { + + &wkup_omap2_pwrdm, + &gfx_omap2_pwrdm, + &iva2_pwrdm, + &mpu_3xxx_pwrdm, + &neon_pwrdm, + &core_3xxx_pre_es3_1_pwrdm, + &core_3xxx_es3_1_pwrdm, + &cam_pwrdm, + &dss_pwrdm, + &per_pwrdm, + &emu_pwrdm, + &sgx_pwrdm, + &usbhost_pwrdm, + &dpll1_pwrdm, + &dpll2_pwrdm, + &dpll3_pwrdm, + &dpll4_pwrdm, + &dpll5_pwrdm, +#endif + NULL +}; + + +void __init omap3xxx_powerdomains_init(void) +{ + pwrdm_init(powerdomains_omap3xxx, &omap3_pwrdm_operations); +} diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h deleted file mode 100644 index 9c01b55d6102..000000000000 --- a/arch/arm/mach-omap2/powerdomains44xx.h +++ /dev/null @@ -1,319 +0,0 @@ -/* - * OMAP4 Power domains framework - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * Copyright (C) 2009-2010 Nokia Corporation - * - * Abhijit Pagare (abhijitpagare@ti.com) - * Benoit Cousson (b-cousson@ti.com) - * Paul Walmsley (paul@pwsan.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H -#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H - -#include - -#include "prcm-common.h" -#include "cm.h" -#include "cm-regbits-44xx.h" -#include "prm.h" -#include "prm-regbits-44xx.h" - -#if defined(CONFIG_ARCH_OMAP4) - -/* core_44xx_pwrdm: CORE power domain */ -static struct powerdomain core_44xx_pwrdm = { - .name = "core_pwrdm", - .prcm_offs = OMAP4430_PRM_CORE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .banks = 5, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_OFF, /* core_nret_bank */ - [1] = PWRSTS_OFF_RET, /* core_ocmram */ - [2] = PWRDM_POWER_RET, /* core_other_bank */ - [3] = PWRSTS_OFF_RET, /* ducati_l2ram */ - [4] = PWRSTS_OFF_RET, /* ducati_unicache */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* core_nret_bank */ - [1] = PWRSTS_OFF_RET, /* core_ocmram */ - [2] = PWRDM_POWER_ON, /* core_other_bank */ - [3] = PWRDM_POWER_ON, /* ducati_l2ram */ - [4] = PWRDM_POWER_ON, /* ducati_unicache */ - }, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, -}; - -/* gfx_44xx_pwrdm: 3D accelerator power domain */ -static struct powerdomain gfx_44xx_pwrdm = { - .name = "gfx_pwrdm", - .prcm_offs = OMAP4430_PRM_GFX_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_ON, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_OFF, /* gfx_mem */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* gfx_mem */ - }, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, -}; - -/* abe_44xx_pwrdm: Audio back end power domain */ -static struct powerdomain abe_44xx_pwrdm = { - .name = "abe_pwrdm", - .prcm_offs = OMAP4430_PRM_ABE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRDM_POWER_OFF, - .banks = 2, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_RET, /* aessmem */ - [1] = PWRDM_POWER_OFF, /* periphmem */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* aessmem */ - [1] = PWRDM_POWER_ON, /* periphmem */ - }, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, -}; - -/* dss_44xx_pwrdm: Display subsystem power domain */ -static struct powerdomain dss_44xx_pwrdm = { - .name = "dss_pwrdm", - .prcm_offs = OMAP4430_PRM_DSS_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_OFF, /* dss_mem */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* dss_mem */ - }, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, -}; - -/* tesla_44xx_pwrdm: Tesla processor power domain */ -static struct powerdomain tesla_44xx_pwrdm = { - .name = "tesla_pwrdm", - .prcm_offs = OMAP4430_PRM_TESLA_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .banks = 3, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_RET, /* tesla_edma */ - [1] = PWRSTS_OFF_RET, /* tesla_l1 */ - [2] = PWRSTS_OFF_RET, /* tesla_l2 */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* tesla_edma */ - [1] = PWRDM_POWER_ON, /* tesla_l1 */ - [2] = PWRDM_POWER_ON, /* tesla_l2 */ - }, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, -}; - -/* wkup_44xx_pwrdm: Wake-up power domain */ -static struct powerdomain wkup_44xx_pwrdm = { - .name = "wkup_pwrdm", - .prcm_offs = OMAP4430_PRM_WKUP_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_ON, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_OFF, /* wkup_bank */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* wkup_bank */ - }, -}; - -/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ -static struct powerdomain cpu0_44xx_pwrdm = { - .name = "cpu0_pwrdm", - .prcm_offs = OMAP4430_PRCM_MPU_CPU0_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* cpu0_l1 */ - }, -}; - -/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ -static struct powerdomain cpu1_44xx_pwrdm = { - .name = "cpu1_pwrdm", - .prcm_offs = OMAP4430_PRCM_MPU_CPU1_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* cpu1_l1 */ - }, -}; - -/* emu_44xx_pwrdm: Emulation power domain */ -static struct powerdomain emu_44xx_pwrdm = { - .name = "emu_pwrdm", - .prcm_offs = OMAP4430_PRM_EMU_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_ON, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_OFF, /* emu_bank */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* emu_bank */ - }, -}; - -/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */ -static struct powerdomain mpu_44xx_pwrdm = { - .name = "mpu_pwrdm", - .prcm_offs = OMAP4430_PRM_MPU_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .banks = 3, - .pwrsts_mem_ret = { - [0] = PWRSTS_OFF_RET, /* mpu_l1 */ - [1] = PWRSTS_OFF_RET, /* mpu_l2 */ - [2] = PWRDM_POWER_RET, /* mpu_ram */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* mpu_l1 */ - [1] = PWRDM_POWER_ON, /* mpu_l2 */ - [2] = PWRDM_POWER_ON, /* mpu_ram */ - }, -}; - -/* ivahd_44xx_pwrdm: IVA-HD power domain */ -static struct powerdomain ivahd_44xx_pwrdm = { - .name = "ivahd_pwrdm", - .prcm_offs = OMAP4430_PRM_IVAHD_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRDM_POWER_OFF, - .banks = 4, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_OFF, /* hwa_mem */ - [1] = PWRSTS_OFF_RET, /* sl2_mem */ - [2] = PWRSTS_OFF_RET, /* tcm1_mem */ - [3] = PWRSTS_OFF_RET, /* tcm2_mem */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* hwa_mem */ - [1] = PWRDM_POWER_ON, /* sl2_mem */ - [2] = PWRDM_POWER_ON, /* tcm1_mem */ - [3] = PWRDM_POWER_ON, /* tcm2_mem */ - }, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, -}; - -/* cam_44xx_pwrdm: Camera subsystem power domain */ -static struct powerdomain cam_44xx_pwrdm = { - .name = "cam_pwrdm", - .prcm_offs = OMAP4430_PRM_CAM_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_ON, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_OFF, /* cam_mem */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* cam_mem */ - }, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, -}; - -/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ -static struct powerdomain l3init_44xx_pwrdm = { - .name = "l3init_pwrdm", - .prcm_offs = OMAP4430_PRM_L3INIT_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_OFF, /* l3init_bank1 */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* l3init_bank1 */ - }, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, -}; - -/* l4per_44xx_pwrdm: Target peripherals power domain */ -static struct powerdomain l4per_44xx_pwrdm = { - .name = "l4per_pwrdm", - .prcm_offs = OMAP4430_PRM_L4PER_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .banks = 2, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_OFF, /* nonretained_bank */ - [1] = PWRDM_POWER_RET, /* retained_bank */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* nonretained_bank */ - [1] = PWRDM_POWER_ON, /* retained_bank */ - }, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, -}; - -/* - * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage - * domain - */ -static struct powerdomain always_on_core_44xx_pwrdm = { - .name = "always_on_core_pwrdm", - .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_ON, -}; - -/* cefuse_44xx_pwrdm: Customer efuse controller power domain */ -static struct powerdomain cefuse_44xx_pwrdm = { - .name = "cefuse_pwrdm", - .prcm_offs = OMAP4430_PRM_CEFUSE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - .pwrsts = PWRSTS_OFF_ON, -}; - -/* - * The following power domains are not under SW control - * - * always_on_iva - * always_on_mpu - * stdefuse - */ - -#endif - -#endif diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c new file mode 100644 index 000000000000..2512f69fd9c7 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains44xx_data.c @@ -0,0 +1,340 @@ +/* + * OMAP4 Power domains framework + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Abhijit Pagare (abhijitpagare@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Paul Walmsley (paul@pwsan.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +#include +#include "powerdomains.h" + +#include "prcm-common.h" +#include "cm.h" +#include "cm-regbits-44xx.h" +#include "prm.h" +#include "prm-regbits-44xx.h" + +/* core_44xx_pwrdm: CORE power domain */ +static struct powerdomain core_44xx_pwrdm = { + .name = "core_pwrdm", + .prcm_offs = OMAP4430_PRM_CORE_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 5, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* core_nret_bank */ + [1] = PWRSTS_OFF_RET, /* core_ocmram */ + [2] = PWRDM_POWER_RET, /* core_other_bank */ + [3] = PWRSTS_OFF_RET, /* ducati_l2ram */ + [4] = PWRSTS_OFF_RET, /* ducati_unicache */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* core_nret_bank */ + [1] = PWRSTS_OFF_RET, /* core_ocmram */ + [2] = PWRDM_POWER_ON, /* core_other_bank */ + [3] = PWRDM_POWER_ON, /* ducati_l2ram */ + [4] = PWRDM_POWER_ON, /* ducati_unicache */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* gfx_44xx_pwrdm: 3D accelerator power domain */ +static struct powerdomain gfx_44xx_pwrdm = { + .name = "gfx_pwrdm", + .prcm_offs = OMAP4430_PRM_GFX_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* gfx_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* gfx_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* abe_44xx_pwrdm: Audio back end power domain */ +static struct powerdomain abe_44xx_pwrdm = { + .name = "abe_pwrdm", + .prcm_offs = OMAP4430_PRM_ABE_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRDM_POWER_OFF, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, /* aessmem */ + [1] = PWRDM_POWER_OFF, /* periphmem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* aessmem */ + [1] = PWRDM_POWER_ON, /* periphmem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* dss_44xx_pwrdm: Display subsystem power domain */ +static struct powerdomain dss_44xx_pwrdm = { + .name = "dss_pwrdm", + .prcm_offs = OMAP4430_PRM_DSS_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* dss_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* dss_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* tesla_44xx_pwrdm: Tesla processor power domain */ +static struct powerdomain tesla_44xx_pwrdm = { + .name = "tesla_pwrdm", + .prcm_offs = OMAP4430_PRM_TESLA_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 3, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, /* tesla_edma */ + [1] = PWRSTS_OFF_RET, /* tesla_l1 */ + [2] = PWRSTS_OFF_RET, /* tesla_l2 */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* tesla_edma */ + [1] = PWRDM_POWER_ON, /* tesla_l1 */ + [2] = PWRDM_POWER_ON, /* tesla_l2 */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* wkup_44xx_pwrdm: Wake-up power domain */ +static struct powerdomain wkup_44xx_pwrdm = { + .name = "wkup_pwrdm", + .prcm_offs = OMAP4430_PRM_WKUP_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* wkup_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* wkup_bank */ + }, +}; + +/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ +static struct powerdomain cpu0_44xx_pwrdm = { + .name = "cpu0_pwrdm", + .prcm_offs = OMAP4430_PRCM_MPU_CPU0_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* cpu0_l1 */ + }, +}; + +/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ +static struct powerdomain cpu1_44xx_pwrdm = { + .name = "cpu1_pwrdm", + .prcm_offs = OMAP4430_PRCM_MPU_CPU1_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* cpu1_l1 */ + }, +}; + +/* emu_44xx_pwrdm: Emulation power domain */ +static struct powerdomain emu_44xx_pwrdm = { + .name = "emu_pwrdm", + .prcm_offs = OMAP4430_PRM_EMU_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* emu_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* emu_bank */ + }, +}; + +/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */ +static struct powerdomain mpu_44xx_pwrdm = { + .name = "mpu_pwrdm", + .prcm_offs = OMAP4430_PRM_MPU_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 3, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* mpu_l1 */ + [1] = PWRSTS_OFF_RET, /* mpu_l2 */ + [2] = PWRDM_POWER_RET, /* mpu_ram */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* mpu_l1 */ + [1] = PWRDM_POWER_ON, /* mpu_l2 */ + [2] = PWRDM_POWER_ON, /* mpu_ram */ + }, +}; + +/* ivahd_44xx_pwrdm: IVA-HD power domain */ +static struct powerdomain ivahd_44xx_pwrdm = { + .name = "ivahd_pwrdm", + .prcm_offs = OMAP4430_PRM_IVAHD_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRDM_POWER_OFF, + .banks = 4, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* hwa_mem */ + [1] = PWRSTS_OFF_RET, /* sl2_mem */ + [2] = PWRSTS_OFF_RET, /* tcm1_mem */ + [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* hwa_mem */ + [1] = PWRDM_POWER_ON, /* sl2_mem */ + [2] = PWRDM_POWER_ON, /* tcm1_mem */ + [3] = PWRDM_POWER_ON, /* tcm2_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* cam_44xx_pwrdm: Camera subsystem power domain */ +static struct powerdomain cam_44xx_pwrdm = { + .name = "cam_pwrdm", + .prcm_offs = OMAP4430_PRM_CAM_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* cam_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* cam_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ +static struct powerdomain l3init_44xx_pwrdm = { + .name = "l3init_pwrdm", + .prcm_offs = OMAP4430_PRM_L3INIT_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* l3init_bank1 */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* l3init_bank1 */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* l4per_44xx_pwrdm: Target peripherals power domain */ +static struct powerdomain l4per_44xx_pwrdm = { + .name = "l4per_pwrdm", + .prcm_offs = OMAP4430_PRM_L4PER_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* nonretained_bank */ + [1] = PWRDM_POWER_RET, /* retained_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* nonretained_bank */ + [1] = PWRDM_POWER_ON, /* retained_bank */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* + * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage + * domain + */ +static struct powerdomain always_on_core_44xx_pwrdm = { + .name = "always_on_core_pwrdm", + .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_ON, +}; + +/* cefuse_44xx_pwrdm: Customer efuse controller power domain */ +static struct powerdomain cefuse_44xx_pwrdm = { + .name = "cefuse_pwrdm", + .prcm_offs = OMAP4430_PRM_CEFUSE_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_ON, +}; + +/* + * The following power domains are not under SW control + * + * always_on_iva + * always_on_mpu + * stdefuse + */ + +/* As powerdomains are added or removed above, this list must also be changed */ +static struct powerdomain *powerdomains_omap44xx[] __initdata = { + &core_44xx_pwrdm, + &gfx_44xx_pwrdm, + &abe_44xx_pwrdm, + &dss_44xx_pwrdm, + &tesla_44xx_pwrdm, + &wkup_44xx_pwrdm, + &cpu0_44xx_pwrdm, + &cpu1_44xx_pwrdm, + &emu_44xx_pwrdm, + &mpu_44xx_pwrdm, + &ivahd_44xx_pwrdm, + &cam_44xx_pwrdm, + &l3init_44xx_pwrdm, + &l4per_44xx_pwrdm, + &always_on_core_44xx_pwrdm, + &cefuse_44xx_pwrdm, + NULL +}; + +void __init omap44xx_powerdomains_init(void) +{ + pwrdm_init(powerdomains_omap44xx, &omap4_pwrdm_operations); +} diff --git a/arch/arm/mach-omap2/powerdomains_data.c b/arch/arm/mach-omap2/powerdomains_data.c deleted file mode 100644 index 29690c64bf1e..000000000000 --- a/arch/arm/mach-omap2/powerdomains_data.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * OMAP2/3 common powerdomain definitions - * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2009 Nokia Corporation - * - * Written by Paul Walmsley - * Debugging and integration fixes by Jouni Högander - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * To Do List - * -> Move the Sleep/Wakeup dependencies from Power Domain framework to - * Clock Domain Framework - */ - -/* - * This file contains all of the powerdomains that have some element - * of software control for the OMAP24xx and OMAP34xx chips. - * - * This is not an exhaustive listing of powerdomains on the chips; only - * powerdomains that can be controlled in software. - */ - -/* - * The names for the DSP/IVA2 powerdomains are confusing. - * - * Most OMAP chips have an on-board DSP. - * - * On the 2420, this is a 'C55 DSP called, simply, the DSP. Its - * powerdomain is called the "DSP power domain." On the 2430, the - * on-board DSP is a 'C64 DSP, now called (along with its hardware - * accelerators) the IVA2 or IVA2.1. Its powerdomain is still called - * the "DSP power domain." On the 3430, the DSP is a 'C64 DSP like the - * 2430, also known as the IVA2; but its powerdomain is now called the - * "IVA2 power domain." - * - * The 2420 also has something called the IVA, which is a separate ARM - * core, and has nothing to do with the DSP/IVA2. - * - * Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM - * address offset is different between the C55 and C64 DSPs. - */ - -#include -#include - -#include "prcm-common.h" -#include "prm.h" -#include "cm.h" -#include "powerdomains24xx.h" -#include "powerdomains34xx.h" -#include "powerdomains44xx.h" -#include "powerdomains.h" - -/* OMAP2/3-common powerdomains */ - -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - -/* - * The GFX powerdomain is not present on 3430ES2, but currently we do not - * have a macro to filter it out at compile-time. - */ -static struct powerdomain gfx_omap2_pwrdm = { - .name = "gfx_pwrdm", - .prcm_offs = GFX_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | - CHIP_IS_OMAP3430ES1), - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRDM_POWER_RET, - .banks = 1, - .pwrsts_mem_ret = { - [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ - }, - .pwrsts_mem_on = { - [0] = PWRDM_POWER_ON, /* MEMONSTATE */ - }, -}; - -static struct powerdomain wkup_omap2_pwrdm = { - .name = "wkup_pwrdm", - .prcm_offs = WKUP_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), -}; - -#endif - - -/* As powerdomains are added or removed above, this list must also be changed */ -static struct powerdomain *powerdomains_omap[] __initdata = { - -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - &wkup_omap2_pwrdm, - &gfx_omap2_pwrdm, -#endif - -#ifdef CONFIG_ARCH_OMAP2 - &dsp_pwrdm, - &mpu_24xx_pwrdm, - &core_24xx_pwrdm, -#endif - -#ifdef CONFIG_ARCH_OMAP2430 - &mdm_pwrdm, -#endif - -#ifdef CONFIG_ARCH_OMAP3 - &iva2_pwrdm, - &mpu_3xxx_pwrdm, - &neon_pwrdm, - &core_3xxx_pre_es3_1_pwrdm, - &core_3xxx_es3_1_pwrdm, - &cam_pwrdm, - &dss_pwrdm, - &per_pwrdm, - &emu_pwrdm, - &sgx_pwrdm, - &usbhost_pwrdm, - &dpll1_pwrdm, - &dpll2_pwrdm, - &dpll3_pwrdm, - &dpll4_pwrdm, - &dpll5_pwrdm, -#endif - -#ifdef CONFIG_ARCH_OMAP4 - &core_44xx_pwrdm, - &gfx_44xx_pwrdm, - &abe_44xx_pwrdm, - &dss_44xx_pwrdm, - &tesla_44xx_pwrdm, - &wkup_44xx_pwrdm, - &cpu0_44xx_pwrdm, - &cpu1_44xx_pwrdm, - &emu_44xx_pwrdm, - &mpu_44xx_pwrdm, - &ivahd_44xx_pwrdm, - &cam_44xx_pwrdm, - &l3init_44xx_pwrdm, - &l4per_44xx_pwrdm, - &always_on_core_44xx_pwrdm, - &cefuse_44xx_pwrdm, -#endif - NULL -}; - -void pwrdm_fw_init(void) -{ - if (cpu_is_omap24xx()) - pwrdm_init(powerdomains_omap, &omap2_pwrdm_operations); - else if (cpu_is_omap34xx()) - pwrdm_init(powerdomains_omap, &omap3_pwrdm_operations); - else if (cpu_is_omap44xx()) - pwrdm_init(powerdomains_omap, &omap4_pwrdm_operations); -} -- cgit v1.2.1