From 2f7e8faef5a50efaa1c173e99bdaa29e0129bb99 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 4 Dec 2009 09:41:28 -0500 Subject: [ARM] mmp: add support for Marvell MMP2 Marvell MMP2 (aka ARMADA610) is a SoC based on PJ4 core. It's ARMv6 compatible. Support basic interrupt handler and timer, and basic support for MMP2 based FLINT platform. Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-mmp/irq-mmp2.c | 138 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 arch/arm/mach-mmp/irq-mmp2.c (limited to 'arch/arm/mach-mmp/irq-mmp2.c') diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c new file mode 100644 index 000000000000..dcd36f4bc9de --- /dev/null +++ b/arch/arm/mach-mmp/irq-mmp2.c @@ -0,0 +1,138 @@ +/* + * linux/arch/arm/mach-mmp/irq-mmp2.c + * + * Generic IRQ handling, GPIO IRQ demultiplexing, etc. + * + * Author: Haojian Zhuang + * Copyright: Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "common.h" + +static void icu_mask_irq(unsigned int irq) +{ + uint32_t r = __raw_readl(ICU_INT_CONF(irq)); + + r &= ~ICU_INT_ROUTE_PJ4_IRQ; + __raw_writel(r, ICU_INT_CONF(irq)); +} + +static void icu_unmask_irq(unsigned int irq) +{ + uint32_t r = __raw_readl(ICU_INT_CONF(irq)); + + r |= ICU_INT_ROUTE_PJ4_IRQ; + __raw_writel(r, ICU_INT_CONF(irq)); +} + +static struct irq_chip icu_irq_chip = { + .name = "icu_irq", + .mask_ack = icu_mask_irq, + .unmask = icu_unmask_irq, +}; + +#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \ +static void _name_##_mask_irq(unsigned int irq) \ +{ \ + uint32_t r; \ + r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base)); \ + __raw_writel(r, prefix##_MASK); \ +} + +#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ +static void _name_##_unmask_irq(unsigned int irq) \ +{ \ + uint32_t r; \ + r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base)); \ + __raw_writel(r, prefix##_MASK); \ +} + +#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ +static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \ +{ \ + unsigned long status, mask, n; \ + mask = __raw_readl(prefix##_MASK); \ + while (1) { \ + status = __raw_readl(prefix##_STATUS) & ~mask; \ + if (status == 0) \ + break; \ + n = find_first_bit(&status, BITS_PER_LONG); \ + while (n < BITS_PER_LONG) { \ + generic_handle_irq(irq_base + n); \ + n = find_next_bit(&status, BITS_PER_LONG, n+1); \ + } \ + } \ +} + +#define SECOND_IRQ_CHIP(_name_, irq_base, prefix) \ +SECOND_IRQ_MASK(_name_, irq_base, prefix) \ +SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ +SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ +static struct irq_chip _name_##_irq_chip = { \ + .name = #_name_, \ + .mask_ack = _name_##_mask_irq, \ + .unmask = _name_##_unmask_irq, \ +} + +SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4); +SECOND_IRQ_CHIP(rtc, IRQ_MMP2_RTC_BASE, MMP2_ICU_INT5); +SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17); +SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35); +SECOND_IRQ_CHIP(ssp, IRQ_MMP2_SSP_BASE, MMP2_ICU_INT51); + +static void init_mux_irq(struct irq_chip *chip, int start, int num) +{ + int irq; + + for (irq = start; num > 0; irq++, num--) { + chip->mask_ack(irq); + set_irq_chip(irq, chip); + set_irq_flags(irq, IRQF_VALID); + set_irq_handler(irq, handle_level_irq); + } +} + +void __init mmp2_init_irq(void) +{ + int irq; + + for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { + icu_mask_irq(irq); + set_irq_chip(irq, &icu_irq_chip); + set_irq_flags(irq, IRQF_VALID); + + switch (irq) { + case IRQ_MMP2_PMIC_MUX: + case IRQ_MMP2_RTC_MUX: + case IRQ_MMP2_TWSI_MUX: + case IRQ_MMP2_MISC_MUX: + case IRQ_MMP2_SSP_MUX: + break; + default: + set_irq_handler(irq, handle_level_irq); + break; + } + } + + init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2); + init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2); + init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5); + init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); + init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); + + set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); + set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); + set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); + set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); + set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); +} -- cgit v1.2.1 From 4e3b4da98e20c5dc58e544ac5b321c1942071f7f Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Mon, 25 Jan 2010 06:02:50 -0500 Subject: [ARM] mmp2: add mask function in irq-mmp2.c Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-mmp/irq-mmp2.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-mmp/irq-mmp2.c') diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c index dcd36f4bc9de..ddebde84231a 100644 --- a/arch/arm/mach-mmp/irq-mmp2.c +++ b/arch/arm/mach-mmp/irq-mmp2.c @@ -37,6 +37,7 @@ static void icu_unmask_irq(unsigned int irq) static struct irq_chip icu_irq_chip = { .name = "icu_irq", + .mask = icu_mask_irq, .mask_ack = icu_mask_irq, .unmask = icu_unmask_irq, }; @@ -80,6 +81,7 @@ SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ static struct irq_chip _name_##_irq_chip = { \ .name = #_name_, \ + .mask = _name_##_mask_irq, \ .mask_ack = _name_##_mask_irq, \ .unmask = _name_##_unmask_irq, \ } -- cgit v1.2.1 From 16144bfb83bb8319c07c18b57eac15368708d02c Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Mon, 25 Jan 2010 06:03:54 -0500 Subject: [ARM] mmp2: add gpio initialization Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-mmp/irq-mmp2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-mmp/irq-mmp2.c') diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c index ddebde84231a..3ae1c543707c 100644 --- a/arch/arm/mach-mmp/irq-mmp2.c +++ b/arch/arm/mach-mmp/irq-mmp2.c @@ -104,7 +104,7 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num) } } -void __init mmp2_init_irq(void) +void __init mmp2_init_icu(void) { int irq; -- cgit v1.2.1 From df0c382436df5bdd74030baafa294b75c231ec8c Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 3 Feb 2010 10:01:18 -0500 Subject: [ARM] mmp2: add handling on PMIC IRQ Since PMIC INT pin is a special pin of CPU, the status of PMIC INT pin needs to be cleared after PMIC IRQ occured. Now append the clear operation in irq chip handler. Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-mmp/irq-mmp2.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-mmp/irq-mmp2.c') diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c index 3ae1c543707c..b187c027822d 100644 --- a/arch/arm/mach-mmp/irq-mmp2.c +++ b/arch/arm/mach-mmp/irq-mmp2.c @@ -42,6 +42,12 @@ static struct irq_chip icu_irq_chip = { .unmask = icu_unmask_irq, }; +static void pmic_irq_ack(unsigned int irq) +{ + if (irq == IRQ_MMP2_PMIC) + mmp2_clear_pmic_int(); +} + #define SECOND_IRQ_MASK(_name_, irq_base, prefix) \ static void _name_##_mask_irq(unsigned int irq) \ { \ @@ -82,7 +88,6 @@ SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ static struct irq_chip _name_##_irq_chip = { \ .name = #_name_, \ .mask = _name_##_mask_irq, \ - .mask_ack = _name_##_mask_irq, \ .unmask = _name_##_unmask_irq, \ } @@ -126,6 +131,11 @@ void __init mmp2_init_icu(void) } } + /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register + * to be written to clear the interrupt + */ + pmic_irq_chip.ack = pmic_irq_ack; + init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2); init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2); init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5); -- cgit v1.2.1 From 2029e5643a3c4fdd4ad20169fb950cc16e023d0c Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Tue, 2 Feb 2010 23:39:35 -0800 Subject: [ARM] mmp2: fix incorrect calling of chip->mask_ack() for 2nd level cascaded IRQs The irq_chip is not yet registered, so no default irq_chip.mask_ack(), which we have to handle it correctly manually here. Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-mmp/irq-mmp2.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-mmp/irq-mmp2.c') diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c index b187c027822d..cb18221c0af3 100644 --- a/arch/arm/mach-mmp/irq-mmp2.c +++ b/arch/arm/mach-mmp/irq-mmp2.c @@ -102,7 +102,11 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num) int irq; for (irq = start; num > 0; irq++, num--) { - chip->mask_ack(irq); + /* mask and clear the IRQ */ + chip->mask(irq); + if (chip->ack) + chip->ack(irq); + set_irq_chip(irq, chip); set_irq_flags(irq, IRQF_VALID); set_irq_handler(irq, handle_level_irq); -- cgit v1.2.1