From 7000fe8c7a072214d90ca1fc8189b25c30fdd918 Mon Sep 17 00:00:00 2001 From: Abhilash Kesavan Date: Tue, 20 Nov 2012 18:20:38 +0900 Subject: ARM: EXYNOS: Setup legacy i2c controller interrupts On Exynos5 we have a new high-speed i2c controller. The interrupt sources for the legacy and new controller are muxed and are controlled via the SYSCON I2C_CFG register. At reset the interrupt source is configured for the high-speed controller, to continue using the old i2c controller we need to modify the I2C_CFG register. Signed-off-by: Abhilash Kesavan Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/include/mach/regs-pmu.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-exynos/include/mach') diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index d4e392b811a3..684625ad3f39 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h @@ -15,6 +15,7 @@ #include #define S5P_PMUREG(x) (S5P_VA_PMU + (x)) +#define S5P_SYSREG(x) (S3C_VA_SYS + (x)) #define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200) @@ -230,6 +231,7 @@ /* For EXYNOS5 */ +#define EXYNOS5_SYS_I2C_CFG S5P_SYSREG(0x0234) #define EXYNOS5_USB_CFG S5P_PMUREG(0x0230) #define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408) -- cgit v1.2.1