From 1b021a3b23a40be89c4f3fbe6f4696aa15141f26 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 28 Apr 2011 20:19:32 +0800 Subject: at91: fix map_io init usage switch early init to init_early and introduce soc map_io with this Patch we will not do any more early device setup during the map io tks to Russell to point the new call back Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Cc: Nicolas Ferre Cc: Patrice Vilchez Acked-by: Russell King Acked-by: Andrew Victor --- arch/arm/mach-at91/at91sam9g45.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-at91/at91sam9g45.c') diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index c67b47f1c0fd..024e456b943f 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -306,11 +306,14 @@ static void at91sam9g45_poweroff(void) * AT91SAM9G45 processor initialization * -------------------------------------------------------------------- */ -void __init at91sam9g45_initialize(unsigned long main_clock) +void __init at91sam9g45_map_io(void) { /* Map peripherals */ iotable_init(at91sam9g45_io_desc, ARRAY_SIZE(at91sam9g45_io_desc)); +} +void __init at91sam9g45_initialize(unsigned long main_clock) +{ at91_arch_reset = at91sam9g45_reset; pm_power_off = at91sam9g45_poweroff; at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0); -- cgit v1.2.1 From bd60299594fb1d28ae66563c9e76a0b89b0412cf Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Wed, 2 Feb 2011 07:27:07 +0100 Subject: at91: switch to CLKDEV_LOOKUP we do not change the clock naming convention so does not need to switch the AVR32 yet Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Acked-by: Nicolas Ferre Cc: Patrice Vilchez --- arch/arm/mach-at91/at91sam9g45.c | 59 ++++++++++++++++++++++++++++------------ 1 file changed, 41 insertions(+), 18 deletions(-) (limited to 'arch/arm/mach-at91/at91sam9g45.c') diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 024e456b943f..2bb6ff9af1c7 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -184,22 +184,6 @@ static struct clk vdec_clk = { .type = CLK_TYPE_PERIPHERAL, }; -/* One additional fake clock for ohci */ -static struct clk ohci_clk = { - .name = "ohci_clk", - .pmc_mask = 0, - .type = CLK_TYPE_PERIPHERAL, - .parent = &uhphs_clk, -}; - -/* One additional fake clock for second TC block */ -static struct clk tcb1_clk = { - .name = "tcb1_clk", - .pmc_mask = 0, - .type = CLK_TYPE_PERIPHERAL, - .parent = &tcb0_clk, -}; - static struct clk *periph_clocks[] __initdata = { &pioA_clk, &pioB_clk, @@ -228,8 +212,30 @@ static struct clk *periph_clocks[] __initdata = { &udphs_clk, &mmc1_clk, // irq0 - &ohci_clk, - &tcb1_clk, +}; + +static struct clk_lookup periph_clocks_lookups[] = { + /* One additional fake clock for ohci */ + CLKDEV_CON_ID("ohci_clk", &uhphs_clk), + CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci.0", &uhphs_clk), + CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc.0", &utmi_clk), + CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc.0", &udphs_clk), + CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk), + CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk), + CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), + CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), + CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk), + CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk), + CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), + CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), +}; + +static struct clk_lookup usart_clocks_lookups[] = { + CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), + CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), + CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), + CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), + CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk), }; /* @@ -256,6 +262,11 @@ static void __init at91sam9g45_register_clocks(void) for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) clk_register(periph_clocks[i]); + clkdev_add_table(periph_clocks_lookups, + ARRAY_SIZE(periph_clocks_lookups)); + clkdev_add_table(usart_clocks_lookups, + ARRAY_SIZE(usart_clocks_lookups)); + if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) clk_register(&vdec_clk); @@ -263,6 +274,18 @@ static void __init at91sam9g45_register_clocks(void) clk_register(&pck1); } +static struct clk_lookup console_clock_lookup; + +void __init at91sam9g45_set_console_clock(int id) +{ + if (id >= ARRAY_SIZE(usart_clocks_lookups)) + return; + + console_clock_lookup.con_id = "usart"; + console_clock_lookup.clk = usart_clocks_lookups[id].clk; + clkdev_add(&console_clock_lookup); +} + /* -------------------------------------------------------------------- * GPIO * -------------------------------------------------------------------- */ -- cgit v1.2.1