From 7ec13d42f6d7e37fabe09dfd0d257a87f6bf2ee9 Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Tue, 23 Apr 2013 10:33:44 +1200 Subject: dts: vt8500: Fix invalid/missing cpu nodes for soc files. vt8500, wm8650 and wm8850 have no cpu node specified. wm8505 has a cpu node which contains an invalid compatible string, and is missing the other required properties. Signed-off-by: Tony Prisk --- arch/arm/boot/dts/wm8505.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts/wm8505.dtsi') diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index b2bf359e852f..35d9ead79513 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -12,8 +12,12 @@ compatible = "wm,wm8505"; cpus { - cpu@0 { - compatible = "arm,arm926ejs"; + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; }; }; -- cgit v1.2.1 From 55954f8522cf108e8c894130b2656516b9ae6991 Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Tue, 23 Apr 2013 14:23:26 +1200 Subject: dts: vt8500: Update serial nodes and disable by default in SoC files Missing aliases for uarts on vt8500, wm8505, wm8650 added. Nodes incorrectly labelled uart@.., changed to serial@... on all SoCs. Set each uarts default status = "disabled" as they generally don't exist. For each board file, we only need to enable uart0 as no other uarts are physically present on any of these boards. Signed-off-by: Tony Prisk --- arch/arm/boot/dts/wm8505.dtsi | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) (limited to 'arch/arm/boot/dts/wm8505.dtsi') diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index 35d9ead79513..060b5fca2c16 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -21,6 +21,15 @@ }; }; + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -167,46 +176,52 @@ reg = <0xd8050400 0x100>; }; - uart@d8200000 { + uart0: serial@d8200000 { compatible = "via,vt8500-uart"; reg = <0xd8200000 0x1040>; interrupts = <32>; clocks = <&clkuart0>; + status = "disabled"; }; - uart@d82b0000 { + uart1: serial@d82b0000 { compatible = "via,vt8500-uart"; reg = <0xd82b0000 0x1040>; interrupts = <33>; clocks = <&clkuart1>; + status = "disabled"; }; - uart@d8210000 { + uart2: serial@d8210000 { compatible = "via,vt8500-uart"; reg = <0xd8210000 0x1040>; interrupts = <47>; clocks = <&clkuart2>; + status = "disabled"; }; - uart@d82c0000 { + uart3: serial@d82c0000 { compatible = "via,vt8500-uart"; reg = <0xd82c0000 0x1040>; interrupts = <50>; clocks = <&clkuart3>; + status = "disabled"; }; - uart@d8370000 { + uart4: serial@d8370000 { compatible = "via,vt8500-uart"; reg = <0xd8370000 0x1040>; interrupts = <31>; clocks = <&clkuart4>; + status = "disabled"; }; - uart@d8380000 { + uart5: serial@d8380000 { compatible = "via,vt8500-uart"; reg = <0xd8380000 0x1040>; interrupts = <30>; clocks = <&clkuart5>; + status = "disabled"; }; rtc@d8100000 { -- cgit v1.2.1 From 5c2b0a8531f594db82abc29e786b4c2d38fa298b Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Fri, 10 May 2013 17:35:11 +1200 Subject: dts: vt8500: Populate missing PLL nodes Add the missing devicetree nodes for PLL's found on the WM8505, WM8650 and WM8850 SoCs. Signed-off-by: Tony Prisk --- arch/arm/boot/dts/wm8505.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot/dts/wm8505.dtsi') diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index 060b5fca2c16..702d866b6f57 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -81,6 +81,13 @@ clock-frequency = <25000000>; }; + plla: plla { + #clock-cells = <0>; + compatible = "via,vt8500-pll-clock"; + clocks = <&ref25>; + reg = <0x200>; + }; + pllb: pllb { #clock-cells = <0>; compatible = "via,vt8500-pll-clock"; @@ -88,6 +95,20 @@ reg = <0x204>; }; + pllc: pllc { + #clock-cells = <0>; + compatible = "via,vt8500-pll-clock"; + clocks = <&ref25>; + reg = <0x208>; + }; + + plld: plld { + #clock-cells = <0>; + compatible = "via,vt8500-pll-clock"; + clocks = <&ref25>; + reg = <0x20c>; + }; + clkuart0: uart0 { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; -- cgit v1.2.1 From 9e7b6d3eda8551912b0cf9507ca5f489a476d522 Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Fri, 10 May 2013 17:44:58 +1200 Subject: dts: vt8500: Add ARM, AHB, APB and DDR clock nodes to SoC files Add support for the ARM, AHB, APB and DDR clocks found on the WM8505, WM8650, WM8750 and WM8850 SoCs. These clocks are gateable, but the enable part of the clock definition is left out as there are no users for these clocks, and we don't want them being disabled at boot, but it does provide users the ability to check the current rate of these clocks. Signed-off-by: Tony Prisk --- arch/arm/boot/dts/wm8505.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm/boot/dts/wm8505.dtsi') diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index 702d866b6f57..a1a854b8a454 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -109,6 +109,34 @@ reg = <0x20c>; }; + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x350>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + clkuart0: uart0 { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; -- cgit v1.2.1