From b45ccc4e4923ad4c9d1b541f52b2b33facd3b0c5 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Sun, 10 Feb 2013 21:40:19 +0530 Subject: ARM: dts: OMAP5: Align the local timer dt node as per the current binding code It has been decided to not duplicate banked modules dt nodes and that is how the current arch timer dt extraction code is. Update the OMAP5 DT file accordingly. Signed-off-by: Santosh Shilimkar Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) (limited to 'arch/arm/boot/dts/omap5.dtsi') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index b760c116e7f7..aefecf7ca574 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -33,24 +33,19 @@ cpus { cpu@0 { compatible = "arm,cortex-a15"; - timer { - compatible = "arm,armv7-timer"; - /* 14th PPI IRQ, active low level-sensitive */ - interrupts = <1 14 0x308>; - clock-frequency = <6144000>; - }; }; cpu@1 { compatible = "arm,cortex-a15"; - timer { - compatible = "arm,armv7-timer"; - /* 14th PPI IRQ, active low level-sensitive */ - interrupts = <1 14 0x308>; - clock-frequency = <6144000>; - }; }; }; + timer { + compatible = "arm,armv7-timer"; + /* 14th PPI IRQ, active low level-sensitive */ + interrupts = <1 14 0x308>; + clock-frequency = <6144000>; + }; + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. -- cgit v1.2.1