From 8f7726d251f381bfad185d3e7a2d60e0bff48acc Mon Sep 17 00:00:00 2001 From: Greentime Hu Date: Thu, 28 Dec 2017 17:49:33 +0800 Subject: dt-bindings: nds32 L2 cache controller Bindings This patch adds nds32 L2 cache controller binding documents. Signed-off-by: Greentime Hu Reviewed-by: Rob Herring Acked-by: Arnd Bergmann --- Documentation/devicetree/bindings/nds32/atl2c.txt | 28 +++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/nds32/atl2c.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/nds32/atl2c.txt b/Documentation/devicetree/bindings/nds32/atl2c.txt new file mode 100644 index 000000000000..da8ab8e7ae9b --- /dev/null +++ b/Documentation/devicetree/bindings/nds32/atl2c.txt @@ -0,0 +1,28 @@ +* Andestech L2 cache Controller + +The level-2 cache controller plays an important role in reducing memory latency +for high performance systems, such as thoese designs with AndesCore processors. +Level-2 cache controller in general enhances overall system performance +signigicantly and the system power consumption might be reduced as well by +reducing DRAM accesses. + +This binding specifies what properties must be available in the device tree +representation of an Andestech L2 cache controller. + +Required properties: + - compatible: + Usage: required + Value type: + Definition: "andestech,atl2c" + - reg : Physical base address and size of cache controller's memory mapped + - cache-unified : Specifies the cache is a unified cache. + - cache-level : Should be set to 2 for a level 2 cache. + +* Example + + cache-controller@e0500000 { + compatible = "andestech,atl2c"; + reg = <0xe0500000 0x1000>; + cache-unified; + cache-level = <2>; + }; -- cgit v1.2.1