From 34e12121f9f46dbeda1017cac4615c96ffe16c6d Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 00:44:48 +0900 Subject: ARM: shmobile: Remove unused headers from hotplug.c This file has no SoC-specific references in it, and fortunately it is still independent of OF so there is no real reason to drag in these headers. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/hotplug.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c index a1524e3367b0..efd0b36a4175 100644 --- a/arch/arm/mach-shmobile/hotplug.c +++ b/arch/arm/mach-shmobile/hotplug.c @@ -14,12 +14,8 @@ #include #include #include -#include #include -#include -#include #include -#include static cpumask_t dead_cpus; -- cgit v1.2.1 From d62242d7f63d6c874f783d8a691534080df1cb59 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 00:44:57 +0900 Subject: ARM: shmobile: Remove partial CPU Hotplug from EMEV2 Remove partial CPU hotplug support from EMEV2 SMP code. The upstream EMEV2 SMP support code has no CPU shutdown or reset ability so we cannot reboot the secondary CPU cores. Regular SMP operation is however still working as expected. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-emev2.c | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 953eb1f9388d..72620b1f87c8 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -62,29 +62,6 @@ static unsigned int __init emev2_get_core_count(void) return scu_base ? scu_get_core_count(scu_base) : 1; } -static int emev2_platform_cpu_kill(unsigned int cpu) -{ - return 0; /* not supported yet */ -} - -static int __maybe_unused emev2_cpu_kill(unsigned int cpu) -{ - int k; - - /* this function is running on another CPU than the offline target, - * here we need wait for shutdown code in platform_cpu_die() to - * finish before asking SoC-specific code to power off the CPU core. - */ - for (k = 0; k < 1000; k++) { - if (shmobile_cpu_is_dead(cpu)) - return emev2_platform_cpu_kill(cpu); - mdelay(1); - } - - return 0; -} - - static void __cpuinit emev2_secondary_init(unsigned int cpu) { gic_secondary_init(0); @@ -126,9 +103,4 @@ struct smp_operations emev2_smp_ops __initdata = { .smp_prepare_cpus = emev2_smp_prepare_cpus, .smp_secondary_init = emev2_secondary_init, .smp_boot_secondary = emev2_boot_secondary, -#ifdef CONFIG_HOTPLUG_CPU - .cpu_kill = emev2_cpu_kill, - .cpu_die = shmobile_cpu_die, - .cpu_disable = shmobile_cpu_disable, -#endif }; -- cgit v1.2.1 From da252b8ee542e95d35374b1d31006f8fe5d59f6a Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 00:45:06 +0900 Subject: ARM: shmobile: Move EMEV2 CPU boot vector setup code Move the boot vector setup code for the EMEV2 SoC to match the sh73a0 and r8a7779 implementations. With this in place all SoC specific SMP implementations for mach-shmobile uses the ->smp_prepare_cpus() callback to setup the boot vector. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-emev2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 72620b1f87c8..64278215adaa 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -74,9 +74,6 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct * /* enable cache coherency */ modify_scu_cpu_psr(0, 3 << (cpu * 8)); - /* Tell ROM loader about our vector (in headsmp.S) */ - emev2_set_boot_vector(__pa(shmobile_secondary_vector)); - arch_send_wakeup_ipi_mask(cpumask_of(cpu)); return 0; } @@ -87,6 +84,9 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) scu_enable(scu_base); + /* Tell ROM loader about our vector (in headsmp.S) */ + emev2_set_boot_vector(__pa(shmobile_secondary_vector)); + /* enable cache coherency on CPU0 */ modify_scu_cpu_psr(0, 3 << (cpu * 8)); } -- cgit v1.2.1 From f313ae4e98f2c0825a5a808e4b822214836b5085 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 00:45:16 +0900 Subject: ARM: shmobile: Remove sh73a0_get_core_count() Reduce the number of lines of code in smp-sh73a0.c by getting rid of the sh73a0_get_core_count() function. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-sh73a0.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index acb46a94ccdf..81c0f4ba1846 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -52,13 +52,6 @@ void __init sh73a0_register_twd(void) } #endif -static unsigned int __init sh73a0_get_core_count(void) -{ - void __iomem *scu_base = scu_base_addr(); - - return scu_get_core_count(scu_base); -} - static void __cpuinit sh73a0_secondary_init(unsigned int cpu) { gic_secondary_init(0); @@ -90,7 +83,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) static void __init sh73a0_smp_init_cpus(void) { - unsigned int ncores = sh73a0_get_core_count(); + unsigned int ncores = scu_get_core_count(scu_base_addr()); shmobile_smp_init_cpus(ncores); } -- cgit v1.2.1 From 0ae56a951de0efbf36a51de5b2e91db10425c771 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 00:45:25 +0900 Subject: ARM: shmobile: Remove r8a7779_get_core_count() Reduce the number of lines of code in smp-r8a7779.c by getting rid of the r8a7779_get_core_count() function. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-r8a7779.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 3a4acf23edcf..f46b51658c3a 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -87,13 +87,6 @@ static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) __raw_writel(tmp, scu_base + 8); } -static unsigned int __init r8a7779_get_core_count(void) -{ - void __iomem *scu_base = scu_base_addr(); - - return scu_get_core_count(scu_base); -} - static int r8a7779_platform_cpu_kill(unsigned int cpu) { struct r8a7779_pm_ch *ch = NULL; @@ -178,7 +171,7 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) static void __init r8a7779_smp_init_cpus(void) { - unsigned int ncores = r8a7779_get_core_count(); + unsigned int ncores = scu_get_core_count(scu_base_addr()); shmobile_smp_init_cpus(ncores); } -- cgit v1.2.1 From 2f747dbab424396b797d8abfb5d54c5e19003885 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 00:45:34 +0900 Subject: ARM: shmobile: Remove emev2_get_core_count() Reduce the number of lines of code in smp-emev2.c by getting rid of the emev2_get_core_count() function. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-emev2.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 64278215adaa..4ede41339a70 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -50,18 +50,6 @@ static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) } -static unsigned int __init emev2_get_core_count(void) -{ - if (!scu_base) { - scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); - emev2_clock_init(); /* need ioremapped SMU */ - } - - WARN_ON_ONCE(!scu_base); - - return scu_base ? scu_get_core_count(scu_base) : 1; -} - static void __cpuinit emev2_secondary_init(unsigned int cpu) { gic_secondary_init(0); @@ -93,7 +81,14 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) static void __init emev2_smp_init_cpus(void) { - unsigned int ncores = emev2_get_core_count(); + unsigned int ncores; + + if (!scu_base) { + scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); + emev2_clock_init(); /* need ioremapped SMU */ + } + + ncores = scu_base ? scu_get_core_count(scu_base) : 1; shmobile_smp_init_cpus(ncores); } -- cgit v1.2.1 From df2ddd7b9b781f0aee7fc90e6bed21e62ebf7564 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 8 Feb 2013 19:38:25 +0100 Subject: ARM: shmobile: add MMCIF and SDHI DT clock aliases to sh73a0 and r8a7740 Add clock lookup entries for SDHI and MMCIF device names, for the FDT case. Signed-off-by: Guennadi Liakhovetski Acked-by: Laurent Pinchart Acked-by: Linus Walleij [horms+renesas@verge.net.au: resolved trivial conflict in clock-r8a7740.c] Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7740.c | 4 ++++ arch/arm/mach-shmobile/clock-sh73a0.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index 19ce885a3b43..1a9b9a29442a 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -611,11 +611,15 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]), CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), + CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), /* ICK */ CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]), diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index afa5423a0f93..5fa106b61149 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -581,10 +581,13 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ + CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ + CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */ + CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */ CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */ CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */ CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */ -- cgit v1.2.1 From c58a1545e39ed1ff54dd2c167d3d25ae62c0dbd3 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 29 Jan 2013 14:21:46 +0900 Subject: ARM: mach-shmobile: r8a7779: Allow initialisation of GIC by DT This allows the GIC interrupt controller of the r8a7779 SoC to be initialised using a flattened device tree blob. Signed-off-by: Simon Horman --- v3 * Fix copy-paste error and use unique reg values for each CPU v2 As suggested by Mark Rutland * Add reg and device_type to cpus * Remove #address-cells from gic --- arch/arm/boot/dts/r8a7779.dtsi | 50 ++++++++++++++++++++++++++++ arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/intc-r8a7779.c | 27 +++++++++++---- 3 files changed, 72 insertions(+), 6 deletions(-) create mode 100644 arch/arm/boot/dts/r8a7779.dtsi diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi new file mode 100644 index 000000000000..8c6d52cee6c6 --- /dev/null +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -0,0 +1,50 @@ +/* + * Device Tree Source for Renesas r8a7740 + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Simon Horman + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "renesas,r8a7779"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + }; + }; + + gic: interrupt-controller@f0001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xf0001000 0x1000>, + <0xf0000100 0x100>; + }; +}; diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index e48606d8a2be..3f067100bb05 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -59,6 +59,7 @@ extern void r8a7740_pinmux_init(void); extern void r8a7740_pm_init(void); extern void r8a7779_init_irq(void); +extern void r8a7779_init_irq_dt(void); extern void r8a7779_map_io(void); extern void r8a7779_earlytimer_init(void); extern void r8a7779_add_early_devices(void); diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c index 8807c27f71f9..f9cc4bc9c798 100644 --- a/arch/arm/mach-shmobile/intc-r8a7779.c +++ b/arch/arm/mach-shmobile/intc-r8a7779.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -43,13 +44,8 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on) return 0; /* always allow wakeup */ } -void __init r8a7779_init_irq(void) +static void __init r8a7779_init_irq_common(void) { - void __iomem *gic_dist_base = IOMEM(0xf0001000); - void __iomem *gic_cpu_base = IOMEM(0xf0000100); - - /* use GIC to handle interrupts */ - gic_init(0, 29, gic_dist_base, gic_cpu_base); gic_arch_extn.irq_set_wake = r8a7779_set_wake; /* route all interrupts to ARM */ @@ -63,3 +59,22 @@ void __init r8a7779_init_irq(void) __raw_writel(0xbffffffc, INT2SMSKCR3); __raw_writel(0x003fee3f, INT2SMSKCR4); } + +void __init r8a7779_init_irq(void) +{ + void __iomem *gic_dist_base = IOMEM(0xf0001000); + void __iomem *gic_cpu_base = IOMEM(0xf0000100); + + /* use GIC to handle interrupts */ + gic_init(0, 29, gic_dist_base, gic_cpu_base); + + r8a7779_init_irq_common(); +} + +#ifdef CONFIG_OF +void __init r8a7779_init_irq_dt(void) +{ + irqchip_init(); + r8a7779_init_irq_common(); +} +#endif -- cgit v1.2.1 From 10e8d4f6dddb0f9dc408c2f2bde8399b243a42ca Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 21 Nov 2012 22:00:15 +0900 Subject: ARM: mach-shmobile: r8a7779: Minimal setup using DT Allow a minimal setup of the r8a7779 SoC using a flattened device tree. In particular, configure the i2c and ethernet controllers using a flattened device tree. SCI serial controller and TMU clock source, whose drivers do not yet support configuration using a flattened device tree, are still configured using C code in order to allow booting of a board with this SoC. The ethernet controller also requires a regulator which is a board property. A sample snippet DT for the marzen board is as follows: /dts-v1/; /include/ "r8a7779.dtsi" / { fixedregulator3v3: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; }; &lan0 { vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; }; Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 45 +++++++++++++++++++++ arch/arm/mach-shmobile/include/mach/common.h | 2 + arch/arm/mach-shmobile/setup-r8a7779.c | 59 +++++++++++++++++++++++++--- 3 files changed, 100 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 8c6d52cee6c6..2913759e93e2 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -47,4 +47,49 @@ reg = <0xf0001000 0x1000>, <0xf0000100 0x100>; }; + + i2c0: i2c@0xffc70000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; + reg = <0xffc70000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 79 0x4>; + }; + + i2c1: i2c@0xffc71000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; + reg = <0xffc71000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 82 0x4>; + }; + + i2c2: i2c@0xffc72000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; + reg = <0xffc72000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 80 0x4>; + }; + + i2c3: i2c@0xffc73000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; + reg = <0xffc73000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 81 0x4>; + }; + + lan0: lan0@18000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x18000000 0x100>; + phy-mode = "mii"; + interrupt-parent = <&gic>; + interrupts = <0 28 0x4>; + reg-io-width = <4>; + }; }; diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 3f067100bb05..c72d301a8d98 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -63,7 +63,9 @@ extern void r8a7779_init_irq_dt(void); extern void r8a7779_map_io(void); extern void r8a7779_earlytimer_init(void); extern void r8a7779_add_early_devices(void); +extern void r8a7779_add_early_devices_dt(void); extern void r8a7779_add_standard_devices(void); +extern void r8a7779_add_standard_devices_dt(void); extern void r8a7779_clock_init(void); extern void r8a7779_pinmux_init(void); extern void r8a7779_pm_init(void); diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index c54ff9b29fe5..922dd4db21a0 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -321,7 +322,7 @@ static struct platform_device i2c3_device = { .num_resources = ARRAY_SIZE(rcar_i2c3_res), }; -static struct platform_device *r8a7779_early_devices[] __initdata = { +static struct platform_device *r8a7779_early_devices_dt[] __initdata = { &scif0_device, &scif1_device, &scif2_device, @@ -330,15 +331,15 @@ static struct platform_device *r8a7779_early_devices[] __initdata = { &scif5_device, &tmu00_device, &tmu01_device, +}; + +static struct platform_device *r8a7779_early_devices[] __initdata = { &i2c0_device, &i2c1_device, &i2c2_device, &i2c3_device, }; -static struct platform_device *r8a7779_late_devices[] __initdata = { -}; - void __init r8a7779_add_standard_devices(void) { #ifdef CONFIG_CACHE_L2X0 @@ -349,10 +350,10 @@ void __init r8a7779_add_standard_devices(void) r8a7779_init_pm_domains(); + platform_add_devices(r8a7779_early_devices_dt, + ARRAY_SIZE(r8a7779_early_devices_dt)); platform_add_devices(r8a7779_early_devices, ARRAY_SIZE(r8a7779_early_devices)); - platform_add_devices(r8a7779_late_devices, - ARRAY_SIZE(r8a7779_late_devices)); } /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ @@ -367,6 +368,8 @@ void __init r8a7779_earlytimer_init(void) void __init r8a7779_add_early_devices(void) { + early_platform_add_devices(r8a7779_early_devices_dt, + ARRAY_SIZE(r8a7779_early_devices_dt)); early_platform_add_devices(r8a7779_early_devices, ARRAY_SIZE(r8a7779_early_devices)); @@ -386,3 +389,47 @@ void __init r8a7779_add_early_devices(void) * command line in case of the marzen board. */ } + +#ifdef CONFIG_USE_OF +void __init r8a7779_add_early_devices_dt(void) +{ + shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ + + early_platform_add_devices(r8a7779_early_devices_dt, + ARRAY_SIZE(r8a7779_early_devices_dt)); + + /* Early serial console setup is not included here. + * See comment in r8a7779_add_early_devices(). + */ +} + +static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = { + {}, +}; + +void __init r8a7779_add_standard_devices_dt(void) +{ + /* clocks are setup late during boot in the case of DT */ + r8a7779_clock_init(); + + platform_add_devices(r8a7779_early_devices_dt, + ARRAY_SIZE(r8a7779_early_devices_dt)); + of_platform_populate(NULL, of_default_bus_match_table, + r8a7779_auxdata_lookup, NULL); +} + +static const char *r8a7779_compat_dt[] __initdata = { + "renesas,r8a7779", + NULL, +}; + +DT_MACHINE_START(SH73A0_DT, "Generic R8A7779 (Flattened Device Tree)") + .map_io = r8a7779_map_io, + .init_early = r8a7779_add_early_devices_dt, + .nr_irqs = NR_IRQS_LEGACY, + .init_irq = r8a7779_init_irq_dt, + .init_machine = r8a7779_add_standard_devices_dt, + .init_time = shmobile_timer_init, + .dt_compat = r8a7779_compat_dt, +MACHINE_END +#endif /* CONFIG_USE_OF */ -- cgit v1.2.1 From aa8d3bb177a3ba64407d98c75d5c6c5130ff2182 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 22:46:38 +0900 Subject: ARM: shmobile: Kill off sh73a0 scu_base_addr() function Replace scu_base_addr() with a static shmobile_scu_base variable and introduce SH73A0_SCU_BASE. Later in the series the shmobile_scu_base variable will be made into a global variable so this is preparation only. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-sh73a0.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 81c0f4ba1846..0757f4a94bf5 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -39,13 +39,12 @@ #define PSTR_SHUTDOWN_MODE 3 -static void __iomem *scu_base_addr(void) -{ - return (void __iomem *)0xf0000000; -} +#define SH73A0_SCU_BASE IOMEM(0xf0000000) + +static void __iomem *shmobile_scu_base; #ifdef CONFIG_HAVE_ARM_TWD -static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); +static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29); void __init sh73a0_register_twd(void) { twd_local_timer_register(&twd_local_timer); @@ -71,21 +70,22 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) { - scu_enable(scu_base_addr()); + scu_enable(shmobile_scu_base); /* Map the reset vector (in headsmp-sh73a0.S) */ __raw_writel(0, APARMBAREA); /* 4k */ __raw_writel(__pa(sh73a0_secondary_vector), SBAR); /* enable cache coherency on booting CPU */ - scu_power_mode(scu_base_addr(), SCU_PM_NORMAL); + scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); } static void __init sh73a0_smp_init_cpus(void) { - unsigned int ncores = scu_get_core_count(scu_base_addr()); + /* setup sh73a0 specific SCU base */ + shmobile_scu_base = SH73A0_SCU_BASE; - shmobile_smp_init_cpus(ncores); + shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); } #ifdef CONFIG_HOTPLUG_CPU @@ -121,7 +121,7 @@ static void sh73a0_cpu_die(unsigned int cpu) flush_cache_all(); /* Set power off mode. This takes the CPU out of the MP cluster */ - scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF); + scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); /* Enter shutdown mode */ cpu_do_idle(); -- cgit v1.2.1 From 3b94afa38350ad5b592df5b6539a20a253e04b53 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 22:46:48 +0900 Subject: ARM: shmobile: Kill off r8a7779 scu_base_addr() function Replace scu_base_addr() with a static shmobile_scu_base variable and introduce R8A7779_SCU_BASE. Later in the series the shmobile_scu_base variable will be made into a global variable so this is preparation only. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-r8a7779.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index f46b51658c3a..d92188d702ab 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -31,6 +31,9 @@ #include #define AVECR IOMEM(0xfe700040) +#define R8A7779_SCU_BASE IOMEM(0xf0000000) + +static void __iomem *shmobile_scu_base; static struct r8a7779_pm_ch r8a7779_ch_cpu1 = { .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ @@ -56,11 +59,6 @@ static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = { [3] = &r8a7779_ch_cpu3, }; -static void __iomem *scu_base_addr(void) -{ - return (void __iomem *)0xf0000000; -} - static DEFINE_SPINLOCK(scu_lock); static unsigned long tmp; @@ -75,7 +73,7 @@ void __init r8a7779_register_twd(void) static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) { - void __iomem *scu_base = scu_base_addr(); + void __iomem *scu_base = shmobile_scu_base; spin_lock(&scu_lock); tmp = __raw_readl(scu_base + 8); @@ -153,7 +151,7 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) { int cpu = cpu_logical_map(0); - scu_enable(scu_base_addr()); + scu_enable(shmobile_scu_base); /* Map the reset vector (in headsmp.S) */ __raw_writel(__pa(shmobile_secondary_vector), AVECR); @@ -171,9 +169,10 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) static void __init r8a7779_smp_init_cpus(void) { - unsigned int ncores = scu_get_core_count(scu_base_addr()); + /* setup r8a7779 specific SCU base */ + shmobile_scu_base = R8A7779_SCU_BASE; - shmobile_smp_init_cpus(ncores); + shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); } struct smp_operations r8a7779_smp_ops __initdata = { -- cgit v1.2.1 From d8a28ed1bc06128f8761b332c74759db1dc7d82c Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 22:46:57 +0900 Subject: ARM: shmobile: Rework EMEV2 scu_base variable Rename the static scu_base variable into shmobile_scu_base. Later in the series the shmobile_scu_base variable will be made into a global variable so this is preparation only. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-emev2.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 4ede41339a70..136867ea1e93 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -32,8 +32,9 @@ #define EMEV2_SCU_BASE 0x1e000000 +static void __iomem *shmobile_scu_base; + static DEFINE_SPINLOCK(scu_lock); -static void __iomem *scu_base; static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) { @@ -42,10 +43,10 @@ static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) /* we assume this code is running on a different cpu * than the one that is changing coherency setting */ spin_lock(&scu_lock); - tmp = readl(scu_base + 8); + tmp = readl(shmobile_scu_base + 8); tmp &= ~clr; tmp |= set; - writel(tmp, scu_base + 8); + writel(tmp, shmobile_scu_base + 8); spin_unlock(&scu_lock); } @@ -70,7 +71,7 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) { int cpu = cpu_logical_map(0); - scu_enable(scu_base); + scu_enable(shmobile_scu_base); /* Tell ROM loader about our vector (in headsmp.S) */ emev2_set_boot_vector(__pa(shmobile_secondary_vector)); @@ -83,12 +84,12 @@ static void __init emev2_smp_init_cpus(void) { unsigned int ncores; - if (!scu_base) { - scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); + if (!shmobile_scu_base) { + shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); emev2_clock_init(); /* need ioremapped SMU */ } - ncores = scu_base ? scu_get_core_count(scu_base) : 1; + ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1; shmobile_smp_init_cpus(ncores); } -- cgit v1.2.1 From ec0d84a8d5522aaed3f932caff30a0b165c8cf44 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 22:47:07 +0900 Subject: ARM: shmobile: Move headsmp-sh73a0.S to headsmp-scu.S Rename headsmp-sh73a0.S into headsmp-scu.S and introduce shmobile_secondary_vector_scu(). The goal is to be able to share the function above between all mach-shmobile SoCs that use SCU for SMP. So far only sh73a0 use this. At this time the SCU base address is still hard coded in headsmp-scu.S to 0xf0000000, but this will be changed in the future. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Makefile | 2 +- arch/arm/mach-shmobile/headsmp-scu.S | 50 ++++++++++++++++++++++++++++ arch/arm/mach-shmobile/include/mach/common.h | 2 +- arch/arm/mach-shmobile/smp-sh73a0.c | 4 +-- 4 files changed, 54 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mach-shmobile/headsmp-scu.S diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index e1fac57514b9..245a8736754a 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o # SMP objects smp-y := platsmp.o headsmp.o smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o -smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-sh73a0.o +smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S new file mode 100644 index 000000000000..4ee287d9c508 --- /dev/null +++ b/arch/arm/mach-shmobile/headsmp-scu.S @@ -0,0 +1,50 @@ +/* + * Shared SCU setup for mach-shmobile + * + * Copyright (C) 2012 Bastian Hecht + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + + __CPUINIT +/* + * Reset vector for secondary CPUs. + * + * First we turn on L1 cache coherency for our CPU. Then we jump to + * shmobile_invalidate_start that invalidates the cache and hands over control + * to the common ARM startup code. + * This function will be mapped to address 0 by the SBAR register. + * A normal branch is out of range here so we need a long jump. We jump to + * the physical address as the MMU is still turned off. + */ + .align 12 +ENTRY(shmobile_secondary_vector_scu) + mrc p15, 0, r0, c0, c0, 5 @ read MIPDR + and r0, r0, #3 @ mask out cpu ID + lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits + mov r1, #0xf0000000 @ SCU base address + ldr r2, [r1, #8] @ SCU Power Status Register + mov r3, #3 + bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) + str r2, [r1, #8] @ write back + + ldr pc, 1f +1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET +ENDPROC(shmobile_secondary_vector_scu) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index c72d301a8d98..20acf000b46b 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -8,6 +8,7 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz, struct twd_local_timer; extern void shmobile_setup_console(void); extern void shmobile_secondary_vector(void); +extern void shmobile_secondary_vector_scu(void); struct clk; extern int shmobile_clk_init(void); extern void shmobile_handle_irq_intc(struct pt_regs *); @@ -44,7 +45,6 @@ extern void sh73a0_add_standard_devices_dt(void); extern void sh73a0_clock_init(void); extern void sh73a0_pinmux_init(void); extern void sh73a0_pm_init(void); -extern void sh73a0_secondary_vector(void); extern struct clk sh73a0_extal1_clk; extern struct clk sh73a0_extal2_clk; extern struct clk sh73a0_extcki_clk; diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 0757f4a94bf5..de7518f745f0 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -72,9 +72,9 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) { scu_enable(shmobile_scu_base); - /* Map the reset vector (in headsmp-sh73a0.S) */ + /* Map the reset vector (in headsmp-scu.S) */ __raw_writel(0, APARMBAREA); /* 4k */ - __raw_writel(__pa(sh73a0_secondary_vector), SBAR); + __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR); /* enable cache coherency on booting CPU */ scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); -- cgit v1.2.1 From 4c8228455d1008136d748e6973dd72578bab4697 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 22:47:17 +0900 Subject: ARM: shmobile: Common shmobile_scu_base in headsmp-scu.S Update the code in headsmp-scu.S to use a global shmobile_scu_base variable both for convenient SCU base address storage and for the early SCU setup code in shmobile_secondary_vector_scu. With this patch applied r8a7779, sh73a0 and EMEV2 all make use of the global shmobile_scu_base variable. However only sh73a0 makes use of the SCU bring up code in shmobile_secondary_vector_scu. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Makefile | 4 +-- arch/arm/mach-shmobile/headsmp-scu.S | 8 ++++- arch/arm/mach-shmobile/headsmp-sh73a0.S | 50 ---------------------------- arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/smp-emev2.c | 2 -- arch/arm/mach-shmobile/smp-r8a7779.c | 2 -- arch/arm/mach-shmobile/smp-sh73a0.c | 2 -- 7 files changed, 10 insertions(+), 59 deletions(-) delete mode 100644 arch/arm/mach-shmobile/headsmp-sh73a0.S diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 245a8736754a..d7d20579bef7 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -16,8 +16,8 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o smp-y := platsmp.o headsmp.o smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o -smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o -smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o +smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o +smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o # IRQ objects obj-$(CONFIG_ARCH_SH7372) += entry-intc.o diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S index 4ee287d9c508..0b9317062b2a 100644 --- a/arch/arm/mach-shmobile/headsmp-scu.S +++ b/arch/arm/mach-shmobile/headsmp-scu.S @@ -39,7 +39,8 @@ ENTRY(shmobile_secondary_vector_scu) mrc p15, 0, r0, c0, c0, 5 @ read MIPDR and r0, r0, #3 @ mask out cpu ID lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits - mov r1, #0xf0000000 @ SCU base address + ldr r1, =shmobile_scu_base + ldr r1, [r1] @ SCU base address ldr r2, [r1, #8] @ SCU Power Status Register mov r3, #3 bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) @@ -48,3 +49,8 @@ ENTRY(shmobile_secondary_vector_scu) ldr pc, 1f 1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET ENDPROC(shmobile_secondary_vector_scu) + + .text + .globl shmobile_scu_base +shmobile_scu_base: + .space 4 diff --git a/arch/arm/mach-shmobile/headsmp-sh73a0.S b/arch/arm/mach-shmobile/headsmp-sh73a0.S deleted file mode 100644 index bec4c0d9b713..000000000000 --- a/arch/arm/mach-shmobile/headsmp-sh73a0.S +++ /dev/null @@ -1,50 +0,0 @@ -/* - * SMP support for SoC sh73a0 - * - * Copyright (C) 2012 Bastian Hecht - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - - __CPUINIT -/* - * Reset vector for secondary CPUs. - * - * First we turn on L1 cache coherency for our CPU. Then we jump to - * shmobile_invalidate_start that invalidates the cache and hands over control - * to the common ARM startup code. - * This function will be mapped to address 0 by the SBAR register. - * A normal branch is out of range here so we need a long jump. We jump to - * the physical address as the MMU is still turned off. - */ - .align 12 -ENTRY(sh73a0_secondary_vector) - mrc p15, 0, r0, c0, c0, 5 @ read MIPDR - and r0, r0, #3 @ mask out cpu ID - lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits - mov r1, #0xf0000000 @ SCU base address - ldr r2, [r1, #8] @ SCU Power Status Register - mov r3, #3 - bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) - str r2, [r1, #8] @ write back - - ldr pc, 1f -1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET -ENDPROC(sh73a0_secondary_vector) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 20acf000b46b..84dcaa4279b2 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -95,6 +95,7 @@ extern int shmobile_cpu_is_dead(unsigned int cpu); static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; } #endif +extern void __iomem *shmobile_scu_base; extern void shmobile_smp_init_cpus(unsigned int ncores); static inline void __init shmobile_init_late(void) diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 136867ea1e93..bc8e071d55c6 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -32,8 +32,6 @@ #define EMEV2_SCU_BASE 0x1e000000 -static void __iomem *shmobile_scu_base; - static DEFINE_SPINLOCK(scu_lock); static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index d92188d702ab..7fd58a3a26d8 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -33,8 +33,6 @@ #define AVECR IOMEM(0xfe700040) #define R8A7779_SCU_BASE IOMEM(0xf0000000) -static void __iomem *shmobile_scu_base; - static struct r8a7779_pm_ch r8a7779_ch_cpu1 = { .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ .chan_bit = 1, /* ARM1 */ diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index de7518f745f0..2244fd074f72 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -41,8 +41,6 @@ #define SH73A0_SCU_BASE IOMEM(0xf0000000) -static void __iomem *shmobile_scu_base; - #ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29); void __init sh73a0_register_twd(void) -- cgit v1.2.1 From 1af4b3fa1912f20a3dd1e231e90b439c0226b9b1 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 22:47:27 +0900 Subject: ARM: shmobile: Update EMEV2 to use scu_power_mode() Update the SMP code for EMEV2 to make use of the shared SCU function scu_power_mode() together with the early setup code in shmobile_secondary_vector_scu. With this patch in place the secondary CPUs modify the SCU setting during early boot instead of letting other CPUs deal with the coherency setting before boot. In other words, we used to setup coherency before boot in emev2_boot_secondary() but that bit is now instead handled by the code in shmobile_secondary_vector_scu. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-emev2.c | 42 ++++++++------------------------------ 1 file changed, 8 insertions(+), 34 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index bc8e071d55c6..8225c16b371b 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -28,27 +28,9 @@ #include #include #include -#include #define EMEV2_SCU_BASE 0x1e000000 -static DEFINE_SPINLOCK(scu_lock); - -static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) -{ - unsigned long tmp; - - /* we assume this code is running on a different cpu - * than the one that is changing coherency setting */ - spin_lock(&scu_lock); - tmp = readl(shmobile_scu_base + 8); - tmp &= ~clr; - tmp |= set; - writel(tmp, shmobile_scu_base + 8); - spin_unlock(&scu_lock); - -} - static void __cpuinit emev2_secondary_init(unsigned int cpu) { gic_secondary_init(0); @@ -56,36 +38,28 @@ static void __cpuinit emev2_secondary_init(unsigned int cpu) static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) { - cpu = cpu_logical_map(cpu); - - /* enable cache coherency */ - modify_scu_cpu_psr(0, 3 << (cpu * 8)); - - arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu))); return 0; } static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) { - int cpu = cpu_logical_map(0); - scu_enable(shmobile_scu_base); - /* Tell ROM loader about our vector (in headsmp.S) */ - emev2_set_boot_vector(__pa(shmobile_secondary_vector)); + /* Tell ROM loader about our vector (in headsmp-scu.S) */ + emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu)); - /* enable cache coherency on CPU0 */ - modify_scu_cpu_psr(0, 3 << (cpu * 8)); + /* enable cache coherency on booting CPU */ + scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); } static void __init emev2_smp_init_cpus(void) { unsigned int ncores; - if (!shmobile_scu_base) { - shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); - emev2_clock_init(); /* need ioremapped SMU */ - } + /* setup EMEV2 specific SCU base */ + shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); + emev2_clock_init(); /* need ioremapped SMU */ ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1; -- cgit v1.2.1 From 342ab8741cf3da5505e0d253784d19365a2eca8f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Feb 2013 22:49:47 +0900 Subject: ARM: shmobile: Make EMEV2 setup functions static Adjust emev2_init_delay() and emev2_add_standard_devices_dt() to become static. They are not used outside this file anyway. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-emev2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index 47662a581c0a..e4545c152722 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c @@ -404,7 +404,7 @@ void __init emev2_add_standard_devices(void) ARRAY_SIZE(emev2_late_devices)); } -void __init emev2_init_delay(void) +static void __init emev2_init_delay(void) { shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ } @@ -439,7 +439,7 @@ static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = { { } }; -void __init emev2_add_standard_devices_dt(void) +static void __init emev2_add_standard_devices_dt(void) { of_platform_populate(NULL, of_default_bus_match_table, emev2_auxdata_lookup, NULL); -- cgit v1.2.1 From 8a444474efbe808471366fb57f31ec802846a818 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 22 Feb 2013 18:17:51 +0100 Subject: ARM: shmobile: sh73a0: fix Z and ZG clock hierarchy Z and ZG clocks on sh73a0 have pll0 as their parent, not pll1. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh73a0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 5fa106b61149..71843dd39e16 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -265,12 +265,12 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, static struct clk div4_clks[DIV4_NR] = { [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT), - [DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), + [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT), [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), - [DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0), + [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0), [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0), [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0), [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), -- cgit v1.2.1 From 4eca134f71a5d3095b54279b7e643b3c2df9512c Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 15 Feb 2013 21:38:20 +0900 Subject: ARM: shmobile: sh73a0: Remove sh73a0_init_irq_dt() This is not needed as irq_set_wake is only used for suspend to ram which is not a requirement for bringing up boards using DT. Reported-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/intc-sh73a0.c | 8 -------- arch/arm/mach-shmobile/setup-sh73a0.c | 3 ++- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c index 91faba666d46..a81a1d804e2e 100644 --- a/arch/arm/mach-shmobile/intc-sh73a0.c +++ b/arch/arm/mach-shmobile/intc-sh73a0.c @@ -460,11 +460,3 @@ void __init sh73a0_init_irq(void) sh73a0_pint1_cascade.handler = sh73a0_pint1_demux; setup_irq(gic_spi(34), &sh73a0_pint1_cascade); } - -#ifdef CONFIG_OF -void __init sh73a0_init_irq_dt(void) -{ - irqchip_init(); - gic_arch_extn.irq_set_wake = sh73a0_set_wake; -} -#endif diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index bdab575f88bc..49483f4c76c5 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -921,7 +922,7 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") .map_io = sh73a0_map_io, .init_early = sh73a0_add_early_devices_dt, .nr_irqs = NR_IRQS_LEGACY, - .init_irq = sh73a0_init_irq_dt, + .init_irq = irqchip_init, .init_machine = sh73a0_add_standard_devices_dt, .init_time = shmobile_timer_init, .dt_compat = sh73a0_boards_compat_dt, -- cgit v1.2.1 From f998950788a4a488e37189b1bb056295cf1fe2f9 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 15 Feb 2013 21:38:20 +0900 Subject: ARM: shmobile: sh73a0: Add smp ops to DT_MACHINE_START This a board to be brought up with SMP enabled without a board file present. Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-sh73a0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 49483f4c76c5..c7630aaaa260 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -919,6 +919,7 @@ static const char *sh73a0_boards_compat_dt[] __initdata = { }; DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") + .smp = smp_ops(sh73a0_smp_ops), .map_io = sh73a0_map_io, .init_early = sh73a0_add_early_devices_dt, .nr_irqs = NR_IRQS_LEGACY, -- cgit v1.2.1 From e4e240841d62e24589cc2544430fe0c62699733a Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 15 Feb 2013 21:38:20 +0900 Subject: ARM: shmobile: sh73a0: Remove warning about SMP Remove warning about SMP not working with the clock initialisation sheme used for reference DT. This is resolved by not selecting CONFIG_PREEMPT. Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-sh73a0.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index c7630aaaa260..37baa481ce3b 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -879,14 +879,6 @@ void __init sh73a0_add_early_devices(void) #ifdef CONFIG_USE_OF -/* Please note that the clock initialisation shcheme used in - * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt() - * does not work with SMP as there is a yet to be resolved lock-up in - * workqueue initialisation. - * - * CONFIG_SMP should be disabled when using this code. - */ - void __init sh73a0_add_early_devices_dt(void) { shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ -- cgit v1.2.1 From 3b00f9342623a5ebc19bea663199864252bf3e93 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 19 Feb 2013 10:53:05 +0900 Subject: ARM: shmobile: sh73a0: Do not use early devices with DT reference Do not initialise any early devices when using the minimal DT reference code. Only the delay needs to be initialised. Cc: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 2 +- arch/arm/mach-shmobile/setup-sh73a0.c | 24 +++++++++--------------- 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 84dcaa4279b2..44cdeccaccd2 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -34,12 +34,12 @@ extern int sh7372_do_idle_sysc(unsigned long sleep_mode); extern struct clk sh7372_extal1_clk; extern struct clk sh7372_extal2_clk; +extern void sh73a0_init_delay(void); extern void sh73a0_init_irq(void); extern void sh73a0_init_irq_dt(void); extern void sh73a0_map_io(void); extern void sh73a0_earlytimer_init(void); extern void sh73a0_add_early_devices(void); -extern void sh73a0_add_early_devices_dt(void); extern void sh73a0_add_standard_devices(void); extern void sh73a0_add_standard_devices_dt(void); extern void sh73a0_clock_init(void); diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 37baa481ce3b..2257a915746d 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -811,7 +811,7 @@ static struct platform_device ipmmu_device = { .num_resources = ARRAY_SIZE(ipmmu_resources), }; -static struct platform_device *sh73a0_early_devices_dt[] __initdata = { +static struct platform_device *sh73a0_devices_dt[] __initdata = { &scif0_device, &scif1_device, &scif2_device, @@ -848,8 +848,8 @@ void __init sh73a0_add_standard_devices(void) /* Clear software reset bit on SY-DMAC module */ __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); - platform_add_devices(sh73a0_early_devices_dt, - ARRAY_SIZE(sh73a0_early_devices_dt)); + platform_add_devices(sh73a0_devices_dt, + ARRAY_SIZE(sh73a0_devices_dt)); platform_add_devices(sh73a0_early_devices, ARRAY_SIZE(sh73a0_early_devices)); platform_add_devices(sh73a0_late_devices, @@ -868,8 +868,8 @@ void __init sh73a0_earlytimer_init(void) void __init sh73a0_add_early_devices(void) { - early_platform_add_devices(sh73a0_early_devices_dt, - ARRAY_SIZE(sh73a0_early_devices_dt)); + early_platform_add_devices(sh73a0_devices_dt, + ARRAY_SIZE(sh73a0_devices_dt)); early_platform_add_devices(sh73a0_early_devices, ARRAY_SIZE(sh73a0_early_devices)); @@ -879,15 +879,9 @@ void __init sh73a0_add_early_devices(void) #ifdef CONFIG_USE_OF -void __init sh73a0_add_early_devices_dt(void) +void __init sh73a0_init_delay(void) { shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ - - early_platform_add_devices(sh73a0_early_devices_dt, - ARRAY_SIZE(sh73a0_early_devices_dt)); - - /* setup early console here as well */ - shmobile_setup_console(); } static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = { @@ -899,8 +893,8 @@ void __init sh73a0_add_standard_devices_dt(void) /* clocks are setup late during boot in the case of DT */ sh73a0_clock_init(); - platform_add_devices(sh73a0_early_devices_dt, - ARRAY_SIZE(sh73a0_early_devices_dt)); + platform_add_devices(sh73a0_devices_dt, + ARRAY_SIZE(sh73a0_devices_dt)); of_platform_populate(NULL, of_default_bus_match_table, sh73a0_auxdata_lookup, NULL); } @@ -913,7 +907,7 @@ static const char *sh73a0_boards_compat_dt[] __initdata = { DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") .smp = smp_ops(sh73a0_smp_ops), .map_io = sh73a0_map_io, - .init_early = sh73a0_add_early_devices_dt, + .init_early = sh73a0_init_delay, .nr_irqs = NR_IRQS_LEGACY, .init_irq = irqchip_init, .init_machine = sh73a0_add_standard_devices_dt, -- cgit v1.2.1 From 916ddc355f061b636a71ee5e1d0eb977ee8a6938 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 19 Feb 2013 10:53:05 +0900 Subject: ARM: shmobile: r8a7779: Do not use early devices with DT reference Do not initialise any early devices when using the minimal DT reference code. Only the delay needs to be initialised. Cc: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 2 +- arch/arm/mach-shmobile/setup-r8a7779.c | 25 +++++++++---------------- 2 files changed, 10 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 44cdeccaccd2..b8a4872f77b3 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -58,12 +58,12 @@ extern void r8a7740_clock_init(u8 md_ck); extern void r8a7740_pinmux_init(void); extern void r8a7740_pm_init(void); +extern void r8a7779_init_delay(void); extern void r8a7779_init_irq(void); extern void r8a7779_init_irq_dt(void); extern void r8a7779_map_io(void); extern void r8a7779_earlytimer_init(void); extern void r8a7779_add_early_devices(void); -extern void r8a7779_add_early_devices_dt(void); extern void r8a7779_add_standard_devices(void); extern void r8a7779_add_standard_devices_dt(void); extern void r8a7779_clock_init(void); diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 922dd4db21a0..b1f7a45b56b9 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -322,7 +322,7 @@ static struct platform_device i2c3_device = { .num_resources = ARRAY_SIZE(rcar_i2c3_res), }; -static struct platform_device *r8a7779_early_devices_dt[] __initdata = { +static struct platform_device *r8a7779_devices_dt[] __initdata = { &scif0_device, &scif1_device, &scif2_device, @@ -350,8 +350,8 @@ void __init r8a7779_add_standard_devices(void) r8a7779_init_pm_domains(); - platform_add_devices(r8a7779_early_devices_dt, - ARRAY_SIZE(r8a7779_early_devices_dt)); + platform_add_devices(r8a7779_devices_dt, + ARRAY_SIZE(r8a7779_devices_dt)); platform_add_devices(r8a7779_early_devices, ARRAY_SIZE(r8a7779_early_devices)); } @@ -368,8 +368,8 @@ void __init r8a7779_earlytimer_init(void) void __init r8a7779_add_early_devices(void) { - early_platform_add_devices(r8a7779_early_devices_dt, - ARRAY_SIZE(r8a7779_early_devices_dt)); + early_platform_add_devices(r8a7779_devices_dt, + ARRAY_SIZE(r8a7779_devices_dt)); early_platform_add_devices(r8a7779_early_devices, ARRAY_SIZE(r8a7779_early_devices)); @@ -391,16 +391,9 @@ void __init r8a7779_add_early_devices(void) } #ifdef CONFIG_USE_OF -void __init r8a7779_add_early_devices_dt(void) +void __init r8a7779_init_delay(void) { shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ - - early_platform_add_devices(r8a7779_early_devices_dt, - ARRAY_SIZE(r8a7779_early_devices_dt)); - - /* Early serial console setup is not included here. - * See comment in r8a7779_add_early_devices(). - */ } static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = { @@ -412,8 +405,8 @@ void __init r8a7779_add_standard_devices_dt(void) /* clocks are setup late during boot in the case of DT */ r8a7779_clock_init(); - platform_add_devices(r8a7779_early_devices_dt, - ARRAY_SIZE(r8a7779_early_devices_dt)); + platform_add_devices(r8a7779_devices_dt, + ARRAY_SIZE(r8a7779_devices_dt)); of_platform_populate(NULL, of_default_bus_match_table, r8a7779_auxdata_lookup, NULL); } @@ -425,7 +418,7 @@ static const char *r8a7779_compat_dt[] __initdata = { DT_MACHINE_START(SH73A0_DT, "Generic R8A7779 (Flattened Device Tree)") .map_io = r8a7779_map_io, - .init_early = r8a7779_add_early_devices_dt, + .init_early = r8a7779_init_delay, .nr_irqs = NR_IRQS_LEGACY, .init_irq = r8a7779_init_irq_dt, .init_machine = r8a7779_add_standard_devices_dt, -- cgit v1.2.1 From e792120264ee869dc98bdec3842aa5731de0705b Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 19 Feb 2013 10:53:05 +0900 Subject: ARM: shmobile: r8a7779: Do not initialise i2c as an early device It is sufficient to initialise i2c as a late device. Cc: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-r8a7779.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index b1f7a45b56b9..7f8daf17947c 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -333,7 +333,7 @@ static struct platform_device *r8a7779_devices_dt[] __initdata = { &tmu01_device, }; -static struct platform_device *r8a7779_early_devices[] __initdata = { +static struct platform_device *r8a7779_late_devices[] __initdata = { &i2c0_device, &i2c1_device, &i2c2_device, @@ -352,8 +352,8 @@ void __init r8a7779_add_standard_devices(void) platform_add_devices(r8a7779_devices_dt, ARRAY_SIZE(r8a7779_devices_dt)); - platform_add_devices(r8a7779_early_devices, - ARRAY_SIZE(r8a7779_early_devices)); + platform_add_devices(r8a7779_late_devices, + ARRAY_SIZE(r8a7779_late_devices)); } /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ @@ -370,8 +370,6 @@ void __init r8a7779_add_early_devices(void) { early_platform_add_devices(r8a7779_devices_dt, ARRAY_SIZE(r8a7779_devices_dt)); - early_platform_add_devices(r8a7779_early_devices, - ARRAY_SIZE(r8a7779_early_devices)); /* Early serial console setup is not included here due to * memory map collisions. The SCIF serial ports in r8a7779 -- cgit v1.2.1 From 8819ce4b8874ac1db7b52f7eac7cf9d8e3989102 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 19 Feb 2013 11:32:36 +0900 Subject: ARM: shmobile: r8a7779: Remove lan from dtsi The ethernet controller is not part of the r8a7779 SoC. Cc: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 2913759e93e2..0016302952ec 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -83,13 +83,4 @@ interrupt-parent = <&gic>; interrupts = <0 81 0x4>; }; - - lan0: lan0@18000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x18000000 0x100>; - phy-mode = "mii"; - interrupt-parent = <&gic>; - interrupts = <0 28 0x4>; - reg-io-width = <4>; - }; }; -- cgit v1.2.1 From 73e5709875e8b28c63ef8261d61c9eb06b499964 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:46:57 +0900 Subject: ARM: shmobile: Fix base address readout in headsmp-scu.S Rework the early SCU setup code in headsmp-scu.S to read the base address in the same way as we use to fetch the address of the invalidation function. Reported-by: Bastian Hecht Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/headsmp-scu.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S index 0b9317062b2a..7d113f898e7f 100644 --- a/arch/arm/mach-shmobile/headsmp-scu.S +++ b/arch/arm/mach-shmobile/headsmp-scu.S @@ -39,7 +39,7 @@ ENTRY(shmobile_secondary_vector_scu) mrc p15, 0, r0, c0, c0, 5 @ read MIPDR and r0, r0, #3 @ mask out cpu ID lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits - ldr r1, =shmobile_scu_base + ldr r1, 2f ldr r1, [r1] @ SCU base address ldr r2, [r1, #8] @ SCU Power Status Register mov r3, #3 @@ -48,6 +48,7 @@ ENTRY(shmobile_secondary_vector_scu) ldr pc, 1f 1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET +2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET ENDPROC(shmobile_secondary_vector_scu) .text -- cgit v1.2.1 From 76853504c35ef5cf488cf6bac4b65677f3bb672e Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:47:07 +0900 Subject: ARM: shmobile: Rework SH73A0_SCU_BASE IOMEM() usage Rework the IOMEM() usage for the SCU base address in the case of sh73a0. Removes recently introduced build warnings: arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: initialization makes integer from pointer without a cast [enabled by default] arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: (near initialization for 'twd_local_timer.res[0].start') [enabled by default] arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: initialization makes integer from pointer without a cast [enabled by default] /arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: (near initialization for 'twd_local_timer.res[0].end') [enabled by default] Reported-by: Arnd Bergmann Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-sh73a0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 2244fd074f72..593f8de28c5e 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -39,7 +39,7 @@ #define PSTR_SHUTDOWN_MODE 3 -#define SH73A0_SCU_BASE IOMEM(0xf0000000) +#define SH73A0_SCU_BASE 0xf0000000 #ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29); @@ -81,7 +81,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) static void __init sh73a0_smp_init_cpus(void) { /* setup sh73a0 specific SCU base */ - shmobile_scu_base = SH73A0_SCU_BASE; + shmobile_scu_base = IOMEM(SH73A0_SCU_BASE); shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); } -- cgit v1.2.1 From abf88136f73da52162d7e70bd1d8d4294c08bf1e Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:47:16 +0900 Subject: ARM: shmobile: Use R8A7779_SCU_BASE with TWD Rework the IOMEM() usage for the SCU base address in the case of r8a7779. Adjusts the TWD to use R8A7779_SCU_BASE. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-r8a7779.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 7fd58a3a26d8..e69ce259a2d7 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -31,7 +31,7 @@ #include #define AVECR IOMEM(0xfe700040) -#define R8A7779_SCU_BASE IOMEM(0xf0000000) +#define R8A7779_SCU_BASE 0xf0000000 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = { .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ @@ -61,8 +61,7 @@ static DEFINE_SPINLOCK(scu_lock); static unsigned long tmp; #ifdef CONFIG_HAVE_ARM_TWD -static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); - +static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29); void __init r8a7779_register_twd(void) { twd_local_timer_register(&twd_local_timer); @@ -168,7 +167,7 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) static void __init r8a7779_smp_init_cpus(void) { /* setup r8a7779 specific SCU base */ - shmobile_scu_base = R8A7779_SCU_BASE; + shmobile_scu_base = IOMEM(R8A7779_SCU_BASE); shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); } -- cgit v1.2.1 From bbf2627c77355ee07cb589904efaf814cfc223d1 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:47:25 +0900 Subject: ARM: shmobile: Update r8a7779 to check SCU for hotplug Update the r8a7779 CPU Hotplug code to use SCU PSR to wait for the target CPU core. Previously the shared code in hotplug.c was used to let cpu_kill() wait for cpu_die(). With this change in place the r8a7779 SMP code does not depend on hotplug.c anymore. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-r8a7779.c | 38 ++++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index e69ce259a2d7..63c8db966fb2 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -68,6 +69,16 @@ void __init r8a7779_register_twd(void) } #endif +static int r8a7779_scu_psr_core_disabled(int cpu) +{ + unsigned long mask = 3 << (cpu * 8); + + if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) + return 1; + + return 0; +} + static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) { void __iomem *scu_base = shmobile_scu_base; @@ -89,9 +100,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) cpu = cpu_logical_map(cpu); - /* disable cache coherency */ - modify_scu_cpu_psr(3 << (cpu * 8), 0); - if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) ch = r8a7779_ch_cpu[cpu]; @@ -110,7 +118,7 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) * finish before asking SoC-specific code to power off the CPU core. */ for (k = 0; k < 1000; k++) { - if (shmobile_cpu_is_dead(cpu)) + if (r8a7779_scu_psr_core_disabled(cpu)) return r8a7779_platform_cpu_kill(cpu); mdelay(1); @@ -119,6 +127,24 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) return 0; } +static void __maybe_unused r8a7779_cpu_die(unsigned int cpu) +{ + dsb(); + flush_cache_all(); + + /* disable cache coherency */ + modify_scu_cpu_psr(3 << (cpu * 8), 0); + + /* Endless loop until power off from r8a7779_cpu_kill() */ + while (1) + cpu_do_idle(); +} + +static int __maybe_unused r8a7779_cpu_disable(unsigned int cpu) +{ + /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */ + return cpu == 0 ? -EPERM : 0; +} static void __cpuinit r8a7779_secondary_init(unsigned int cpu) { @@ -179,7 +205,7 @@ struct smp_operations r8a7779_smp_ops __initdata = { .smp_boot_secondary = r8a7779_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = r8a7779_cpu_kill, - .cpu_die = shmobile_cpu_die, - .cpu_disable = shmobile_cpu_disable, + .cpu_die = r8a7779_cpu_die, + .cpu_disable = r8a7779_cpu_disable, #endif }; -- cgit v1.2.1 From 8bbcd729d219ca7cdc06ad3b0dea161c4c41b807 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:47:35 +0900 Subject: ARM: shmobile: Update r8a7779 to use scu_power_mode() Update the SMP code for R8A7779 to make use of the shared SCU function scu_power_mode() together with the early setup code in shmobile_secondary_vector_scu. With this patch in place the secondary CPUs modify the SCU setting during early boot instead of letting other CPUs deal with the coherency setting before boot. In other words, we used to setup coherency before boot in r8a7779_boot_secondary() but that bit is now instead handled by the code in shmobile_secondary_vector_scu. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-r8a7779.c | 32 +++++--------------------------- 1 file changed, 5 insertions(+), 27 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 63c8db966fb2..bdd38091dc9e 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -58,9 +58,6 @@ static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = { [3] = &r8a7779_ch_cpu3, }; -static DEFINE_SPINLOCK(scu_lock); -static unsigned long tmp; - #ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29); void __init r8a7779_register_twd(void) @@ -79,20 +76,6 @@ static int r8a7779_scu_psr_core_disabled(int cpu) return 0; } -static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) -{ - void __iomem *scu_base = shmobile_scu_base; - - spin_lock(&scu_lock); - tmp = __raw_readl(scu_base + 8); - tmp &= ~clr; - tmp |= set; - spin_unlock(&scu_lock); - - /* disable cache coherency after releasing the lock */ - __raw_writel(tmp, scu_base + 8); -} - static int r8a7779_platform_cpu_kill(unsigned int cpu) { struct r8a7779_pm_ch *ch = NULL; @@ -133,7 +116,7 @@ static void __maybe_unused r8a7779_cpu_die(unsigned int cpu) flush_cache_all(); /* disable cache coherency */ - modify_scu_cpu_psr(3 << (cpu * 8), 0); + scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); /* Endless loop until power off from r8a7779_cpu_kill() */ while (1) @@ -158,9 +141,6 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct cpu = cpu_logical_map(cpu); - /* enable cache coherency */ - modify_scu_cpu_psr(0, 3 << (cpu * 8)); - if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) ch = r8a7779_ch_cpu[cpu]; @@ -172,15 +152,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) { - int cpu = cpu_logical_map(0); - scu_enable(shmobile_scu_base); - /* Map the reset vector (in headsmp.S) */ - __raw_writel(__pa(shmobile_secondary_vector), AVECR); + /* Map the reset vector (in headsmp-scu.S) */ + __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR); - /* enable cache coherency on CPU0 */ - modify_scu_cpu_psr(0, 3 << (cpu * 8)); + /* enable cache coherency on booting CPU */ + scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); r8a7779_pm_init(); -- cgit v1.2.1 From eebadd676499e4c8aee181a669cc8a386e308c31 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:47:44 +0900 Subject: ARM: shmobile: Use sh73a0-specific cpu disable code Convert the sh73a0 CPU Hotplug code to use a local implementation of ->cpu_disable(). With this change in place the sh73a0 SMP code does no longer depend on hotplug.c. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-sh73a0.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 593f8de28c5e..5ae502b16437 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -124,6 +124,11 @@ static void sh73a0_cpu_die(unsigned int cpu) /* Enter shutdown mode */ cpu_do_idle(); } + +static int sh73a0_cpu_disable(unsigned int cpu) +{ + return 0; /* CPU0 and CPU1 supported */ +} #endif /* CONFIG_HOTPLUG_CPU */ struct smp_operations sh73a0_smp_ops __initdata = { @@ -134,6 +139,6 @@ struct smp_operations sh73a0_smp_ops __initdata = { #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = sh73a0_cpu_kill, .cpu_die = sh73a0_cpu_die, - .cpu_disable = shmobile_cpu_disable_any, + .cpu_disable = sh73a0_cpu_disable, #endif }; -- cgit v1.2.1 From fd0865c3f7054d9068007fd280681cb4ea7929a1 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:47:54 +0900 Subject: ARM: shmobile: Rearrange r8a7779 cpu hotplug code Update the r8a7779 SMP code and CPU Hotplug in particular to follow the same style as sh73a0. This means dropping __maybe_unused for #ifdef CONFIG_HOTPLUG_CPU. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-r8a7779.c | 96 ++++++++++++++++++------------------ 1 file changed, 49 insertions(+), 47 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index bdd38091dc9e..ea4535a5c4e2 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -66,16 +66,6 @@ void __init r8a7779_register_twd(void) } #endif -static int r8a7779_scu_psr_core_disabled(int cpu) -{ - unsigned long mask = 3 << (cpu * 8); - - if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) - return 1; - - return 0; -} - static int r8a7779_platform_cpu_kill(unsigned int cpu) { struct r8a7779_pm_ch *ch = NULL; @@ -92,43 +82,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) return ret ? ret : 1; } -static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) -{ - int k; - - /* this function is running on another CPU than the offline target, - * here we need wait for shutdown code in platform_cpu_die() to - * finish before asking SoC-specific code to power off the CPU core. - */ - for (k = 0; k < 1000; k++) { - if (r8a7779_scu_psr_core_disabled(cpu)) - return r8a7779_platform_cpu_kill(cpu); - - mdelay(1); - } - - return 0; -} - -static void __maybe_unused r8a7779_cpu_die(unsigned int cpu) -{ - dsb(); - flush_cache_all(); - - /* disable cache coherency */ - scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); - - /* Endless loop until power off from r8a7779_cpu_kill() */ - while (1) - cpu_do_idle(); -} - -static int __maybe_unused r8a7779_cpu_disable(unsigned int cpu) -{ - /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */ - return cpu == 0 ? -EPERM : 0; -} - static void __cpuinit r8a7779_secondary_init(unsigned int cpu) { gic_secondary_init(0); @@ -176,6 +129,55 @@ static void __init r8a7779_smp_init_cpus(void) shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); } +#ifdef CONFIG_HOTPLUG_CPU +static int r8a7779_scu_psr_core_disabled(int cpu) +{ + unsigned long mask = 3 << (cpu * 8); + + if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) + return 1; + + return 0; +} + +static int r8a7779_cpu_kill(unsigned int cpu) +{ + int k; + + /* this function is running on another CPU than the offline target, + * here we need wait for shutdown code in platform_cpu_die() to + * finish before asking SoC-specific code to power off the CPU core. + */ + for (k = 0; k < 1000; k++) { + if (r8a7779_scu_psr_core_disabled(cpu)) + return r8a7779_platform_cpu_kill(cpu); + + mdelay(1); + } + + return 0; +} + +static void r8a7779_cpu_die(unsigned int cpu) +{ + dsb(); + flush_cache_all(); + + /* disable cache coherency */ + scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); + + /* Endless loop until power off from r8a7779_cpu_kill() */ + while (1) + cpu_do_idle(); +} + +static int r8a7779_cpu_disable(unsigned int cpu) +{ + /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */ + return cpu == 0 ? -EPERM : 0; +} +#endif /* CONFIG_HOTPLUG_CPU */ + struct smp_operations r8a7779_smp_ops __initdata = { .smp_init_cpus = r8a7779_smp_init_cpus, .smp_prepare_cpus = r8a7779_smp_prepare_cpus, -- cgit v1.2.1 From 5e4460fcc845ae669e20eac67558871d3f0ca432 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 22:48:03 +0900 Subject: ARM: shmobile: Remove unused hotplug.c Each CPU Hotplug implementation for mach-shmobile is now self-contained, so this change removes unused helper code in hotplug.c. The two CPU Hotplug capable SoCs sh73a0 and r8a7779 remain unchanged. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Makefile | 1 - arch/arm/mach-shmobile/hotplug.c | 64 ---------------------------- arch/arm/mach-shmobile/include/mach/common.h | 10 ----- 3 files changed, 75 deletions(-) delete mode 100644 arch/arm/mach-shmobile/hotplug.c diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index d7d20579bef7..b646ff4d742a 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -14,7 +14,6 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o # SMP objects smp-y := platsmp.o headsmp.o -smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c deleted file mode 100644 index efd0b36a4175..000000000000 --- a/arch/arm/mach-shmobile/hotplug.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * SMP support for R-Mobile / SH-Mobile - * - * Copyright (C) 2010 Magnus Damm - * - * Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include -#include - -static cpumask_t dead_cpus; - -void shmobile_cpu_die(unsigned int cpu) -{ - /* hardware shutdown code running on the CPU that is being offlined */ - flush_cache_all(); - dsb(); - - /* notify platform_cpu_kill() that hardware shutdown is finished */ - cpumask_set_cpu(cpu, &dead_cpus); - - /* wait for SoC code in platform_cpu_kill() to shut off CPU core - * power. CPU bring up starts from the reset vector. - */ - while (1) { - /* - * here's the WFI - */ - asm(".word 0xe320f003\n" - : - : - : "memory", "cc"); - } -} - -int shmobile_cpu_disable(unsigned int cpu) -{ - cpumask_clear_cpu(cpu, &dead_cpus); - /* - * we don't allow CPU 0 to be shutdown (it is still too special - * e.g. clock tick interrupts) - */ - return cpu == 0 ? -EPERM : 0; -} - -int shmobile_cpu_disable_any(unsigned int cpu) -{ - cpumask_clear_cpu(cpu, &dead_cpus); - return 0; -} - -int shmobile_cpu_is_dead(unsigned int cpu) -{ - return cpumask_test_cpu(cpu, &dead_cpus); -} diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index b8a4872f77b3..1ca1ad938d19 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -85,16 +85,6 @@ int shmobile_cpuidle_init(void); static inline int shmobile_cpuidle_init(void) { return 0; } #endif -extern void shmobile_cpu_die(unsigned int cpu); -extern int shmobile_cpu_disable(unsigned int cpu); -extern int shmobile_cpu_disable_any(unsigned int cpu); - -#ifdef CONFIG_HOTPLUG_CPU -extern int shmobile_cpu_is_dead(unsigned int cpu); -#else -static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; } -#endif - extern void __iomem *shmobile_scu_base; extern void shmobile_smp_init_cpus(unsigned int ncores); -- cgit v1.2.1 From 386e9464fab9beb6d55081edb120f2ed9a22ca41 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Tue, 26 Feb 2013 11:03:27 -0600 Subject: ARM: mach-shmobile: r8a7740: Add DT names to clock list This adds temporarily the alternative device names to the clock list that are used when booting via Device Tree setup. Signed-off-by: Bastian Hecht Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7740.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index 1a9b9a29442a..1feb9a2286a8 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -593,18 +593,27 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]), CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), + CLKDEV_DEV_ID("e6c80000.sci", &mstp_clks[MSTP200]), CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), + CLKDEV_DEV_ID("e6c70000.sci", &mstp_clks[MSTP201]), CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), + CLKDEV_DEV_ID("e6c60000.sci", &mstp_clks[MSTP202]), CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), + CLKDEV_DEV_ID("e6c50000.sci", &mstp_clks[MSTP203]), CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), + CLKDEV_DEV_ID("e6c40000.sci", &mstp_clks[MSTP204]), CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), + CLKDEV_DEV_ID("e6c30000.sci", &mstp_clks[MSTP206]), CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), + CLKDEV_DEV_ID("e6cb0000.sci", &mstp_clks[MSTP207]), CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), + CLKDEV_DEV_ID("e6cd0000.sci", &mstp_clks[MSTP222]), CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), + CLKDEV_DEV_ID("e6cc0000.sci", &mstp_clks[MSTP230]), CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), -- cgit v1.2.1 From 652f9452781630cb624928c48803db353cdeb09f Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 25 Feb 2013 01:39:44 -0800 Subject: ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID R-Car H1 datasheet GIC number is indicating GIC ICCIAR / interrupt ID number, not SPI number, but current marzen board code is using gic_spi() with un-understandable calculation. This patch adds new gic_iid() macro which means ICCIAR / interrupt ID, and used the number currently written on datasheet. Signed-off-by: Kuninori Morimoto [ horms+renesas@verge.net.au: Split board-marzen.c portion into a separate patch ] Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/irqs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h index 06a5da3c3050..992ed213cec1 100644 --- a/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/arch/arm/mach-shmobile/include/mach/irqs.h @@ -5,6 +5,7 @@ /* GIC */ #define gic_spi(nr) ((nr) + 32) +#define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */ /* INTCS */ #define INTCS_VECT_BASE 0x3400 -- cgit v1.2.1 From 349f556edd9bdf691d85f38758021668b1013d8e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 3 Mar 2013 23:11:03 -0800 Subject: ARM: shmobile: r8a7779: fixup dtsi typo r8a7779 is not r8a7740 chip Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 0016302952ec..c73eb3771be9 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -1,5 +1,5 @@ /* - * Device Tree Source for Renesas r8a7740 + * Device Tree Source for Renesas r8a7779 * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Simon Horman -- cgit v1.2.1 From abe0e14b0b51b26bdf80ccaf4d7ee99a4b261af0 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 3 Mar 2013 23:11:20 -0800 Subject: ARM: shmobile: r8a7779: fixup DT machine name r8a7779 is not sh73a0 Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-r8a7779.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 7f8daf17947c..932285841b71 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -414,7 +414,7 @@ static const char *r8a7779_compat_dt[] __initdata = { NULL, }; -DT_MACHINE_START(SH73A0_DT, "Generic R8A7779 (Flattened Device Tree)") +DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") .map_io = r8a7779_map_io, .init_early = r8a7779_init_delay, .nr_irqs = NR_IRQS_LEGACY, -- cgit v1.2.1 From dbe95ad00b95a8baaedd87ce84996d95e5811055 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 3 Mar 2013 23:11:41 -0800 Subject: ARM: shmobile: r8a7779: use gic_iid macro "ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID" enabled to use gic_iid macro. This patch exchange current GIC interrupt setting from gic_spi() to gic_iid() Signed-off-by: Kuninori Morimoto [ horms+renesas@verge.net.au: Updated git commit id in changelog ] Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-r8a7779.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 932285841b71..0068b9f85bc0 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -92,7 +92,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_spi(88)), + .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)), }; static struct platform_device scif0_device = { @@ -109,7 +109,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_spi(89)), + .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)), }; static struct platform_device scif1_device = { @@ -126,7 +126,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_spi(90)), + .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)), }; static struct platform_device scif2_device = { @@ -143,7 +143,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_spi(91)), + .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)), }; static struct platform_device scif3_device = { @@ -160,7 +160,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_spi(92)), + .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)), }; static struct platform_device scif4_device = { @@ -177,7 +177,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_spi(93)), + .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)), }; static struct platform_device scif5_device = { @@ -204,7 +204,7 @@ static struct resource tmu00_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(32), + .start = gic_iid(0x40), .flags = IORESOURCE_IRQ, }, }; @@ -234,7 +234,7 @@ static struct resource tmu01_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(33), + .start = gic_iid(0x41), .flags = IORESOURCE_IRQ, }, }; @@ -256,7 +256,7 @@ static struct resource rcar_i2c0_res[] = { .end = 0xffc70fff, .flags = IORESOURCE_MEM, }, { - .start = gic_spi(79), + .start = gic_iid(0x6f), .flags = IORESOURCE_IRQ, }, }; @@ -274,7 +274,7 @@ static struct resource rcar_i2c1_res[] = { .end = 0xffc71fff, .flags = IORESOURCE_MEM, }, { - .start = gic_spi(82), + .start = gic_iid(0x72), .flags = IORESOURCE_IRQ, }, }; @@ -292,7 +292,7 @@ static struct resource rcar_i2c2_res[] = { .end = 0xffc72fff, .flags = IORESOURCE_MEM, }, { - .start = gic_spi(80), + .start = gic_iid(0x70), .flags = IORESOURCE_IRQ, }, }; @@ -310,7 +310,7 @@ static struct resource rcar_i2c3_res[] = { .end = 0xffc73fff, .flags = IORESOURCE_MEM, }, { - .start = gic_spi(81), + .start = gic_iid(0x71), .flags = IORESOURCE_IRQ, }, }; -- cgit v1.2.1 From 195f96220143dc2672bfb84db9aad3ee536a6c98 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 3 Mar 2013 23:30:19 -0800 Subject: ARM: shmobile: tidyup chip series definition order for r8a7740/r8a7779 move r8a7740_meram_workaround() to r8a7740 area from r8a7779 area Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 1ca1ad938d19..86fcdf9fde1b 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -50,6 +50,7 @@ extern struct clk sh73a0_extal2_clk; extern struct clk sh73a0_extcki_clk; extern struct clk sh73a0_extalr_clk; +extern void r8a7740_meram_workaround(void); extern void r8a7740_init_irq(void); extern void r8a7740_map_io(void); extern void r8a7740_add_early_devices(void); @@ -69,8 +70,6 @@ extern void r8a7779_add_standard_devices_dt(void); extern void r8a7779_clock_init(void); extern void r8a7779_pinmux_init(void); extern void r8a7779_pm_init(void); -extern void r8a7740_meram_workaround(void); - extern void r8a7779_register_twd(void); #ifdef CONFIG_SUSPEND -- cgit v1.2.1 From 25a65975fc33826cfb8cdc399c5bb7f4b5364c51 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 4 Mar 2013 00:32:16 -0800 Subject: ARM: shmobile: r8a7779: add Thermal support on DT 76cc1887496fe80138c6b07c37d7f81e4cf27cde (thermal: rcar: add Device Tree support) supported rcar_thermal DT probing. rcar thermal driver doesn't support IRQ on r8a7779 chip since it is using old design IRQ. R-Car/R-Mobile next generation chips are using new design IRQ, and rcar thermal driver is supporting these. This patch adds rcar_thermal DT support for r8a7779 without IRQ. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index c73eb3771be9..18383db464b0 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -83,4 +83,9 @@ interrupt-parent = <&gic>; interrupts = <0 81 0x4>; }; + + thermal@ffc48000 { + compatible = "renesas,rcar-thermal"; + reg = <0xffc48000 0x38>; + }; }; -- cgit v1.2.1 From 7840a65a0384f87b7d02fdaff5001a6d8f5f6491 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 27 Feb 2013 23:34:36 +0300 Subject: ARM: mach-shmobile: r8a7779: SATA DT configuration Allow configuration of the r8a7779 SoC SATA controller using a flattened device tree. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 18383db464b0..fe5c6f213271 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -88,4 +88,11 @@ compatible = "renesas,rcar-thermal"; reg = <0xffc48000 0x38>; }; + + sata: sata@fc600000 { + compatible = "renesas,rcar-sata"; + reg = <0xfc600000 0x2000>; + interrupt-parent = <&gic>; + interrupts = <0 100 0x4>; + }; }; -- cgit v1.2.1 From a7b9837c7749bf3333151a7d060d239caff1569d Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 27 Feb 2013 23:39:14 +0300 Subject: ARM: mach-shmobile: r8a7779: add SATA support Add SATA clock for r8a7779 SoC (for both device tree and usual cases). Register SATA controller as a "late" platform device on r8a7779 SoC. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7779.c | 4 ++++ arch/arm/mach-shmobile/setup-r8a7779.c | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 1db36537255c..0f66d356e1bc 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -87,6 +87,7 @@ static struct clk div4_clks[DIV4_NR] = { }; enum { MSTP323, MSTP322, MSTP321, MSTP320, + MSTP115, MSTP101, MSTP100, MSTP030, MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, @@ -99,6 +100,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ + [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */ [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */ [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */ @@ -156,6 +158,8 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), /* MSTP32 clocks */ + CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ + CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */ CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */ CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 0068b9f85bc0..10031fef074a 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -322,6 +323,30 @@ static struct platform_device i2c3_device = { .num_resources = ARRAY_SIZE(rcar_i2c3_res), }; +static struct resource sata_resources[] = { + [0] = { + .name = "rcar-sata", + .start = 0xfc600000, + .end = 0xfc601fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(100), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sata_device = { + .name = "sata_rcar", + .id = -1, + .resource = sata_resources, + .num_resources = ARRAY_SIZE(sata_resources), + .dev = { + .dma_mask = &sata_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + static struct platform_device *r8a7779_devices_dt[] __initdata = { &scif0_device, &scif1_device, @@ -338,6 +363,7 @@ static struct platform_device *r8a7779_late_devices[] __initdata = { &i2c1_device, &i2c2_device, &i2c3_device, + &sata_device, }; void __init r8a7779_add_standard_devices(void) -- cgit v1.2.1 From d60cd5f16b5af62672209eddd64f70be3f68d17b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 8 Mar 2013 02:31:03 +0300 Subject: ARM: shmobile: R8A7779: use gic_iid() in SATA IRQ resource Commit "ARM: shmobile: r8a7779: use gic_iid macro" switched R8A7779 platform devices to using gic_iid() macro instead of gic_spi() but commit "ARM: mach- shmobile: r8a7779: add SATA support" added another use of gic_spi(). Convert the SATA IRQ resource to using gic_iid(). Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-r8a7779.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 10031fef074a..042df35e71a0 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -331,7 +331,7 @@ static struct resource sata_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(100), + .start = gic_iid(0x84), .flags = IORESOURCE_IRQ, }, }; -- cgit v1.2.1 From d75bc78b508d0a95d7738290d8ec9923691f4301 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Thu, 31 Jan 2013 02:45:01 +0100 Subject: r8a7779: Add Display Unit clock support Signed-off-by: Phil Edworthy [Rename device from to rcarfb to rcar-du] Signed-off-by: Laurent Pinchart [Manual conflict resolution] Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7779.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 0f66d356e1bc..d9edeaf66007 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -88,7 +88,7 @@ static struct clk div4_clks[DIV4_NR] = { enum { MSTP323, MSTP322, MSTP321, MSTP320, MSTP115, - MSTP101, MSTP100, + MSTP103, MSTP101, MSTP100, MSTP030, MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, MSTP016, MSTP015, MSTP014, @@ -101,6 +101,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */ + [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1, 3, 0), /* DU */ [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */ [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */ @@ -184,6 +185,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ + CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */ }; void __init r8a7779_clock_init(void) -- cgit v1.2.1 From 443580486e3b96578928c1c91e8fbdcf0c9c9c7f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Feb 2013 23:28:34 +0900 Subject: irqchip: Renesas INTC External IRQ pin driver This patch adds a driver for external IRQ pins connected to the INTC block on recent SoCs from Renesas. The INTC hardware block usually contains a rather wide range of features ranging from external IRQ pin handling to legacy interrupt controller support. On older SoCs the INTC is used as a general purpose interrupt controller both for external IRQ pins and on-chip devices. On more recent ARM based SoCs with Cortex-A9 the main interrupt controller is the GIC, but IRQ trigger setup still need to happen in the INTC hardware block. This driver implements the glue code needed to configure IRQ trigger and also handle mask/unmask and demux of external IRQ pins hooked up from the INTC to the GIC. Tested on sh73a0 and r8a7779. The hardware varies quite a bit with SoC model, for instance register width and bitfield widths vary wildly. The driver requires one GIC SPI per external IRQ pin to operate. Each driver instance will handle up to 8 external IRQ pins. The SoCs using this driver are currently mainly used together with regular platform devices so this driver allows configuration via platform data to support things like static interrupt base address. DT support will be added incrementally in the not so distant future. Signed-off-by: Magnus Damm Acked-by: Thomas Gleixner Signed-off-by: Simon Horman --- drivers/irqchip/Kconfig | 4 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-intc-irqpin.c | 464 +++++++++++++++++++++ .../linux/platform_data/irq-renesas-intc-irqpin.h | 10 + 4 files changed, 479 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-intc-irqpin.c create mode 100644 include/linux/platform_data/irq-renesas-intc-irqpin.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index a350969e5efe..0f5f1c3825bc 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -25,6 +25,10 @@ config ARM_VIC_NR The maximum number of VICs available in the system, for power management. +config RENESAS_INTC_IRQPIN + bool + select IRQ_DOMAIN + config VERSATILE_FPGA_IRQ bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 98e3b87bdf1b..1aaa4073ab60 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o obj-$(CONFIG_ARM_GIC) += irq-gic.o obj-$(CONFIG_ARM_VIC) += irq-vic.o +obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c new file mode 100644 index 000000000000..1e5058a56517 --- /dev/null +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -0,0 +1,464 @@ +/* + * Renesas INTC External IRQ Pin Driver + * + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */ + +#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */ +#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */ +#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */ +#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */ +#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */ +#define INTC_IRQPIN_REG_NR 5 + +/* INTC external IRQ PIN hardware register access: + * + * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*) + * PRIO is read-write 32-bit with 4-bits per IRQ (**) + * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***) + * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***) + * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***) + * + * (*) May be accessed by more than one driver instance - lock needed + * (**) Read-modify-write access by one driver instance - lock needed + * (***) Accessed by one driver instance only - no locking needed + */ + +struct intc_irqpin_iomem { + void __iomem *iomem; + unsigned long (*read)(void __iomem *iomem); + void (*write)(void __iomem *iomem, unsigned long data); + int width; +}; + +struct intc_irqpin_irq { + int hw_irq; + int irq; + struct intc_irqpin_priv *p; +}; + +struct intc_irqpin_priv { + struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR]; + struct intc_irqpin_irq irq[INTC_IRQPIN_MAX]; + struct renesas_intc_irqpin_config config; + unsigned int number_of_irqs; + struct platform_device *pdev; + struct irq_chip irq_chip; + struct irq_domain *irq_domain; +}; + +static unsigned long intc_irqpin_read32(void __iomem *iomem) +{ + return ioread32(iomem); +} + +static unsigned long intc_irqpin_read8(void __iomem *iomem) +{ + return ioread8(iomem); +} + +static void intc_irqpin_write32(void __iomem *iomem, unsigned long data) +{ + iowrite32(data, iomem); +} + +static void intc_irqpin_write8(void __iomem *iomem, unsigned long data) +{ + iowrite8(data, iomem); +} + +static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p, + int reg) +{ + struct intc_irqpin_iomem *i = &p->iomem[reg]; + return i->read(i->iomem); +} + +static inline void intc_irqpin_write(struct intc_irqpin_priv *p, + int reg, unsigned long data) +{ + struct intc_irqpin_iomem *i = &p->iomem[reg]; + i->write(i->iomem, data); +} + +static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p, + int reg, int hw_irq) +{ + return BIT((p->iomem[reg].width - 1) - hw_irq); +} + +static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p, + int reg, int hw_irq) +{ + intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq)); +} + +static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */ + +static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p, + int reg, int shift, + int width, int value) +{ + unsigned long flags; + unsigned long tmp; + + raw_spin_lock_irqsave(&intc_irqpin_lock, flags); + + tmp = intc_irqpin_read(p, reg); + tmp &= ~(((1 << width) - 1) << shift); + tmp |= value << shift; + intc_irqpin_write(p, reg, tmp); + + raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags); +} + +static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, + int irq, int do_mask) +{ + int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */ + int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */ + + intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO, + shift, bitfield_width, + do_mask ? 0 : (1 << bitfield_width) - 1); +} + +static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) +{ + int bitfield_width = p->config.sense_bitfield_width; + int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */ + + dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value); + + if (value >= (1 << bitfield_width)) + return -EINVAL; + + intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift, + bitfield_width, value); + return 0; +} + +static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str) +{ + dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", + str, i->irq, i->hw_irq, + irq_find_mapping(i->p->irq_domain, i->hw_irq)); +} + +static void intc_irqpin_irq_enable(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + intc_irqpin_dbg(&p->irq[hw_irq], "enable"); + intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); +} + +static void intc_irqpin_irq_disable(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + intc_irqpin_dbg(&p->irq[hw_irq], "disable"); + intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); +} + +static void intc_irqpin_irq_enable_force(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int irq = p->irq[irqd_to_hwirq(d)].irq; + + intc_irqpin_irq_enable(d); + irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq)); +} + +static void intc_irqpin_irq_disable_force(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int irq = p->irq[irqd_to_hwirq(d)].irq; + + irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq)); + intc_irqpin_irq_disable(d); +} + +#define INTC_IRQ_SENSE_VALID 0x10 +#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID) + +static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = { + [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00), + [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01), + [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02), + [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03), + [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04), +}; + +static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type) +{ + unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK]; + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + + if (!(value & INTC_IRQ_SENSE_VALID)) + return -EINVAL; + + return intc_irqpin_set_sense(p, irqd_to_hwirq(d), + value ^ INTC_IRQ_SENSE_VALID); +} + +static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id) +{ + struct intc_irqpin_irq *i = dev_id; + struct intc_irqpin_priv *p = i->p; + unsigned long bit; + + intc_irqpin_dbg(i, "demux1"); + bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq); + + if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) { + intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit); + intc_irqpin_dbg(i, "demux2"); + generic_handle_irq(irq_find_mapping(p->irq_domain, i->hw_irq)); + return IRQ_HANDLED; + } + return IRQ_NONE; +} + +static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct intc_irqpin_priv *p = h->host_data; + + intc_irqpin_dbg(&p->irq[hw], "map"); + irq_set_chip_data(virq, h->host_data); + irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); + set_irq_flags(virq, IRQF_VALID); /* kill me now */ + return 0; +} + +static struct irq_domain_ops intc_irqpin_irq_domain_ops = { + .map = intc_irqpin_irq_domain_map, +}; + +static int intc_irqpin_probe(struct platform_device *pdev) +{ + struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data; + struct intc_irqpin_priv *p; + struct intc_irqpin_iomem *i; + struct resource *io[INTC_IRQPIN_REG_NR]; + struct resource *irq; + struct irq_chip *irq_chip; + void (*enable_fn)(struct irq_data *d); + void (*disable_fn)(struct irq_data *d); + const char *name = dev_name(&pdev->dev); + int ret; + int k; + + p = kzalloc(sizeof(*p), GFP_KERNEL); + if (!p) { + dev_err(&pdev->dev, "failed to allocate driver data\n"); + ret = -ENOMEM; + goto err0; + } + + /* deal with driver instance configuration */ + if (pdata) + memcpy(&p->config, pdata, sizeof(*pdata)); + if (!p->config.sense_bitfield_width) + p->config.sense_bitfield_width = 4; /* default to 4 bits */ + + p->pdev = pdev; + platform_set_drvdata(pdev, p); + + /* get hold of manadatory IOMEM */ + for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { + io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k); + if (!io[k]) { + dev_err(&pdev->dev, "not enough IOMEM resources\n"); + ret = -EINVAL; + goto err1; + } + } + + /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */ + for (k = 0; k < INTC_IRQPIN_MAX; k++) { + irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); + if (!irq) + break; + + p->irq[k].hw_irq = k; + p->irq[k].p = p; + p->irq[k].irq = irq->start; + } + + p->number_of_irqs = k; + if (p->number_of_irqs < 1) { + dev_err(&pdev->dev, "not enough IRQ resources\n"); + ret = -EINVAL; + goto err1; + } + + /* ioremap IOMEM and setup read/write callbacks */ + for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { + i = &p->iomem[k]; + + switch (resource_size(io[k])) { + case 1: + i->width = 8; + i->read = intc_irqpin_read8; + i->write = intc_irqpin_write8; + break; + case 4: + i->width = 32; + i->read = intc_irqpin_read32; + i->write = intc_irqpin_write32; + break; + default: + dev_err(&pdev->dev, "IOMEM size mismatch\n"); + ret = -EINVAL; + goto err2; + } + + i->iomem = ioremap_nocache(io[k]->start, resource_size(io[k])); + if (!i->iomem) { + dev_err(&pdev->dev, "failed to remap IOMEM\n"); + ret = -ENXIO; + goto err2; + } + } + + /* mask all interrupts using priority */ + for (k = 0; k < p->number_of_irqs; k++) + intc_irqpin_mask_unmask_prio(p, k, 1); + + /* use more severe masking method if requested */ + if (p->config.control_parent) { + enable_fn = intc_irqpin_irq_enable_force; + disable_fn = intc_irqpin_irq_disable_force; + } else { + enable_fn = intc_irqpin_irq_enable; + disable_fn = intc_irqpin_irq_disable; + } + + irq_chip = &p->irq_chip; + irq_chip->name = name; + irq_chip->irq_mask = disable_fn; + irq_chip->irq_unmask = enable_fn; + irq_chip->irq_enable = enable_fn; + irq_chip->irq_disable = disable_fn; + irq_chip->irq_set_type = intc_irqpin_irq_set_type; + irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; + + p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, + p->number_of_irqs, + p->config.irq_base, + &intc_irqpin_irq_domain_ops, p); + if (!p->irq_domain) { + ret = -ENXIO; + dev_err(&pdev->dev, "cannot initialize irq domain\n"); + goto err2; + } + + /* request and set priority on interrupts one by one */ + for (k = 0; k < p->number_of_irqs; k++) { + if (request_irq(p->irq[k].irq, intc_irqpin_irq_handler, + 0, name, &p->irq[k])) { + dev_err(&pdev->dev, "failed to request low IRQ\n"); + ret = -ENOENT; + goto err3; + } + intc_irqpin_mask_unmask_prio(p, k, 0); + } + + dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); + + /* warn in case of mismatch if irq base is specified */ + if (p->config.irq_base) { + k = irq_find_mapping(p->irq_domain, 0); + if (p->config.irq_base != k) + dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n", + p->config.irq_base, k); + } + + return 0; + +err3: + for (; k >= 0; k--) + free_irq(p->irq[k - 1].irq, &p->irq[k - 1]); + + irq_domain_remove(p->irq_domain); +err2: + for (k = 0; k < INTC_IRQPIN_REG_NR; k++) + iounmap(p->iomem[k].iomem); +err1: + kfree(p); +err0: + return ret; +} + +static int intc_irqpin_remove(struct platform_device *pdev) +{ + struct intc_irqpin_priv *p = platform_get_drvdata(pdev); + int k; + + for (k = 0; k < p->number_of_irqs; k++) + free_irq(p->irq[k].irq, &p->irq[k]); + + irq_domain_remove(p->irq_domain); + + for (k = 0; k < INTC_IRQPIN_REG_NR; k++) + iounmap(p->iomem[k].iomem); + + kfree(p); + return 0; +} + +static struct platform_driver intc_irqpin_device_driver = { + .probe = intc_irqpin_probe, + .remove = intc_irqpin_remove, + .driver = { + .name = "renesas_intc_irqpin", + } +}; + +static int __init intc_irqpin_init(void) +{ + return platform_driver_register(&intc_irqpin_device_driver); +} +postcore_initcall(intc_irqpin_init); + +static void __exit intc_irqpin_exit(void) +{ + platform_driver_unregister(&intc_irqpin_device_driver); +} +module_exit(intc_irqpin_exit); + +MODULE_AUTHOR("Magnus Damm"); +MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/platform_data/irq-renesas-intc-irqpin.h b/include/linux/platform_data/irq-renesas-intc-irqpin.h new file mode 100644 index 000000000000..00ccac34dac8 --- /dev/null +++ b/include/linux/platform_data/irq-renesas-intc-irqpin.h @@ -0,0 +1,10 @@ +#ifndef __IRQ_RENESAS_INTC_IRQPIN_H__ +#define __IRQ_RENESAS_INTC_IRQPIN_H__ + +struct renesas_intc_irqpin_config { + unsigned int sense_bitfield_width; + unsigned int irq_base; + bool control_parent; +}; + +#endif /* __IRQ_RENESAS_INTC_IRQPIN_H__ */ -- cgit v1.2.1 From 1f4f11c671dacc219fae538ecf691fd212e295a6 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 12:00:59 +0900 Subject: ARM: shmobile: irq_pin() for static IRQ pin assignment Add the macro irq_pin() to let board-specific code using platform devices tie in external IRQn pins in a common way. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/irqs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h index 992ed213cec1..b2074e2acb15 100644 --- a/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/arch/arm/mach-shmobile/include/mach/irqs.h @@ -12,4 +12,8 @@ #define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) #define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) +/* External IRQ pins */ +#define IRQPIN_BASE 2000 +#define irq_pin(nr) ((nr) + IRQPIN_BASE) + #endif /* __ASM_MACH_IRQS_H */ -- cgit v1.2.1 From 341eb5465f67437ad37ef2f6302b581beda4614a Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 12:01:09 +0900 Subject: ARM: shmobile: INTC External IRQ pin driver on sh73a0 Adjust the sh73a0 IRQ code to make use of the INTC External IRQ pin driver for external interrupt pins IRQ0 -> IRQ31. This removes quite a bit of special-case code in intc-sh73a0.c but the number of lines get replaced with platform device information in setup-sh73a0.c. The PFC code is also adjusted to make gpio_to_irq() return the correct interrupt number. At this point the DT reference implementations are not covered. In the future such code shall tie in the INTC External IRQ pin driver via DT, so this kind of verbose code is not needed for the long term DT case. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/board-kzm9g.c | 14 ++-- arch/arm/mach-shmobile/intc-sh73a0.c | 117 ------------------------------- arch/arm/mach-shmobile/setup-sh73a0.c | 126 ++++++++++++++++++++++++++++++++++ drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 6 +- 5 files changed, 137 insertions(+), 127 deletions(-) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 9255546e7bf6..f964accbce24 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -16,6 +16,7 @@ config ARCH_SH73A0 select CPU_V7 select I2C select SH_CLK_CPG + select RENESAS_INTC_IRQPIN config ARCH_R8A7740 bool "R-Mobile A1 (R8A77400)" diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index 7f3a6b7e7b7c..d34d12ae496b 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -81,7 +81,7 @@ static struct resource smsc9221_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0x260), /* IRQ3 */ + .start = irq_pin(3), /* IRQ3 */ .flags = IORESOURCE_IRQ, }, }; @@ -115,7 +115,7 @@ static struct resource usb_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0x220), /* IRQ1 */ + .start = irq_pin(1), /* IRQ1 */ .flags = IORESOURCE_IRQ, }, }; @@ -138,7 +138,7 @@ struct usbhs_private { struct renesas_usbhs_platform_info info; }; -#define IRQ15 intcs_evt2irq(0x03e0) +#define IRQ15 irq_pin(15) #define USB_PHY_MODE (1 << 4) #define USB_PHY_INT_EN ((1 << 3) | (1 << 2)) #define USB_PHY_ON (1 << 1) @@ -563,25 +563,25 @@ static struct i2c_board_info i2c0_devices[] = { }, { I2C_BOARD_INFO("ak8975", 0x0c), - .irq = intcs_evt2irq(0x3380), /* IRQ28 */ + .irq = irq_pin(28), /* IRQ28 */ }, { I2C_BOARD_INFO("adxl34x", 0x1d), - .irq = intcs_evt2irq(0x3340), /* IRQ26 */ + .irq = irq_pin(26), /* IRQ26 */ }, }; static struct i2c_board_info i2c1_devices[] = { { I2C_BOARD_INFO("st1232-ts", 0x55), - .irq = intcs_evt2irq(0x300), /* IRQ8 */ + .irq = irq_pin(8), /* IRQ8 */ }, }; static struct i2c_board_info i2c3_devices[] = { { I2C_BOARD_INFO("pcf8575", 0x20), - .irq = intcs_evt2irq(0x3260), /* IRQ19 */ + .irq = irq_pin(19), /* IRQ19 */ .platform_data = &pcf8575_pdata, }, }; diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c index a81a1d804e2e..19a26f4579b3 100644 --- a/arch/arm/mach-shmobile/intc-sh73a0.c +++ b/arch/arm/mach-shmobile/intc-sh73a0.c @@ -260,108 +260,6 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on) return 0; /* always allow wakeup */ } -#define RELOC_BASE 0x1200 - -/* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */ -#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE) - -INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, - INTCS_VECT_RELOC, "sh73a0-intca-irq-pins"); - -static int to_gic_irq(struct irq_data *data) -{ - unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE; - - if (vect >= 0x3200) - vect -= 0x3000; - else - vect -= 0x0200; - - return gic_spi((vect >> 5) + 1); -} - -static int to_intca_reloc_irq(struct irq_data *data) -{ - return data->irq + (RELOC_BASE >> 5); -} - -#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq)) -#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p) - -static void intca_gic_enable(struct irq_data *data) -{ - irq_cb(irq_unmask, to_intca_reloc_irq(data)); - irq_cb(irq_unmask, to_gic_irq(data)); -} - -static void intca_gic_disable(struct irq_data *data) -{ - irq_cb(irq_mask, to_gic_irq(data)); - irq_cb(irq_mask, to_intca_reloc_irq(data)); -} - -static void intca_gic_mask_ack(struct irq_data *data) -{ - irq_cb(irq_mask, to_gic_irq(data)); - irq_cb(irq_mask_ack, to_intca_reloc_irq(data)); -} - -static void intca_gic_eoi(struct irq_data *data) -{ - irq_cb(irq_eoi, to_gic_irq(data)); -} - -static int intca_gic_set_type(struct irq_data *data, unsigned int type) -{ - return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type); -} - -#ifdef CONFIG_SMP -static int intca_gic_set_affinity(struct irq_data *data, - const struct cpumask *cpumask, - bool force) -{ - return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force); -} -#endif - -struct irq_chip intca_gic_irq_chip = { - .name = "INTCA-GIC", - .irq_mask = intca_gic_disable, - .irq_unmask = intca_gic_enable, - .irq_mask_ack = intca_gic_mask_ack, - .irq_eoi = intca_gic_eoi, - .irq_enable = intca_gic_enable, - .irq_disable = intca_gic_disable, - .irq_shutdown = intca_gic_disable, - .irq_set_type = intca_gic_set_type, - .irq_set_wake = sh73a0_set_wake, -#ifdef CONFIG_SMP - .irq_set_affinity = intca_gic_set_affinity, -#endif -}; - -static int to_intc_vect(int irq) -{ - unsigned int irq_pin = irq - gic_spi(1); - unsigned int offs; - - if (irq_pin < 16) - offs = 0x0200; - else - offs = 0x3000; - - return offs + (irq_pin << 5); -} - -static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id) -{ - generic_handle_irq(intcs_evt2irq(to_intc_vect(irq))); - return IRQ_HANDLED; -} - -static struct irqaction sh73a0_irq_pin_cascade[32]; - #define PINTER0_PHYS 0xe69000a0 #define PINTER1_PHYS 0xe69000a4 #define PINTER0_VIRT IOMEM(0xe69000a0) @@ -422,13 +320,11 @@ void __init sh73a0_init_irq(void) void __iomem *gic_dist_base = IOMEM(0xf0001000); void __iomem *gic_cpu_base = IOMEM(0xf0000100); void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); - int k, n; gic_init(0, 29, gic_dist_base, gic_cpu_base); gic_arch_extn.irq_set_wake = sh73a0_set_wake; register_intc_controller(&intcs_desc); - register_intc_controller(&intca_irq_pins_desc); register_intc_controller(&intc_pint0_desc); register_intc_controller(&intc_pint1_desc); @@ -438,19 +334,6 @@ void __init sh73a0_init_irq(void) sh73a0_intcs_cascade.dev_id = intevtsa; setup_irq(gic_spi(50), &sh73a0_intcs_cascade); - /* IRQ pins require special handling through INTCA and GIC */ - for (k = 0; k < 32; k++) { - sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade"; - sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux; - setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]); - - n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k))); - WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n); - irq_set_chip_and_handler_name(n, &intca_gic_irq_chip, - handle_level_irq, "level"); - set_irq_flags(n, IRQF_VALID); /* yuck */ - } - /* PINT pins are sanely tied to the GIC as SPI */ sh73a0_pint0_cascade.name = "PINT0 cascade"; sh73a0_pint0_cascade.handler = sh73a0_pint0_demux; diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 2257a915746d..638735f78e36 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -811,6 +812,127 @@ static struct platform_device ipmmu_device = { .num_resources = ARRAY_SIZE(ipmmu_resources), }; +struct renesas_intc_irqpin_config irqpin0_platform_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ +}; + +static struct resource irqpin0_resources[] = { + DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ + DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ + DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ + DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ + DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ + DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */ + DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */ + DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */ + DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */ + DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */ + DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */ + DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */ + DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */ +}; + +static struct platform_device irqpin0_device = { + .name = "renesas_intc_irqpin", + .id = 0, + .resource = irqpin0_resources, + .num_resources = ARRAY_SIZE(irqpin0_resources), + .dev = { + .platform_data = &irqpin0_platform_data, + }, +}; + +struct renesas_intc_irqpin_config irqpin1_platform_data = { + .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ + .control_parent = true, /* Disable spurious IRQ10 */ +}; + +static struct resource irqpin1_resources[] = { + DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ + DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ + DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ + DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ + DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ + DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */ + DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */ + DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */ + DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */ + DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */ + DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */ + DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */ + DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */ +}; + +static struct platform_device irqpin1_device = { + .name = "renesas_intc_irqpin", + .id = 1, + .resource = irqpin1_resources, + .num_resources = ARRAY_SIZE(irqpin1_resources), + .dev = { + .platform_data = &irqpin1_platform_data, + }, +}; + +struct renesas_intc_irqpin_config irqpin2_platform_data = { + .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ +}; + +static struct resource irqpin2_resources[] = { + DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ + DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */ + DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */ + DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */ + DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */ + DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */ + DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */ + DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */ + DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */ + DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */ + DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */ + DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */ + DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */ +}; + +static struct platform_device irqpin2_device = { + .name = "renesas_intc_irqpin", + .id = 2, + .resource = irqpin2_resources, + .num_resources = ARRAY_SIZE(irqpin2_resources), + .dev = { + .platform_data = &irqpin2_platform_data, + }, +}; + +struct renesas_intc_irqpin_config irqpin3_platform_data = { + .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ +}; + +static struct resource irqpin3_resources[] = { + DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */ + DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ + DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ + DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ + DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ + DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */ + DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */ + DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */ + DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */ + DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */ + DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */ + DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */ + DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */ +}; + +static struct platform_device irqpin3_device = { + .name = "renesas_intc_irqpin", + .id = 3, + .resource = irqpin3_resources, + .num_resources = ARRAY_SIZE(irqpin3_resources), + .dev = { + .platform_data = &irqpin3_platform_data, + }, +}; + static struct platform_device *sh73a0_devices_dt[] __initdata = { &scif0_device, &scif1_device, @@ -839,6 +961,10 @@ static struct platform_device *sh73a0_late_devices[] __initdata = { &dma0_device, &mpdma0_device, &pmu_device, + &irqpin0_device, + &irqpin1_device, + &irqpin2_device, + &irqpin3_device, }; #define SRCR2 IOMEM(0xe61580b0) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 709008e94124..6f15c03077a0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2733,9 +2733,9 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */ -#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5)) -#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5)) +/* External IRQ pins mapped at IRQPIN_BASE */ +#define EXT_IRQ16L(n) irq_pin(n) +#define EXT_IRQ16H(n) irq_pin(n) static struct pinmux_irq pinmux_irqs[] = { PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0), -- cgit v1.2.1 From 8e56e6d5bfad8d07befe1026e49ff0046ef0b147 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 12:01:18 +0900 Subject: ARM: shmobile: INTC External IRQ pin driver on r8a7779 Update the r8a7779 IRQ code to make use of the INTC External IRQ pin driver for external interrupt pins IRQ0 -> IRQ3. The r8a7779 SoC can like older SH SoCs configure to use the IRQ0 -> IRQ3 signals as individual interrupts or a combined IRL mode. Without this patch the r8a7779 SoC code does not fully support external IRQ pins in individual IRQ mode. The r8a7779 PFC code does not yet have gpio_to_irq() support so no need to update such code. At this point the DT reference implementations are not covered. In the future such code shall tie in the INTC External IRQ pin driver via DT, so this kind of verbose code is not needed for the long term DT case. Signed-off-by: Magnus Damm Tested-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/intc-r8a7779.c | 53 +++++++++++++++++++++++++++- 3 files changed, 54 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index f964accbce24..75d413c004b6 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -32,6 +32,7 @@ config ARCH_R8A7779 select SH_CLK_CPG select USB_ARCH_HAS_EHCI select USB_ARCH_HAS_OHCI + select RENESAS_INTC_IRQPIN config ARCH_EMEV2 bool "Emma Mobile EV2" diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 86fcdf9fde1b..03f73def2fc6 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -61,6 +61,7 @@ extern void r8a7740_pm_init(void); extern void r8a7779_init_delay(void); extern void r8a7779_init_irq(void); +extern void r8a7779_init_irq_extpin(int irlm); extern void r8a7779_init_irq_dt(void); extern void r8a7779_map_io(void); extern void r8a7779_earlytimer_init(void); diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c index f9cc4bc9c798..fb0363ca4635 100644 --- a/arch/arm/mach-shmobile/intc-r8a7779.c +++ b/arch/arm/mach-shmobile/intc-r8a7779.c @@ -19,13 +19,16 @@ */ #include #include +#include #include #include #include #include -#include +#include #include +#include #include +#include #include #include #include @@ -39,6 +42,54 @@ #define INT2NTSR0 IOMEM(0xfe700060) #define INT2NTSR1 IOMEM(0xfe700064) +struct renesas_intc_irqpin_config irqpin0_platform_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ + .sense_bitfield_width = 2, +}; + +static struct resource irqpin0_resources[] = { + DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ + DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ + DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ + DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ + DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ + DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ + DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ + DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ + DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ +}; + +static struct platform_device irqpin0_device = { + .name = "renesas_intc_irqpin", + .id = 0, + .resource = irqpin0_resources, + .num_resources = ARRAY_SIZE(irqpin0_resources), + .dev = { + .platform_data = &irqpin0_platform_data, + }, +}; + +void __init r8a7779_init_irq_extpin(int irlm) +{ + void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); + unsigned long tmp; + + if (icr0) { + tmp = ioread32(icr0); + if (irlm) + tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ + else + tmp &= ~(1 << 23); /* IRL mode - not supported */ + tmp |= (1 << 21); /* LVLMODE = 1 */ + iowrite32(tmp, icr0); + iounmap(icr0); + + if (irlm) + platform_device_register(&irqpin0_device); + } else + pr_warn("r8a7779: unable to setup external irq pin mode\n"); +} + static int r8a7779_set_wake(struct irq_data *data, unsigned int on) { return 0; /* always allow wakeup */ -- cgit v1.2.1 From 862d309883c69d67e1a2095e6f9e8ef35bf72dd6 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 20:58:44 +0900 Subject: irqchip: intc-irqpin: Whitespace fixes Remove whitespace damage and add newline between variables and code. Signed-off-by: Magnus Damm Reviewed-by: Thomas Gleixner Tested-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- drivers/irqchip/irq-renesas-intc-irqpin.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 1e5058a56517..4b5933fc0e3d 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -57,13 +57,13 @@ struct intc_irqpin_iomem { unsigned long (*read)(void __iomem *iomem); void (*write)(void __iomem *iomem, unsigned long data); int width; -}; +}; struct intc_irqpin_irq { int hw_irq; int irq; struct intc_irqpin_priv *p; -}; +}; struct intc_irqpin_priv { struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR]; @@ -99,6 +99,7 @@ static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p, int reg) { struct intc_irqpin_iomem *i = &p->iomem[reg]; + return i->read(i->iomem); } @@ -106,6 +107,7 @@ static inline void intc_irqpin_write(struct intc_irqpin_priv *p, int reg, unsigned long data) { struct intc_irqpin_iomem *i = &p->iomem[reg]; + i->write(i->iomem, data); } @@ -405,7 +407,7 @@ static int intc_irqpin_probe(struct platform_device *pdev) dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n", p->config.irq_base, k); } - + return 0; err3: -- cgit v1.2.1 From 33f958f2a71c44164698d1cae5463c0b85296a2c Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 20:58:54 +0900 Subject: irqchip: intc-irqpin: Cache mapped IRQ Cache IRQ in domain_irq variable instead of making use of irq_find_mapping(). While at it rename the irq variable to requested_irq. Signed-off-by: Magnus Damm Reviewed-by: Thomas Gleixner Tested-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- drivers/irqchip/irq-renesas-intc-irqpin.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 4b5933fc0e3d..0ac2bf683378 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -61,7 +61,8 @@ struct intc_irqpin_iomem { struct intc_irqpin_irq { int hw_irq; - int irq; + int requested_irq; + int domain_irq; struct intc_irqpin_priv *p; }; @@ -171,8 +172,7 @@ static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str) { dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", - str, i->irq, i->hw_irq, - irq_find_mapping(i->p->irq_domain, i->hw_irq)); + str, i->requested_irq, i->hw_irq, i->domain_irq); } static void intc_irqpin_irq_enable(struct irq_data *d) @@ -196,7 +196,7 @@ static void intc_irqpin_irq_disable(struct irq_data *d) static void intc_irqpin_irq_enable_force(struct irq_data *d) { struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); - int irq = p->irq[irqd_to_hwirq(d)].irq; + int irq = p->irq[irqd_to_hwirq(d)].requested_irq; intc_irqpin_irq_enable(d); irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq)); @@ -205,7 +205,7 @@ static void intc_irqpin_irq_enable_force(struct irq_data *d) static void intc_irqpin_irq_disable_force(struct irq_data *d) { struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); - int irq = p->irq[irqd_to_hwirq(d)].irq; + int irq = p->irq[irqd_to_hwirq(d)].requested_irq; irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq)); intc_irqpin_irq_disable(d); @@ -246,7 +246,7 @@ static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id) if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) { intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit); intc_irqpin_dbg(i, "demux2"); - generic_handle_irq(irq_find_mapping(p->irq_domain, i->hw_irq)); + generic_handle_irq(i->domain_irq); return IRQ_HANDLED; } return IRQ_NONE; @@ -257,6 +257,9 @@ static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, { struct intc_irqpin_priv *p = h->host_data; + p->irq[hw].domain_irq = virq; + p->irq[hw].hw_irq = hw; + intc_irqpin_dbg(&p->irq[hw], "map"); irq_set_chip_data(virq, h->host_data); irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); @@ -314,9 +317,8 @@ static int intc_irqpin_probe(struct platform_device *pdev) if (!irq) break; - p->irq[k].hw_irq = k; p->irq[k].p = p; - p->irq[k].irq = irq->start; + p->irq[k].requested_irq = irq->start; } p->number_of_irqs = k; @@ -389,7 +391,8 @@ static int intc_irqpin_probe(struct platform_device *pdev) /* request and set priority on interrupts one by one */ for (k = 0; k < p->number_of_irqs; k++) { - if (request_irq(p->irq[k].irq, intc_irqpin_irq_handler, + if (request_irq(p->irq[k].requested_irq, + intc_irqpin_irq_handler, 0, name, &p->irq[k])) { dev_err(&pdev->dev, "failed to request low IRQ\n"); ret = -ENOENT; @@ -402,17 +405,16 @@ static int intc_irqpin_probe(struct platform_device *pdev) /* warn in case of mismatch if irq base is specified */ if (p->config.irq_base) { - k = irq_find_mapping(p->irq_domain, 0); - if (p->config.irq_base != k) + if (p->config.irq_base != p->irq[0].domain_irq) dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n", - p->config.irq_base, k); + p->config.irq_base, p->irq[0].domain_irq); } return 0; err3: for (; k >= 0; k--) - free_irq(p->irq[k - 1].irq, &p->irq[k - 1]); + free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]); irq_domain_remove(p->irq_domain); err2: @@ -430,7 +432,7 @@ static int intc_irqpin_remove(struct platform_device *pdev) int k; for (k = 0; k < p->number_of_irqs; k++) - free_irq(p->irq[k].irq, &p->irq[k]); + free_irq(p->irq[k].requested_irq, &p->irq[k]); irq_domain_remove(p->irq_domain); -- cgit v1.2.1 From d1b6aecde4ab146d115abcaf3bb1940d8e980b5a Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 20:59:04 +0900 Subject: irqchip: intc-irqpin: Add force comments Add comments to describe the special case for "force" versions of enable and disable functions. Signed-off-by: Magnus Damm Reviewed-by: Thomas Gleixner Tested-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- drivers/irqchip/irq-renesas-intc-irqpin.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 0ac2bf683378..59c0cbccf212 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -199,6 +199,11 @@ static void intc_irqpin_irq_enable_force(struct irq_data *d) int irq = p->irq[irqd_to_hwirq(d)].requested_irq; intc_irqpin_irq_enable(d); + + /* enable interrupt through parent interrupt controller, + * assumes non-shared interrupt with 1:1 mapping + * needed for busted IRQs on some SoCs like sh73a0 + */ irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq)); } @@ -207,6 +212,10 @@ static void intc_irqpin_irq_disable_force(struct irq_data *d) struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); int irq = p->irq[irqd_to_hwirq(d)].requested_irq; + /* disable interrupt through parent interrupt controller, + * assumes non-shared interrupt with 1:1 mapping + * needed for busted IRQs on some SoCs like sh73a0 + */ irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq)); intc_irqpin_irq_disable(d); } -- cgit v1.2.1 From 08eba5ba4f321c4b1806ecad0e626904f89263a1 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 20:59:13 +0900 Subject: irqchip: intc-irqpin: Make use of devm functions Use devm_kzalloc(), devm_ioremap_nocache() and devm_request_irq() to simplify error handling. Signed-off-by: Magnus Damm Reviewed-by: Thomas Gleixner Tested-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- drivers/irqchip/irq-renesas-intc-irqpin.c | 41 ++++++++++--------------------- 1 file changed, 13 insertions(+), 28 deletions(-) diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 59c0cbccf212..21f46027f39a 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -294,7 +294,7 @@ static int intc_irqpin_probe(struct platform_device *pdev) int ret; int k; - p = kzalloc(sizeof(*p), GFP_KERNEL); + p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); if (!p) { dev_err(&pdev->dev, "failed to allocate driver data\n"); ret = -ENOMEM; @@ -316,7 +316,7 @@ static int intc_irqpin_probe(struct platform_device *pdev) if (!io[k]) { dev_err(&pdev->dev, "not enough IOMEM resources\n"); ret = -EINVAL; - goto err1; + goto err0; } } @@ -334,7 +334,7 @@ static int intc_irqpin_probe(struct platform_device *pdev) if (p->number_of_irqs < 1) { dev_err(&pdev->dev, "not enough IRQ resources\n"); ret = -EINVAL; - goto err1; + goto err0; } /* ioremap IOMEM and setup read/write callbacks */ @@ -355,14 +355,15 @@ static int intc_irqpin_probe(struct platform_device *pdev) default: dev_err(&pdev->dev, "IOMEM size mismatch\n"); ret = -EINVAL; - goto err2; + goto err0; } - i->iomem = ioremap_nocache(io[k]->start, resource_size(io[k])); + i->iomem = devm_ioremap_nocache(&pdev->dev, io[k]->start, + resource_size(io[k])); if (!i->iomem) { dev_err(&pdev->dev, "failed to remap IOMEM\n"); ret = -ENXIO; - goto err2; + goto err0; } } @@ -395,17 +396,17 @@ static int intc_irqpin_probe(struct platform_device *pdev) if (!p->irq_domain) { ret = -ENXIO; dev_err(&pdev->dev, "cannot initialize irq domain\n"); - goto err2; + goto err0; } /* request and set priority on interrupts one by one */ for (k = 0; k < p->number_of_irqs; k++) { - if (request_irq(p->irq[k].requested_irq, - intc_irqpin_irq_handler, - 0, name, &p->irq[k])) { + if (devm_request_irq(&pdev->dev, p->irq[k].requested_irq, + intc_irqpin_irq_handler, + 0, name, &p->irq[k])) { dev_err(&pdev->dev, "failed to request low IRQ\n"); ret = -ENOENT; - goto err3; + goto err1; } intc_irqpin_mask_unmask_prio(p, k, 0); } @@ -421,16 +422,8 @@ static int intc_irqpin_probe(struct platform_device *pdev) return 0; -err3: - for (; k >= 0; k--) - free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]); - - irq_domain_remove(p->irq_domain); -err2: - for (k = 0; k < INTC_IRQPIN_REG_NR; k++) - iounmap(p->iomem[k].iomem); err1: - kfree(p); + irq_domain_remove(p->irq_domain); err0: return ret; } @@ -438,17 +431,9 @@ err0: static int intc_irqpin_remove(struct platform_device *pdev) { struct intc_irqpin_priv *p = platform_get_drvdata(pdev); - int k; - - for (k = 0; k < p->number_of_irqs; k++) - free_irq(p->irq[k].requested_irq, &p->irq[k]); irq_domain_remove(p->irq_domain); - for (k = 0; k < INTC_IRQPIN_REG_NR; k++) - iounmap(p->iomem[k].iomem); - - kfree(p); return 0; } -- cgit v1.2.1 From 0ca8712285e9e762ce4f5faf9f803b52e48c6837 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Feb 2013 20:59:23 +0900 Subject: irqchip: intc-irqpin: GPL header for platform data Add GPL header to platform data include file. Signed-off-by: Magnus Damm Reviewed-by: Thomas Gleixner Tested-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- include/linux/platform_data/irq-renesas-intc-irqpin.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/linux/platform_data/irq-renesas-intc-irqpin.h b/include/linux/platform_data/irq-renesas-intc-irqpin.h index 00ccac34dac8..e4cb911066a6 100644 --- a/include/linux/platform_data/irq-renesas-intc-irqpin.h +++ b/include/linux/platform_data/irq-renesas-intc-irqpin.h @@ -1,3 +1,22 @@ +/* + * Renesas INTC External IRQ Pin Driver + * + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + #ifndef __IRQ_RENESAS_INTC_IRQPIN_H__ #define __IRQ_RENESAS_INTC_IRQPIN_H__ -- cgit v1.2.1 From fbc83b7f59dd8ed1154286b6de00b6d03c24a3c4 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 27 Feb 2013 17:15:01 +0900 Subject: irqchip: Renesas IRQC driver This patch adds a driver for external IRQ pins connected to the IRQC hardware block on recent SoCs from Renesas. The IRQC hardware block is used together with more recent ARM based SoCs using the GIC. As usual the GIC requires external IRQ trigger setup somewhere else which in this particular case happens to be IRQC. This driver implements the glue code needed to configure IRQ trigger and also handle mask/unmask and demux of external IRQ pins hooked up from the IRQC to the GIC. Tested on r8a73a4 but is designed to work with a wide range of SoCs. The driver requires one GIC SPI per external IRQ pin to operate. Each driver instance will handle up to 32 external IRQ pins. The SoCs using this driver are currently mainly used together with regular platform devices so this driver allows configuration via platform data to support things like static interrupt base address. DT support will be added incrementally in the not so distant future. Signed-off-by: Magnus Damm Tested-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- drivers/irqchip/Kconfig | 4 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-irqc.c | 298 +++++++++++++++++++++++++ include/linux/platform_data/irq-renesas-irqc.h | 27 +++ 4 files changed, 330 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-irqc.c create mode 100644 include/linux/platform_data/irq-renesas-irqc.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 0f5f1c3825bc..4a33351c25dc 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -29,6 +29,10 @@ config RENESAS_INTC_IRQPIN bool select IRQ_DOMAIN +config RENESAS_IRQC + bool + select IRQ_DOMAIN + config VERSATILE_FPGA_IRQ bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 1aaa4073ab60..e41ceb9bec22 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o obj-$(CONFIG_ARM_GIC) += irq-gic.o obj-$(CONFIG_ARM_VIC) += irq-vic.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o +obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c new file mode 100644 index 000000000000..95d69bfac982 --- /dev/null +++ b/drivers/irqchip/irq-renesas-irqc.c @@ -0,0 +1,298 @@ +/* + * Renesas IRQC Driver + * + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */ + +#define IRQC_REQ_STS 0x00 +#define IRQC_EN_STS 0x04 +#define IRQC_EN_SET 0x08 +#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10)) +#define DETECT_STATUS 0x100 +#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04)) + +struct irqc_irq { + int hw_irq; + int requested_irq; + int domain_irq; + struct irqc_priv *p; +}; + +struct irqc_priv { + void __iomem *iomem; + void __iomem *cpu_int_base; + struct irqc_irq irq[IRQC_IRQ_MAX]; + struct renesas_irqc_config config; + unsigned int number_of_irqs; + struct platform_device *pdev; + struct irq_chip irq_chip; + struct irq_domain *irq_domain; +}; + +static void irqc_dbg(struct irqc_irq *i, char *str) +{ + dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", + str, i->requested_irq, i->hw_irq, i->domain_irq); +} + +static void irqc_irq_enable(struct irq_data *d) +{ + struct irqc_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + irqc_dbg(&p->irq[hw_irq], "enable"); + iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET); +} + +static void irqc_irq_disable(struct irq_data *d) +{ + struct irqc_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + irqc_dbg(&p->irq[hw_irq], "disable"); + iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS); +} + +#define INTC_IRQ_SENSE_VALID 0x10 +#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID) + +static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = { + [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x01), + [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x02), + [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x04), /* Synchronous */ + [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x08), /* Synchronous */ + [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x0c), /* Synchronous */ +}; + +static int irqc_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct irqc_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK]; + unsigned long tmp; + + irqc_dbg(&p->irq[hw_irq], "sense"); + + if (!(value & INTC_IRQ_SENSE_VALID)) + return -EINVAL; + + tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); + tmp &= ~0x3f; + tmp |= value ^ INTC_IRQ_SENSE_VALID; + iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq)); + return 0; +} + +static irqreturn_t irqc_irq_handler(int irq, void *dev_id) +{ + struct irqc_irq *i = dev_id; + struct irqc_priv *p = i->p; + unsigned long bit = BIT(i->hw_irq); + + irqc_dbg(i, "demux1"); + + if (ioread32(p->iomem + DETECT_STATUS) & bit) { + iowrite32(bit, p->iomem + DETECT_STATUS); + irqc_dbg(i, "demux2"); + generic_handle_irq(i->domain_irq); + return IRQ_HANDLED; + } + return IRQ_NONE; +} + +static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct irqc_priv *p = h->host_data; + + p->irq[hw].domain_irq = virq; + p->irq[hw].hw_irq = hw; + + irqc_dbg(&p->irq[hw], "map"); + irq_set_chip_data(virq, h->host_data); + irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); + set_irq_flags(virq, IRQF_VALID); /* kill me now */ + return 0; +} + +static struct irq_domain_ops irqc_irq_domain_ops = { + .map = irqc_irq_domain_map, +}; + +static int irqc_probe(struct platform_device *pdev) +{ + struct renesas_irqc_config *pdata = pdev->dev.platform_data; + struct irqc_priv *p; + struct resource *io; + struct resource *irq; + struct irq_chip *irq_chip; + const char *name = dev_name(&pdev->dev); + int ret; + int k; + + p = kzalloc(sizeof(*p), GFP_KERNEL); + if (!p) { + dev_err(&pdev->dev, "failed to allocate driver data\n"); + ret = -ENOMEM; + goto err0; + } + + /* deal with driver instance configuration */ + if (pdata) + memcpy(&p->config, pdata, sizeof(*pdata)); + + p->pdev = pdev; + platform_set_drvdata(pdev, p); + + /* get hold of manadatory IOMEM */ + io = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!io) { + dev_err(&pdev->dev, "not enough IOMEM resources\n"); + ret = -EINVAL; + goto err1; + } + + /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */ + for (k = 0; k < IRQC_IRQ_MAX; k++) { + irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); + if (!irq) + break; + + p->irq[k].p = p; + p->irq[k].requested_irq = irq->start; + } + + p->number_of_irqs = k; + if (p->number_of_irqs < 1) { + dev_err(&pdev->dev, "not enough IRQ resources\n"); + ret = -EINVAL; + goto err1; + } + + /* ioremap IOMEM and setup read/write callbacks */ + p->iomem = ioremap_nocache(io->start, resource_size(io)); + if (!p->iomem) { + dev_err(&pdev->dev, "failed to remap IOMEM\n"); + ret = -ENXIO; + goto err2; + } + + p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */ + + irq_chip = &p->irq_chip; + irq_chip->name = name; + irq_chip->irq_mask = irqc_irq_disable; + irq_chip->irq_unmask = irqc_irq_enable; + irq_chip->irq_enable = irqc_irq_enable; + irq_chip->irq_disable = irqc_irq_disable; + irq_chip->irq_set_type = irqc_irq_set_type; + irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; + + p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, + p->number_of_irqs, + p->config.irq_base, + &irqc_irq_domain_ops, p); + if (!p->irq_domain) { + ret = -ENXIO; + dev_err(&pdev->dev, "cannot initialize irq domain\n"); + goto err2; + } + + /* request interrupts one by one */ + for (k = 0; k < p->number_of_irqs; k++) { + if (request_irq(p->irq[k].requested_irq, irqc_irq_handler, + 0, name, &p->irq[k])) { + dev_err(&pdev->dev, "failed to request IRQ\n"); + ret = -ENOENT; + goto err3; + } + } + + dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); + + /* warn in case of mismatch if irq base is specified */ + if (p->config.irq_base) { + if (p->config.irq_base != p->irq[0].domain_irq) + dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n", + p->config.irq_base, p->irq[0].domain_irq); + } + + return 0; +err3: + for (; k >= 0; k--) + free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]); + + irq_domain_remove(p->irq_domain); +err2: + iounmap(p->iomem); +err1: + kfree(p); +err0: + return ret; +} + +static int irqc_remove(struct platform_device *pdev) +{ + struct irqc_priv *p = platform_get_drvdata(pdev); + int k; + + for (k = 0; k < p->number_of_irqs; k++) + free_irq(p->irq[k].requested_irq, &p->irq[k]); + + irq_domain_remove(p->irq_domain); + iounmap(p->iomem); + kfree(p); + return 0; +} + +static struct platform_driver irqc_device_driver = { + .probe = irqc_probe, + .remove = irqc_remove, + .driver = { + .name = "renesas_irqc", + } +}; + +static int __init irqc_init(void) +{ + return platform_driver_register(&irqc_device_driver); +} +postcore_initcall(irqc_init); + +static void __exit irqc_exit(void) +{ + platform_driver_unregister(&irqc_device_driver); +} +module_exit(irqc_exit); + +MODULE_AUTHOR("Magnus Damm"); +MODULE_DESCRIPTION("Renesas IRQC Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/platform_data/irq-renesas-irqc.h b/include/linux/platform_data/irq-renesas-irqc.h new file mode 100644 index 000000000000..3ae17b3e00ed --- /dev/null +++ b/include/linux/platform_data/irq-renesas-irqc.h @@ -0,0 +1,27 @@ +/* + * Renesas IRQC Driver + * + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __IRQ_RENESAS_IRQC_H__ +#define __IRQ_RENESAS_IRQC_H__ + +struct renesas_irqc_config { + unsigned int irq_base; +}; + +#endif /* __IRQ_RENESAS_IRQC_H__ */ -- cgit v1.2.1 From 1461f8b62ffac3baaa955f74d4fe4a6166bfb4b3 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 6 Mar 2013 15:08:31 +0900 Subject: ARM: shmobile: Make sh73a0 INTC irqpin platform data static The platform data for the INTC irq pin driver seems to be global symbols, make it static to allow multi-soc build. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-sh73a0.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 638735f78e36..e8cd93a5c550 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -812,7 +812,7 @@ static struct platform_device ipmmu_device = { .num_resources = ARRAY_SIZE(ipmmu_resources), }; -struct renesas_intc_irqpin_config irqpin0_platform_data = { +static struct renesas_intc_irqpin_config irqpin0_platform_data = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ }; @@ -842,7 +842,7 @@ static struct platform_device irqpin0_device = { }, }; -struct renesas_intc_irqpin_config irqpin1_platform_data = { +static struct renesas_intc_irqpin_config irqpin1_platform_data = { .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ .control_parent = true, /* Disable spurious IRQ10 */ }; @@ -873,7 +873,7 @@ static struct platform_device irqpin1_device = { }, }; -struct renesas_intc_irqpin_config irqpin2_platform_data = { +static struct renesas_intc_irqpin_config irqpin2_platform_data = { .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ }; @@ -903,7 +903,7 @@ static struct platform_device irqpin2_device = { }, }; -struct renesas_intc_irqpin_config irqpin3_platform_data = { +static struct renesas_intc_irqpin_config irqpin3_platform_data = { .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ }; -- cgit v1.2.1 From 7c9e3c7acd107b967495c44b984f855897caf518 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 6 Mar 2013 15:10:06 +0900 Subject: ARM: shmobile: Make r8a7779 INTC irqpin platform data static The platform data for the INTC irq pin driver seems to be global symbols, make it static to allow multi-soc build. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/intc-r8a7779.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c index fb0363ca4635..b86dc8908724 100644 --- a/arch/arm/mach-shmobile/intc-r8a7779.c +++ b/arch/arm/mach-shmobile/intc-r8a7779.c @@ -42,7 +42,7 @@ #define INT2NTSR0 IOMEM(0xfe700060) #define INT2NTSR1 IOMEM(0xfe700064) -struct renesas_intc_irqpin_config irqpin0_platform_data = { +static struct renesas_intc_irqpin_config irqpin0_platform_data = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ .sense_bitfield_width = 2, }; -- cgit v1.2.1 From 9d833bbe49953a9a07f9ebd7a9ad170c308bd692 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 6 Mar 2013 15:16:08 +0900 Subject: irqchip: intc-irqpin: Initial DT support Add initial DT support to the INTC External IRQ Pin driver. At this point only hardware with 4-bit wide sense registers is supported via DT. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- drivers/irqchip/irq-renesas-intc-irqpin.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 21f46027f39a..fd5dabc2235d 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -278,6 +278,7 @@ static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, static struct irq_domain_ops intc_irqpin_irq_domain_ops = { .map = intc_irqpin_irq_domain_map, + .xlate = irq_domain_xlate_twocell, }; static int intc_irqpin_probe(struct platform_device *pdev) @@ -437,11 +438,19 @@ static int intc_irqpin_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id intc_irqpin_dt_ids[] = { + { .compatible = "renesas,intc-irqpin", }, + {}, +}; +MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids); + static struct platform_driver intc_irqpin_device_driver = { .probe = intc_irqpin_probe, .remove = intc_irqpin_remove, .driver = { .name = "renesas_intc_irqpin", + .of_match_table = intc_irqpin_dt_ids, + .owner = THIS_MODULE, } }; -- cgit v1.2.1 From 3b8dfa7c2f8af7613dae28ac0f3419bf75ead5d0 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 6 Mar 2013 15:23:39 +0900 Subject: irqchip: irqc: Add DT support Add DT support to the IRQC External IRQ Pin driver. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- drivers/irqchip/irq-renesas-irqc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c index 95d69bfac982..927bff373aac 100644 --- a/drivers/irqchip/irq-renesas-irqc.c +++ b/drivers/irqchip/irq-renesas-irqc.c @@ -145,6 +145,7 @@ static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq, static struct irq_domain_ops irqc_irq_domain_ops = { .map = irqc_irq_domain_map, + .xlate = irq_domain_xlate_twocell, }; static int irqc_probe(struct platform_device *pdev) @@ -273,11 +274,19 @@ static int irqc_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id irqc_dt_ids[] = { + { .compatible = "renesas,irqc", }, + {}, +}; +MODULE_DEVICE_TABLE(of, irqc_dt_ids); + static struct platform_driver irqc_device_driver = { .probe = irqc_probe, .remove = irqc_remove, .driver = { .name = "renesas_irqc", + .of_match_table = irqc_dt_ids, + .owner = THIS_MODULE, } }; -- cgit v1.2.1 From 427cc720277c140e6a63a03237f9bf37d8076ac3 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Wed, 27 Mar 2013 14:54:03 +0100 Subject: irqchip: intc-irqpin: Add support for shared interrupt lines On some hardware we don't have a 1-1 mapping from the external interrupts coming from INTC to the GIC SPI pins. We can however share lines to demux incoming IRQs on these SoCs. This patch enables the intc_irqpin driver to detect requests for shared interrupt lines and demuxes them properly by querying the INTC INTREQx0A registers. If you need multiple shared intc_irqpin device instances, be sure to mask out all interrupts on the INTC that share the one line before you start to register them. Else you run into IRQ floods that would be caused by interrupts for which no handler has been set up yet when the first intc_irqpin device is registered. Signed-off-by: Bastian Hecht Acked-by: Magnus Damm Signed-off-by: Simon Horman --- drivers/irqchip/irq-renesas-intc-irqpin.c | 90 ++++++++++++++++++++++++++++--- 1 file changed, 83 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index fd5dabc2235d..5a68e5accec1 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -74,6 +74,8 @@ struct intc_irqpin_priv { struct platform_device *pdev; struct irq_chip irq_chip; struct irq_domain *irq_domain; + bool shared_irqs; + u8 shared_irq_mask; }; static unsigned long intc_irqpin_read32(void __iomem *iomem) @@ -193,6 +195,28 @@ static void intc_irqpin_irq_disable(struct irq_data *d) intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); } +static void intc_irqpin_shared_irq_enable(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + intc_irqpin_dbg(&p->irq[hw_irq], "shared enable"); + intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); + + p->shared_irq_mask &= ~BIT(hw_irq); +} + +static void intc_irqpin_shared_irq_disable(struct irq_data *d) +{ + struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); + int hw_irq = irqd_to_hwirq(d); + + intc_irqpin_dbg(&p->irq[hw_irq], "shared disable"); + intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); + + p->shared_irq_mask |= BIT(hw_irq); +} + static void intc_irqpin_irq_enable_force(struct irq_data *d) { struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); @@ -261,6 +285,25 @@ static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id) return IRQ_NONE; } +static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id) +{ + struct intc_irqpin_priv *p = dev_id; + unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE); + irqreturn_t status = IRQ_NONE; + int k; + + for (k = 0; k < 8; k++) { + if (reg_source & BIT(7 - k)) { + if (BIT(k) & p->shared_irq_mask) + continue; + + status |= intc_irqpin_irq_handler(irq, &p->irq[k]); + } + } + + return status; +} + static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { @@ -292,6 +335,7 @@ static int intc_irqpin_probe(struct platform_device *pdev) void (*enable_fn)(struct irq_data *d); void (*disable_fn)(struct irq_data *d); const char *name = dev_name(&pdev->dev); + int ref_irq; int ret; int k; @@ -372,13 +416,29 @@ static int intc_irqpin_probe(struct platform_device *pdev) for (k = 0; k < p->number_of_irqs; k++) intc_irqpin_mask_unmask_prio(p, k, 1); + /* clear all pending interrupts */ + intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0); + + /* scan for shared interrupt lines */ + ref_irq = p->irq[0].requested_irq; + p->shared_irqs = true; + for (k = 1; k < p->number_of_irqs; k++) { + if (ref_irq != p->irq[k].requested_irq) { + p->shared_irqs = false; + break; + } + } + /* use more severe masking method if requested */ if (p->config.control_parent) { enable_fn = intc_irqpin_irq_enable_force; disable_fn = intc_irqpin_irq_disable_force; - } else { + } else if (!p->shared_irqs) { enable_fn = intc_irqpin_irq_enable; disable_fn = intc_irqpin_irq_disable; + } else { + enable_fn = intc_irqpin_shared_irq_enable; + disable_fn = intc_irqpin_shared_irq_disable; } irq_chip = &p->irq_chip; @@ -400,18 +460,34 @@ static int intc_irqpin_probe(struct platform_device *pdev) goto err0; } - /* request and set priority on interrupts one by one */ - for (k = 0; k < p->number_of_irqs; k++) { - if (devm_request_irq(&pdev->dev, p->irq[k].requested_irq, - intc_irqpin_irq_handler, - 0, name, &p->irq[k])) { + if (p->shared_irqs) { + /* request one shared interrupt */ + if (devm_request_irq(&pdev->dev, p->irq[0].requested_irq, + intc_irqpin_shared_irq_handler, + IRQF_SHARED, name, p)) { dev_err(&pdev->dev, "failed to request low IRQ\n"); ret = -ENOENT; goto err1; } - intc_irqpin_mask_unmask_prio(p, k, 0); + } else { + /* request interrupts one by one */ + for (k = 0; k < p->number_of_irqs; k++) { + if (devm_request_irq(&pdev->dev, + p->irq[k].requested_irq, + intc_irqpin_irq_handler, + 0, name, &p->irq[k])) { + dev_err(&pdev->dev, + "failed to request low IRQ\n"); + ret = -ENOENT; + goto err1; + } + } } + /* unmask all interrupts on prio level */ + for (k = 0; k < p->number_of_irqs; k++) + intc_irqpin_mask_unmask_prio(p, k, 0); + dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); /* warn in case of mismatch if irq base is specified */ -- cgit v1.2.1 From eccf0607e450f5c6ca2af5d826d9308e8cdb6848 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 10:34:24 +0900 Subject: ARM: shmobile: Initial r8a73a4 SoC support V3 V3 of initial support for the r8a73a4 SoC including: - Single Cortex-A15 CPU Core - GIC - Architecture timer No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 55 ++++++++++++++++ arch/arm/mach-shmobile/Kconfig | 7 +++ arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/clock-r8a73a4.c | 91 +++++++++++++++++++++++++++ arch/arm/mach-shmobile/include/mach/r8a73a4.h | 7 +++ arch/arm/mach-shmobile/setup-r8a73a4.c | 50 +++++++++++++++ 6 files changed, 211 insertions(+) create mode 100644 arch/arm/boot/dts/r8a73a4.dtsi create mode 100644 arch/arm/mach-shmobile/clock-r8a73a4.c create mode 100644 arch/arm/mach-shmobile/include/mach/r8a73a4.h create mode 100644 arch/arm/mach-shmobile/setup-r8a73a4.c diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi new file mode 100644 index 000000000000..72c58c172e9d --- /dev/null +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -0,0 +1,55 @@ +/* + * Device Tree Source for the r8a73a4 SoC + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "renesas,r8a73a4"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xf1001000 0x1000>, + <0xf1002000 0x1000>, + <0xf1004000 0x2000>, + <0xf1006000 0x2000>; + interrupts = <1 9 0xf04>; + + gic-cpuif@4 { + compatible = "arm,gic-cpuif"; + cpuif-id = <4>; + cpu = <&cpu0>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; +}; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 75d413c004b6..663d27b39880 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -18,6 +18,13 @@ config ARCH_SH73A0 select SH_CLK_CPG select RENESAS_INTC_IRQPIN +config ARCH_R8A73A4 + bool "R-Mobile APE6 (R8A73A40)" + select ARM_GIC + select CPU_V7 + select ARM_ARCH_TIMER + select SH_CLK_CPG + config ARCH_R8A7740 bool "R-Mobile A1 (R8A77400)" select ARCH_WANT_OPTIONAL_GPIOLIB diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index b646ff4d742a..c5a43ef7cebf 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -8,6 +8,7 @@ obj-y := timer.o console.o clock.o # CPU objects obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o +obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c new file mode 100644 index 000000000000..15d479dbb132 --- /dev/null +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -0,0 +1,91 @@ +/* + * r8a73a4 clock framework support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include + +#define CPG_BASE 0xe6150000 +#define CPG_LEN 0x270 + +#define MPCKCR 0xe6150080 + +static struct clk_mapping cpg_mapping = { + .phys = CPG_BASE, + .len = CPG_LEN, +}; + +static struct clk extalr_clk = { + .rate = 32768, + .mapping = &cpg_mapping, +}; + +static struct clk extal1_clk = { + .rate = 26000000, + .mapping = &cpg_mapping, +}; + +static struct clk extal2_clk = { + .rate = 48000000, + .mapping = &cpg_mapping, +}; + +static struct clk *main_clks[] = { + &extalr_clk, + &extal1_clk, + &extal2_clk, +}; + +enum { MSTP_NR }; +static struct clk mstp_clks[MSTP_NR] = { +}; + +static struct clk_lookup lookups[] = { +}; + +void __init r8a73a4_clock_init(void) +{ + void __iomem *cpg_base, *reg; + int k, ret = 0; + + /* fix MPCLK to EXTAL2 for now. + * this is needed until more detailed clock topology is supported + */ + cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN); + BUG_ON(!cpg_base); + reg = cpg_base + (MPCKCR - CPG_BASE); + iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */ + iounmap(cpg_base); + + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + + if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + if (!ret) + shmobile_clk_init(); + else + panic("failed to setup r8a73a4 clocks\n"); +} diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h new file mode 100644 index 000000000000..6db3495479d8 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h @@ -0,0 +1,7 @@ +#ifndef __ASM_R8A73A4_H__ +#define __ASM_R8A73A4_H__ + +void r8a73a4_add_standard_devices(void); +void r8a73a4_clock_init(void); + +#endif /* __ASM_R8A73A4_H__ */ diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c new file mode 100644 index 000000000000..69156bce76f7 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -0,0 +1,50 @@ +/* + * r8a73a4 processor support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include + +void __init r8a73a4_add_standard_devices(void) +{ +} + +#ifdef CONFIG_USE_OF +void __init r8a73a4_add_standard_devices_dt(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char *r8a73a4_boards_compat_dt[] __initdata = { + "renesas,r8a73a4", + NULL, +}; + +DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") + .init_irq = irqchip_init, + .init_machine = r8a73a4_add_standard_devices_dt, + .init_time = shmobile_timer_init, + .dt_compat = r8a73a4_boards_compat_dt, +MACHINE_END +#endif /* CONFIG_USE_OF */ -- cgit v1.2.1 From e481a528901d0cd18b5b5fcbdc55207ea3b6ef68 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 10:34:33 +0900 Subject: ARM: shmobile: r8a73a4 SCIF support V3 V3 of SCIF serial port support for the r8a73a4 SoC. This is done by adding platform devices for SCIFA0 -> SCIFA1 as well as SCIFB0 -> SCIFB3 together with clock bindings. DT device description is excluded at this point since such bindings are still under development. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a73a4.c | 15 +++++++++++- arch/arm/mach-shmobile/setup-r8a73a4.c | 43 ++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 15d479dbb132..037713bdff3f 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -28,6 +28,7 @@ #define CPG_LEN 0x270 #define MPCKCR 0xe6150080 +#define SMSTPCR2 0xe6150138 static struct clk_mapping cpg_mapping = { .phys = CPG_BASE, @@ -55,11 +56,23 @@ static struct clk *main_clks[] = { &extal2_clk, }; -enum { MSTP_NR }; +enum { MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { + [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ + [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ + [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ + [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */ }; static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), }; void __init r8a73a4_clock_init(void) diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index 69156bce76f7..746a3dc4474d 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -21,13 +21,56 @@ #include #include #include +#include #include #include #include #include +#define SCIF_COMMON(scif_type, baseaddr, irq) \ + .type = scif_type, \ + .mapbase = baseaddr, \ + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ + .scbrr_algo_id = SCBRR_ALGO_4, \ + .irqs = SCIx_IRQ_MUXED(irq) + +#define SCIFA_DATA(index, baseaddr, irq) \ +[index] = { \ + SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ +} + +#define SCIFB_DATA(index, baseaddr, irq) \ +[index] = { \ + SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ + .scscr = SCSCR_RE | SCSCR_TE, \ +} + +enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 }; + +static const struct plat_sci_port scif[] = { + SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ + SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ + SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */ + SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ + SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ + SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */ +}; + +static inline void r8a73a4_register_scif(int idx) +{ + platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], + sizeof(struct plat_sci_port)); +} + void __init r8a73a4_add_standard_devices(void) { + r8a73a4_register_scif(SCIFA0); + r8a73a4_register_scif(SCIFA1); + r8a73a4_register_scif(SCIFB0); + r8a73a4_register_scif(SCIFB1); + r8a73a4_register_scif(SCIFB2); + r8a73a4_register_scif(SCIFB3); } #ifdef CONFIG_USE_OF -- cgit v1.2.1 From 984ca295010ad0113b986a404931566f9b1791d4 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 10:34:42 +0900 Subject: ARM: shmobile: r8a73a4 IRQC support V2 Add IRQC interrupt controller support to r8a73a4 by hooking up two IRQC instances to handle 58 external IRQ signals. There IRQC controllers are tied to SPIs of the GIC. On r8a73a4 exact IRQ pin routing is handled by the PFC which is excluded from this patch. Both platform devices and DT devices are added in this patch. The platform device versions are used to provide a static interrupt map configuration for board code written in C. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 32 +++++++++++++ arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/setup-r8a73a4.c | 84 ++++++++++++++++++++++++++++++++++ 3 files changed, 117 insertions(+) diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 72c58c172e9d..4c68ba15727c 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -52,4 +52,36 @@ <1 11 0xf08>, <1 10 0xf08>; }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe61c0000 0x200>; + interrupt-parent = <&gic>; + interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>, + <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>, + <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>, + <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>, + <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>, + <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>, + <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>, + <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>; + }; + + irqc1: interrupt-controller@e61c0200 { + compatible = "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe61c0200 0x200>; + interrupt-parent = <&gic>; + interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>, + <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>, + <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>, + <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>, + <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>, + <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>, + <0 56 4>, <0 57 4>; + }; + }; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 663d27b39880..17a59cde826e 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -24,6 +24,7 @@ config ARCH_R8A73A4 select CPU_V7 select ARM_ARCH_TIMER select SH_CLK_CPG + select RENESAS_IRQC config ARCH_R8A7740 bool "R-Mobile A1 (R8A77400)" diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index 746a3dc4474d..da5ae1611518 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -63,6 +64,87 @@ static inline void r8a73a4_register_scif(int idx) sizeof(struct plat_sci_port)); } +static const struct renesas_irqc_config irqc0_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ +}; + +static const struct resource irqc0_resources[] = { + DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ + DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ + DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ + DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ + DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ + DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */ + DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */ + DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */ + DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */ + DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */ + DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */ + DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */ + DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */ + DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */ + DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */ + DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */ + DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */ + DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */ + DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */ + DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */ + DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */ + DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */ + DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */ + DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */ + DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */ + DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */ + DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */ + DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */ + DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */ + DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */ + DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */ + DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */ + DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */ +}; + +static const struct renesas_irqc_config irqc1_data = { + .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */ +}; + +static const struct resource irqc1_resources[] = { + DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */ + DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */ + DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */ + DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */ + DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */ + DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */ + DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */ + DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */ + DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */ + DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */ + DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */ + DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */ + DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */ + DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */ + DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */ + DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */ + DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */ + DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */ + DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */ + DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */ + DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */ + DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */ + DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */ + DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */ + DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */ + DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */ + DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */ +}; + +#define r8a73a4_register_irqc(idx) \ + platform_device_register_resndata(&platform_bus, "renesas_irqc", \ + idx, irqc##idx##_resources, \ + ARRAY_SIZE(irqc##idx##_resources), \ + &irqc##idx##_data, \ + sizeof(struct renesas_irqc_config)) + void __init r8a73a4_add_standard_devices(void) { r8a73a4_register_scif(SCIFA0); @@ -71,6 +153,8 @@ void __init r8a73a4_add_standard_devices(void) r8a73a4_register_scif(SCIFB1); r8a73a4_register_scif(SCIFB2); r8a73a4_register_scif(SCIFB3); + r8a73a4_register_irqc(0); + r8a73a4_register_irqc(1); } #ifdef CONFIG_USE_OF -- cgit v1.2.1 From d313d068d4b5801ea9c0c66bed66f37c64ad6807 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 26 Mar 2013 10:34:52 +0900 Subject: ARM: shmobile: r8a73a4 PFC support Add a platform device for the r8a73a4 PFC. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/include/mach/r8a73a4.h | 1 + arch/arm/mach-shmobile/setup-r8a73a4.c | 10 ++++++++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 17a59cde826e..0e4a820bcbe8 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -20,6 +20,7 @@ config ARCH_SH73A0 config ARCH_R8A73A4 bool "R-Mobile APE6 (R8A73A40)" + select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_GIC select CPU_V7 select ARM_ARCH_TIMER diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h index 6db3495479d8..f043103e32c9 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h @@ -3,5 +3,6 @@ void r8a73a4_add_standard_devices(void); void r8a73a4_clock_init(void); +void r8a73a4_pinmux_init(void); #endif /* __ASM_R8A73A4_H__ */ diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index da5ae1611518..c2d86f30cde4 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -28,6 +28,16 @@ #include #include +static const struct resource pfc_resources[] = { + DEFINE_RES_MEM(0xe6050000, 0x9000), +}; + +void __init r8a73a4_pinmux_init(void) +{ + platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources, + ARRAY_SIZE(pfc_resources)); +} + #define SCIF_COMMON(scif_type, baseaddr, irq) \ .type = scif_type, \ .mapbase = baseaddr, \ -- cgit v1.2.1 From 7653c318b73d8553d4c13bb7e371878ddc19f80d Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 28 Feb 2013 13:21:58 +0100 Subject: ARM: shmobile: sh73a0: wait for completion when kicking the clock To reconfigure clocks, controlled by FRQCRA and FRQCRB, a kick bit has to be set and to make sure the setting has taken effect, it has to be read back repeatedly until it is cleared by the hardware. This patch adds the waiting part, that was missing until now. Signed-off-by: Guennadi Liakhovetski Acked-by: Magnus Damm --- arch/arm/mach-shmobile/clock-sh73a0.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 71843dd39e16..34b5c5ae4cbd 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #define FRQCRA IOMEM(0xe6150000) @@ -234,14 +235,24 @@ static struct clk *main_clks[] = { &sh73a0_extalr_clk, }; -static void div4_kick(struct clk *clk) +static int frqcr_kick(void) { - unsigned long value; + int i; + + /* set KICK bit in FRQCRB to update hardware setting, check success */ + __raw_writel(__raw_readl(FRQCRB) | (1 << 31), FRQCRB); + for (i = 1000; i; i--) + if (__raw_readl(FRQCRB) & (1 << 31)) + cpu_relax(); + else + return i; + + return -ETIMEDOUT; +} - /* set KICK bit in FRQCRB to update hardware setting */ - value = __raw_readl(FRQCRB); - value |= (1 << 31); - __raw_writel(value, FRQCRB); +static void div4_kick(struct clk *clk) +{ + frqcr_kick(); } static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, -- cgit v1.2.1 From ccb7cc749f78166178184f77dd95ea24db9d5bb0 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 21 Mar 2013 03:01:36 -0700 Subject: ARM: shmobile: add R8A7778 basis support Add initial support for the R8A7778 R-Car M1A SoC. No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. It is based on v1.0 datasheet Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 35 ++++++ arch/arm/mach-shmobile/Kconfig | 6 + arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/clock-r8a7778.c | 91 ++++++++++++++ arch/arm/mach-shmobile/include/mach/r8a7778.h | 28 +++++ arch/arm/mach-shmobile/setup-r8a7778.c | 167 ++++++++++++++++++++++++++ 6 files changed, 328 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7778.dtsi create mode 100644 arch/arm/mach-shmobile/clock-r8a7778.c create mode 100644 arch/arm/mach-shmobile/include/mach/r8a7778.h create mode 100644 arch/arm/mach-shmobile/setup-r8a7778.c diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi new file mode 100644 index 000000000000..474373559bdc --- /dev/null +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -0,0 +1,35 @@ +/* + * Device Tree Source for Renesas r8a7778 + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto + * + * based on r8a7779 + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Simon Horman + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "renesas,r8a7778"; + + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + }; + }; + + gic: interrupt-controller@fe438000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfe438000 0x1000>, + <0xfe430000 0x100>; + }; +}; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 0e4a820bcbe8..49cba4a511df 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -33,6 +33,12 @@ config ARCH_R8A7740 select CPU_V7 select SH_CLK_CPG +config ARCH_R8A7778 + bool "R-Car M1 (R8A77780)" + select CPU_V7 + select SH_CLK_CPG + select ARM_GIC + config ARCH_R8A7779 bool "R-Car H1 (R8A77790)" select ARCH_WANT_OPTIONAL_GPIOLIB diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index c5a43ef7cebf..2d42de46db8d 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o +obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c new file mode 100644 index 000000000000..387e3b74cc8c --- /dev/null +++ b/arch/arm/mach-shmobile/clock-r8a7778.c @@ -0,0 +1,91 @@ +/* + * r8a7778 clock framework support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto + * + * based on r8a7779 + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define MSTPCR0 IOMEM(0xffc80030) +#define MSTPCR1 IOMEM(0xffc80034) +#define MSTPCR3 IOMEM(0xffc8003c) +#define MSTPSR1 IOMEM(0xffc80044) +#define MSTPSR4 IOMEM(0xffc80048) +#define MSTPSR6 IOMEM(0xffc8004c) +#define MSTPCR4 IOMEM(0xffc80050) +#define MSTPCR5 IOMEM(0xffc80054) +#define MSTPCR6 IOMEM(0xffc80058) + +/* ioremap() through clock mapping mandatory to avoid + * collision with ARM coherent DMA virtual memory range. + */ + +static struct clk_mapping cpg_mapping = { + .phys = 0xffc80000, + .len = 0x80, +}; + +static struct clk clkp = { + .rate = 62500000, /* FIXME: shortcut */ + .flags = CLK_ENABLE_ON_INIT, + .mapping = &cpg_mapping, +}; + +static struct clk *main_clks[] = { + &clkp, +}; + +enum { + MSTP016, MSTP015, + MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { + [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */ + [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */ +}; + +static struct clk_lookup lookups[] = { + /* MSTP32 clocks */ + CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ + CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ +}; + +void __init r8a7778_clock_init(void) +{ + int k, ret = 0; + + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + + if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + if (!ret) + shmobile_clk_init(); + else + panic("failed to setup r8a7778 clocks\n"); +} diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h new file mode 100644 index 000000000000..a755dcafef4d --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef __ASM_R8A7778_H__ +#define __ASM_R8A7778_H__ + +extern void r8a7778_add_standard_devices(void); +extern void r8a7778_add_standard_devices_dt(void); +extern void r8a7778_init_delay(void); +extern void r8a7778_init_irq(void); +extern void r8a7778_init_irq_dt(void); +extern void r8a7778_clock_init(void); + +#endif /* __ASM_R8A7778_H__ */ diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c new file mode 100644 index 000000000000..811ccf3c77a4 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -0,0 +1,167 @@ +/* + * r8a7778 processor support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* TMU */ +static struct resource sh_tmu0_resources[] = { + DEFINE_RES_MEM(0xffd80008, 12), + DEFINE_RES_IRQ(gic_iid(0x40)), +}; + +static struct sh_timer_config sh_tmu0_platform_data = { + .name = "TMU00", + .channel_offset = 0x4, + .timer_bit = 0, + .clockevent_rating = 200, +}; + +static struct resource sh_tmu1_resources[] = { + DEFINE_RES_MEM(0xffd80014, 12), + DEFINE_RES_IRQ(gic_iid(0x41)), +}; + +static struct sh_timer_config sh_tmu1_platform_data = { + .name = "TMU01", + .channel_offset = 0x10, + .timer_bit = 1, + .clocksource_rating = 200, +}; + +#define PLATFORM_INFO(n, i) \ +{ \ + .parent = &platform_bus, \ + .name = #n, \ + .id = i, \ + .res = n ## i ## _resources, \ + .num_res = ARRAY_SIZE(n ## i ##_resources), \ + .data = &n ## i ##_platform_data, \ + .size_data = sizeof(n ## i ## _platform_data), \ +} + +struct platform_device_info platform_devinfo[] = { + PLATFORM_INFO(sh_tmu, 0), + PLATFORM_INFO(sh_tmu, 1), +}; + +void __init r8a7778_add_standard_devices(void) +{ + int i; + +#ifdef CONFIG_CACHE_L2X0 + void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); + if (base) { + /* + * Early BRESP enable, Shared attribute override enable, 64K*16way + * don't call iounmap(base) + */ + l2x0_init(base, 0x40470000, 0x82000fff); + } +#endif + + for (i = 0; i < ARRAY_SIZE(platform_devinfo); i++) + platform_device_register_full(&platform_devinfo[i]); +} + +#define INT2SMSKCR0 0x82288 /* 0xfe782288 */ +#define INT2SMSKCR1 0x8228c /* 0xfe78228c */ + +#define INT2NTSR0 0x00018 /* 0xfe700018 */ +#define INT2NTSR1 0x0002c /* 0xfe70002c */ +static void __init r8a7778_init_irq_common(void) +{ + void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); + + BUG_ON(!base); + + /* route all interrupts to ARM */ + __raw_writel(0x73ffffff, base + INT2NTSR0); + __raw_writel(0xffffffff, base + INT2NTSR1); + + /* unmask all known interrupts in INTCS2 */ + __raw_writel(0x08330773, base + INT2SMSKCR0); + __raw_writel(0x00311110, base + INT2SMSKCR1); + + iounmap(base); +} + +void __init r8a7778_init_irq(void) +{ + void __iomem *gic_dist_base; + void __iomem *gic_cpu_base; + + gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE); + gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE); + BUG_ON(!gic_dist_base || !gic_cpu_base); + + /* use GIC to handle interrupts */ + gic_init(0, 29, gic_dist_base, gic_cpu_base); + + r8a7778_init_irq_common(); +} + +void __init r8a7778_init_delay(void) +{ + shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ +} + +#ifdef CONFIG_USE_OF +void __init r8a7778_init_irq_dt(void) +{ + irqchip_init(); + r8a7778_init_irq_common(); +} + +static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = { + {}, +}; + +void __init r8a7778_add_standard_devices_dt(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + r8a7778_auxdata_lookup, NULL); +} + +static const char *r8a7778_compat_dt[] __initdata = { + "renesas,r8a7778", + NULL, +}; + +DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") + .init_early = r8a7778_init_delay, + .init_irq = r8a7778_init_irq_dt, + .init_machine = r8a7778_add_standard_devices_dt, + .init_time = shmobile_timer_init, + .dt_compat = r8a7778_compat_dt, +MACHINE_END + +#endif /* CONFIG_USE_OF */ -- cgit v1.2.1 From db331fc8fc715fa6af05bf5e9d428be2ec306475 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 21 Mar 2013 03:02:38 -0700 Subject: ARM: shmobile: r8a7778 SCIF support Add SCIF serial port support to the r8a7778 SoC by adding platform devices together with clock bindings. DT device description is excluded at this point since such bindings are still under development. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7778.c | 13 +++++++++++++ arch/arm/mach-shmobile/setup-r8a7778.c | 26 ++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index 387e3b74cc8c..f1277f45381e 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c @@ -58,16 +58,29 @@ static struct clk *main_clks[] = { }; enum { + MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, MSTP016, MSTP015, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { + [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */ + [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */ + [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */ + [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */ + [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */ + [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */ [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */ [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */ }; static struct clk_lookup lookups[] = { /* MSTP32 clocks */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */ + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ }; diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 811ccf3c77a4..01c62bedf9cf 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,26 @@ #include #include +/* SCIF */ +#define SCIF_INFO(baseaddr, irq) \ +{ \ + .mapbase = baseaddr, \ + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ + .scbrr_algo_id = SCBRR_ALGO_2, \ + .type = PORT_SCIF, \ + .irqs = SCIx_IRQ_MUXED(irq), \ +} + +static struct plat_sci_port scif_platform_data[] = { + SCIF_INFO(0xffe40000, gic_iid(0x66)), + SCIF_INFO(0xffe41000, gic_iid(0x67)), + SCIF_INFO(0xffe42000, gic_iid(0x68)), + SCIF_INFO(0xffe43000, gic_iid(0x69)), + SCIF_INFO(0xffe44000, gic_iid(0x6a)), + SCIF_INFO(0xffe45000, gic_iid(0x6b)), +}; + /* TMU */ static struct resource sh_tmu0_resources[] = { DEFINE_RES_MEM(0xffd80008, 12), @@ -88,6 +109,11 @@ void __init r8a7778_add_standard_devices(void) } #endif + for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) + platform_device_register_data(&platform_bus, "sh-sci", i, + &scif_platform_data[i], + sizeof(struct plat_sci_port)); + for (i = 0; i < ARRAY_SIZE(platform_devinfo); i++) platform_device_register_full(&platform_devinfo[i]); } -- cgit v1.2.1 From 558f874029c904ca694a69e96b4b48c4d54686a3 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 21 Mar 2013 17:05:40 +0100 Subject: ARM: shmobile: sh73a0: add irqpin DT nodes Add DT nodes for the 4 irqpin interrupt controllers on sh73a0. We add them to sh73a0.dtsi, which is also used by configurations, doing all their device instantiation from board the .c code. We rely on the fact, that such configurations don't instantiate devices from the device-tree. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0.dtsi | 81 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 8a59465d0231..7e71e3a85767 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -38,6 +38,87 @@ <0xf0000100 0x100>; }; + irqpin0: irqpin@e6900000 { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900000 4>, + <0xe6900010 4>, + <0xe6900020 1>, + <0xe6900040 1>, + <0xe6900060 1>; + interrupt-parent = <&gic>; + interrupts = <0 1 0x4 + 0 2 0x4 + 0 3 0x4 + 0 4 0x4 + 0 5 0x4 + 0 6 0x4 + 0 7 0x4 + 0 8 0x4>; + }; + + irqpin1: irqpin@e6900004 { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900004 4>, + <0xe6900014 4>, + <0xe6900024 1>, + <0xe6900044 1>, + <0xe6900064 1>; + interrupt-parent = <&gic>; + interrupts = <0 9 0x4 + 0 10 0x4 + 0 11 0x4 + 0 12 0x4 + 0 13 0x4 + 0 14 0x4 + 0 15 0x4 + 0 16 0x4>; + control-parent; + }; + + irqpin2: irqpin@e6900008 { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900008 4>, + <0xe6900018 4>, + <0xe6900028 1>, + <0xe6900048 1>, + <0xe6900068 1>; + interrupt-parent = <&gic>; + interrupts = <0 17 0x4 + 0 18 0x4 + 0 19 0x4 + 0 20 0x4 + 0 21 0x4 + 0 22 0x4 + 0 23 0x4 + 0 24 0x4>; + }; + + irqpin3: irqpin@e690000c { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe690000c 4>, + <0xe690001c 4>, + <0xe690002c 1>, + <0xe690004c 1>, + <0xe690006c 1>; + interrupt-parent = <&gic>; + interrupts = <0 25 0x4 + 0 26 0x4 + 0 27 0x4 + 0 28 0x4 + 0 29 0x4 + 0 30 0x4 + 0 31 0x4 + 0 32 0x4>; + }; + i2c0: i2c@0xe6820000 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.1 From 6722f6cb763203cab775297b6e9d00834af0d6d7 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 18 Mar 2013 22:58:18 +0900 Subject: ARM: shmobile: Disallow PINCTRL without GPIOLIB Modify mach-shmobile to only select PINCTRL in case of ARCH_WANT_OPTIONAL_GPIOLIB is set. This fixes a build error triggered when adding a new SoC lacking GPIO software support (ARCH_WANT_OPTIONAL_GPIOLIB=n): CC drivers/tty/vt/keyboard.o In file included from drivers/pinctrl/core.c:30:0: include/asm-generic/gpio.h: In function 'gpio_get_value_cansleep': include/asm-generic/gpio.h:270:2: error: implicit declaration of function '__gpio_get_value' include/asm-generic/gpio.h: In function 'gpio_set_value_cansleep': include/asm-generic/gpio.h:276:2: error: implicit declaration of function '__gpio_set_value' drivers/pinctrl/core.c: In function 'pinctrl_ready_for_gpio_range': drivers/pinctrl/core.c:297:9: error: implicit declaration of function 'gpio_to_chip' drivers/pinctrl/core.c:297:27: warning: initialization makes pointer from integer without a cast drivers/pinctrl/core.c:304:45: error: dereferencing pointer to incomplete type drivers/pinctrl/core.c:305:26: error: dereferencing pointer to incomplete type drivers/pinctrl/core.c:305:39: error: dereferencing pointer to incomplete type make[2]: *** [drivers/pinctrl/core.o] Error 1 make[1]: *** [drivers/pinctrl] Error 2 make[1]: *** Waiting for unfinished jobs.... LD drivers/sh/built-in.o Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5b714695b01b..b63902e7cacd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -725,7 +725,7 @@ config ARCH_SHMOBILE select MULTI_IRQ_HANDLER select NEED_MACH_MEMORY_H select NO_IOPORT - select PINCTRL + select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB select PM_GENERIC_DOMAINS if PM select SPARSE_IRQ help -- cgit v1.2.1 From c91cf2fad00f24bfe268d30b75e4015aaa326c04 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 25 Mar 2013 23:18:15 -0700 Subject: ARM: shmobile: r8a73a4: add thermal driver support You can get current thermal by > cat /sys/class/thermal/thermal_zone?/temp Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 7 +++++++ arch/arm/mach-shmobile/clock-r8a73a4.c | 13 ++++++++++++- arch/arm/mach-shmobile/setup-r8a73a4.c | 15 +++++++++++++++ 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 4c68ba15727c..7db5b504e64c 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -84,4 +84,11 @@ <0 56 4>, <0 57 4>; }; + thermal@e61f0000 { + compatible = "renesas,rcar-thermal"; + reg = <0xe61f0000 0x14>, <0xe61f0100 0x38>, + <0xe61f0200 0x38>, <0xe61f0300 0x38>; + interrupt-parent = <&gic>; + interrupts = <0 69 4>; + }; }; diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 037713bdff3f..e710c00c3822 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -29,6 +29,7 @@ #define MPCKCR 0xe6150080 #define SMSTPCR2 0xe6150138 +#define SMSTPCR5 0xe6150144 static struct clk_mapping cpg_mapping = { .phys = CPG_BASE, @@ -56,7 +57,12 @@ static struct clk *main_clks[] = { &extal2_clk, }; -enum { MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP_NR }; +enum { + MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, + MSTP522, + MSTP_NR +}; + static struct clk mstp_clks[MSTP_NR] = { [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ @@ -64,6 +70,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */ + [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ }; static struct clk_lookup lookups[] = { @@ -73,6 +80,10 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), + CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), + + /* for DT */ + CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), }; void __init r8a73a4_clock_init(void) diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index c2d86f30cde4..c5a75a7a508f 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -155,6 +155,20 @@ static const struct resource irqc1_resources[] = { &irqc##idx##_data, \ sizeof(struct renesas_irqc_config)) +/* Thermal0 -> Thermal2 */ +static const struct resource thermal0_resources[] = { + DEFINE_RES_MEM(0xe61f0000, 0x14), + DEFINE_RES_MEM(0xe61f0100, 0x38), + DEFINE_RES_MEM(0xe61f0200, 0x38), + DEFINE_RES_MEM(0xe61f0300, 0x38), + DEFINE_RES_IRQ(gic_spi(69)), +}; + +#define r8a73a4_register_thermal() \ + platform_device_register_simple("rcar_thermal", -1, \ + thermal0_resources, \ + ARRAY_SIZE(thermal0_resources)) + void __init r8a73a4_add_standard_devices(void) { r8a73a4_register_scif(SCIFA0); @@ -165,6 +179,7 @@ void __init r8a73a4_add_standard_devices(void) r8a73a4_register_scif(SCIFB3); r8a73a4_register_irqc(0); r8a73a4_register_irqc(1); + r8a73a4_register_thermal(); } #ifdef CONFIG_USE_OF -- cgit v1.2.1 From 0b7d78202260162057248875b1c9bac70d041e58 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Wed, 27 Mar 2013 14:54:04 +0100 Subject: ARM: shmobile: r8a7740: Migrate from INTC to GIC With the added capabilty of the intc_irqpin driver to handle shared external IRQs, all prerequisites are fulfilled and we are ready to migrate completely to GIC. This includes the following steps: - Kconfig: select ARM_GIC and RENESAS_INTC_IRQPIN - intc-r8a7740: Throw out all legacy INTC code and init the GIC. We need to mask out all shared IRQs as it is needed by the shared intc_irqpin driver. - setup-r8a7740: Add 4 irqpin devices to handle external IRQs and update all IRQ numbers to point to the GIC SPI. - board-armadillo: Update all IRQ numbers to point to the GIC SPI. - pfc-r8a7740: Update all IRQ numbers of the GPIOs to point to the GIC SPI. Signed-off-by: Bastian Hecht Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Kconfig | 2 + arch/arm/mach-shmobile/board-armadillo800eva.c | 35 +- arch/arm/mach-shmobile/intc-r8a7740.c | 641 ++----------------------- arch/arm/mach-shmobile/setup-r8a7740.c | 192 ++++++-- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 64 +-- 5 files changed, 239 insertions(+), 695 deletions(-) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 49cba4a511df..d569c34b1c86 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -30,8 +30,10 @@ config ARCH_R8A73A4 config ARCH_R8A7740 bool "R-Mobile A1 (R8A77400)" select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_GIC select CPU_V7 select SH_CLK_CPG + select RENESAS_INTC_IRQPIN config ARCH_R8A7778 bool "R-Car M1 (R8A77780)" diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index f2ec0777cfbe..e451327278af 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -145,7 +145,7 @@ * see * usbhsf_power_ctrl() */ -#define IRQ7 evt2irq(0x02e0) +#define IRQ7 irq_pin(7) #define USBCR1 IOMEM(0xe605810a) #define USBH 0xC6700000 #define USBH_USBCTR 0x10834 @@ -330,7 +330,7 @@ static struct resource usbhsf_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = evt2irq(0x0A20), + .start = gic_spi(51), .flags = IORESOURCE_IRQ, }, }; @@ -363,7 +363,7 @@ static struct resource sh_eth_resources[] = { .end = 0xe9a02000 - 1, .flags = IORESOURCE_MEM, }, { - .start = evt2irq(0x0500), + .start = gic_spi(110), .flags = IORESOURCE_IRQ, }, }; @@ -417,7 +417,7 @@ static struct resource lcdc0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0x580), + .start = gic_spi(177), .flags = IORESOURCE_IRQ, }, }; @@ -452,7 +452,7 @@ static struct resource hdmi_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = evt2irq(0x1700), + .start = gic_spi(131), .flags = IORESOURCE_IRQ, }, [2] = { @@ -514,7 +514,7 @@ static struct resource hdmi_lcdc_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0x1780), + .start = gic_spi(178), .flags = IORESOURCE_IRQ, }, }; @@ -574,7 +574,7 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] = * We can use IRQ31 as card detect irq, * but it needs chattering removal operation */ -#define IRQ31 evt2irq(0x33E0) +#define IRQ31 irq_pin(31) static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, @@ -596,12 +596,12 @@ static struct resource sdhi0_resources[] = { */ { .name = SH_MOBILE_SDHI_IRQ_SDCARD, - .start = evt2irq(0x0E20), + .start = gic_spi(118), .flags = IORESOURCE_IRQ, }, { .name = SH_MOBILE_SDHI_IRQ_SDIO, - .start = evt2irq(0x0E40), + .start = gic_spi(119), .flags = IORESOURCE_IRQ, }, }; @@ -633,15 +633,15 @@ static struct resource sdhi1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = evt2irq(0x0E80), + .start = gic_spi(121), .flags = IORESOURCE_IRQ, }, [2] = { - .start = evt2irq(0x0EA0), + .start = gic_spi(122), .flags = IORESOURCE_IRQ, }, [3] = { - .start = evt2irq(0x0EC0), + .start = gic_spi(123), .flags = IORESOURCE_IRQ, }, }; @@ -674,12 +674,12 @@ static struct resource sh_mmcif_resources[] = { }, [1] = { /* MMC ERR */ - .start = evt2irq(0x1AC0), + .start = gic_spi(56), .flags = IORESOURCE_IRQ, }, [2] = { /* MMC NOR */ - .start = evt2irq(0x1AE0), + .start = gic_spi(57), .flags = IORESOURCE_IRQ, }, }; @@ -756,7 +756,7 @@ static struct resource ceu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0x0500), + .start = gic_spi(160), .flags = IORESOURCE_IRQ, }, [2] = { @@ -798,7 +798,7 @@ static struct resource fsi_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = evt2irq(0x1840), + .start = gic_spi(9), .flags = IORESOURCE_IRQ, }, }; @@ -881,7 +881,7 @@ static struct platform_device i2c_gpio_device = { static struct i2c_board_info i2c0_devices[] = { { I2C_BOARD_INFO("st1232-ts", 0x55), - .irq = evt2irq(0x0340), + .irq = irq_pin(10), }, { I2C_BOARD_INFO("wm8978", 0x1a), @@ -1207,7 +1207,6 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva") .map_io = r8a7740_map_io, .init_early = eva_add_early_devices, .init_irq = r8a7740_init_irq, - .handle_irq = shmobile_handle_irq_intc, .init_machine = eva_init, .init_late = shmobile_init_late, .init_time = eva_earlytimer_init, diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c index 9a69a31918ba..b741c8409a5a 100644 --- a/arch/arm/mach-shmobile/intc-r8a7740.c +++ b/arch/arm/mach-shmobile/intc-r8a7740.c @@ -18,620 +18,39 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include #include -#include -#include #include -#include -#include -#include -#include -#include - -/* - * INTCA - */ -enum { - UNUSED_INTCA = 0, - - /* interrupt sources INTCA */ - DIRC, - ATAPI, - IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI, - AP_ARM_COMMTX, AP_ARM_COMMRX, - MFI, MFIS, - BBIF1, BBIF2, - USBHSDMAC, - USBF_OUL_SOF, USBF_IXL_INT, - SGX540, - CMT1_0, CMT1_1, CMT1_2, CMT1_3, - CMT2, - CMT3, - KEYSC, - SCIFA0, SCIFA1, SCIFA2, SCIFA3, - MSIOF2, MSIOF1, - SCIFA4, SCIFA5, SCIFB, - FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, - SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3, - SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3, - AP_ARM_L2CINT, - IRDA, - TPU0, - SCIFA6, SCIFA7, - GbEther, - ICBS0, - DDM, - SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3, - RWDT0, - DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3, - DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR, - DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, - DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, - DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, - DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, - SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, - HDMI, - USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND, - RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, - SPU2_0, SPU2_1, - FSI, FMSI, - HDMI_SSS, HDMI_KEY, - IPMMU, - AP_ARM_CTIIRQ, AP_ARM_PMURQ, - MFIS2, - CPORTR2S, - CMT14, CMT15, - MMCIF_0, MMCIF_1, MMCIF_2, - SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, - STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4, - - /* interrupt groups INTCA */ - DMAC1_1, DMAC1_2, - DMAC2_1, DMAC2_2, - DMAC3_1, DMAC3_2, - AP_ARM1, AP_ARM2, - SDHI0, SDHI1, SDHI2, - SHWYSTAT, - USBF, USBH1, USBH2, - RSPI, SPU2, FLCTL, IIC1, -}; - -static struct intc_vect intca_vectors[] __initdata = { - INTC_VECT(DIRC, 0x0560), - INTC_VECT(ATAPI, 0x05E0), - INTC_VECT(IIC1_ALI, 0x0780), - INTC_VECT(IIC1_TACKI, 0x07A0), - INTC_VECT(IIC1_WAITI, 0x07C0), - INTC_VECT(IIC1_DTEI, 0x07E0), - INTC_VECT(AP_ARM_COMMTX, 0x0840), - INTC_VECT(AP_ARM_COMMRX, 0x0860), - INTC_VECT(MFI, 0x0900), - INTC_VECT(MFIS, 0x0920), - INTC_VECT(BBIF1, 0x0940), - INTC_VECT(BBIF2, 0x0960), - INTC_VECT(USBHSDMAC, 0x0A00), - INTC_VECT(USBF_OUL_SOF, 0x0A20), - INTC_VECT(USBF_IXL_INT, 0x0A40), - INTC_VECT(SGX540, 0x0A60), - INTC_VECT(CMT1_0, 0x0B00), - INTC_VECT(CMT1_1, 0x0B20), - INTC_VECT(CMT1_2, 0x0B40), - INTC_VECT(CMT1_3, 0x0B60), - INTC_VECT(CMT2, 0x0B80), - INTC_VECT(CMT3, 0x0BA0), - INTC_VECT(KEYSC, 0x0BE0), - INTC_VECT(SCIFA0, 0x0C00), - INTC_VECT(SCIFA1, 0x0C20), - INTC_VECT(SCIFA2, 0x0C40), - INTC_VECT(SCIFA3, 0x0C60), - INTC_VECT(MSIOF2, 0x0C80), - INTC_VECT(MSIOF1, 0x0D00), - INTC_VECT(SCIFA4, 0x0D20), - INTC_VECT(SCIFA5, 0x0D40), - INTC_VECT(SCIFB, 0x0D60), - INTC_VECT(FLCTL_FLSTEI, 0x0D80), - INTC_VECT(FLCTL_FLTENDI, 0x0DA0), - INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0), - INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0), - INTC_VECT(SDHI0_0, 0x0E00), - INTC_VECT(SDHI0_1, 0x0E20), - INTC_VECT(SDHI0_2, 0x0E40), - INTC_VECT(SDHI0_3, 0x0E60), - INTC_VECT(SDHI1_0, 0x0E80), - INTC_VECT(SDHI1_1, 0x0EA0), - INTC_VECT(SDHI1_2, 0x0EC0), - INTC_VECT(SDHI1_3, 0x0EE0), - INTC_VECT(AP_ARM_L2CINT, 0x0FA0), - INTC_VECT(IRDA, 0x0480), - INTC_VECT(TPU0, 0x04A0), - INTC_VECT(SCIFA6, 0x04C0), - INTC_VECT(SCIFA7, 0x04E0), - INTC_VECT(GbEther, 0x0500), - INTC_VECT(ICBS0, 0x0540), - INTC_VECT(DDM, 0x1140), - INTC_VECT(SDHI2_0, 0x1200), - INTC_VECT(SDHI2_1, 0x1220), - INTC_VECT(SDHI2_2, 0x1240), - INTC_VECT(SDHI2_3, 0x1260), - INTC_VECT(RWDT0, 0x1280), - INTC_VECT(DMAC1_1_DEI0, 0x2000), - INTC_VECT(DMAC1_1_DEI1, 0x2020), - INTC_VECT(DMAC1_1_DEI2, 0x2040), - INTC_VECT(DMAC1_1_DEI3, 0x2060), - INTC_VECT(DMAC1_2_DEI4, 0x2080), - INTC_VECT(DMAC1_2_DEI5, 0x20A0), - INTC_VECT(DMAC1_2_DADERR, 0x20C0), - INTC_VECT(DMAC2_1_DEI0, 0x2100), - INTC_VECT(DMAC2_1_DEI1, 0x2120), - INTC_VECT(DMAC2_1_DEI2, 0x2140), - INTC_VECT(DMAC2_1_DEI3, 0x2160), - INTC_VECT(DMAC2_2_DEI4, 0x2180), - INTC_VECT(DMAC2_2_DEI5, 0x21A0), - INTC_VECT(DMAC2_2_DADERR, 0x21C0), - INTC_VECT(DMAC3_1_DEI0, 0x2200), - INTC_VECT(DMAC3_1_DEI1, 0x2220), - INTC_VECT(DMAC3_1_DEI2, 0x2240), - INTC_VECT(DMAC3_1_DEI3, 0x2260), - INTC_VECT(DMAC3_2_DEI4, 0x2280), - INTC_VECT(DMAC3_2_DEI5, 0x22A0), - INTC_VECT(DMAC3_2_DADERR, 0x22C0), - INTC_VECT(SHWYSTAT_RT, 0x1300), - INTC_VECT(SHWYSTAT_HS, 0x1320), - INTC_VECT(SHWYSTAT_COM, 0x1340), - INTC_VECT(USBH_INT, 0x1540), - INTC_VECT(USBH_OHCI, 0x1560), - INTC_VECT(USBH_EHCI, 0x1580), - INTC_VECT(USBH_PME, 0x15A0), - INTC_VECT(USBH_BIND, 0x15C0), - INTC_VECT(HDMI, 0x1700), - INTC_VECT(RSPI_OVRF, 0x1780), - INTC_VECT(RSPI_SPTEF, 0x17A0), - INTC_VECT(RSPI_SPRF, 0x17C0), - INTC_VECT(SPU2_0, 0x1800), - INTC_VECT(SPU2_1, 0x1820), - INTC_VECT(FSI, 0x1840), - INTC_VECT(FMSI, 0x1860), - INTC_VECT(HDMI_SSS, 0x18A0), - INTC_VECT(HDMI_KEY, 0x18C0), - INTC_VECT(IPMMU, 0x1920), - INTC_VECT(AP_ARM_CTIIRQ, 0x1980), - INTC_VECT(AP_ARM_PMURQ, 0x19A0), - INTC_VECT(MFIS2, 0x1A00), - INTC_VECT(CPORTR2S, 0x1A20), - INTC_VECT(CMT14, 0x1A40), - INTC_VECT(CMT15, 0x1A60), - INTC_VECT(MMCIF_0, 0x1AA0), - INTC_VECT(MMCIF_1, 0x1AC0), - INTC_VECT(MMCIF_2, 0x1AE0), - INTC_VECT(SIM_ERI, 0x1C00), - INTC_VECT(SIM_RXI, 0x1C20), - INTC_VECT(SIM_TXI, 0x1C40), - INTC_VECT(SIM_TEI, 0x1C60), - INTC_VECT(STPRO_0, 0x1C80), - INTC_VECT(STPRO_1, 0x1CA0), - INTC_VECT(STPRO_2, 0x1CC0), - INTC_VECT(STPRO_3, 0x1CE0), - INTC_VECT(STPRO_4, 0x1D00), -}; - -static struct intc_group intca_groups[] __initdata = { - INTC_GROUP(DMAC1_1, - DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3), - INTC_GROUP(DMAC1_2, - DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR), - INTC_GROUP(DMAC2_1, - DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), - INTC_GROUP(DMAC2_2, - DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR), - INTC_GROUP(DMAC3_1, - DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), - INTC_GROUP(DMAC3_2, - DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR), - INTC_GROUP(AP_ARM1, - AP_ARM_COMMTX, AP_ARM_COMMRX), - INTC_GROUP(AP_ARM2, - AP_ARM_CTIIRQ, AP_ARM_PMURQ), - INTC_GROUP(USBF, - USBF_OUL_SOF, USBF_IXL_INT), - INTC_GROUP(SDHI0, - SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3), - INTC_GROUP(SDHI1, - SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3), - INTC_GROUP(SDHI2, - SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3), - INTC_GROUP(SHWYSTAT, - SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), - INTC_GROUP(USBH1, /* FIXME */ - USBH_INT, USBH_OHCI), - INTC_GROUP(USBH2, /* FIXME */ - USBH_EHCI, - USBH_PME, USBH_BIND), - INTC_GROUP(RSPI, - RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF), - INTC_GROUP(SPU2, - SPU2_0, SPU2_1), - INTC_GROUP(FLCTL, - FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), - INTC_GROUP(IIC1, - IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI), -}; - -static struct intc_mask_reg intca_mask_registers[] __initdata = { - { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8, - { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, - 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, - { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8, - { ATAPI, 0, DIRC, 0, - DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } }, - { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8, - { 0, 0, 0, 0, - BBIF1, BBIF2, MFIS, MFI } }, - { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8, - { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, - DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, - { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8, - { DDM, 0, 0, 0, - 0, 0, 0, 0 } }, - { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8, - { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4, - SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, - { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8, - { SCIFB, SCIFA5, SCIFA4, MSIOF1, - 0, 0, MSIOF2, 0 } }, - { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8, - { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0, - FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, - { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8, - { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0, - 0, USBHSDMAC, 0, AP_ARM_L2CINT } }, - { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8, - { CMT1_3, CMT1_2, CMT1_1, CMT1_0, - CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } }, - { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8, - { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, - 0, 0, 0, 0 } }, - { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8, - { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI, - ICBS0, 0, 0, 0 } }, - { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8, - { 0, 0, TPU0, SCIFA6, - SCIFA7, GbEther, 0, 0 } }, - { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8, - { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0, - 0, CMT3, 0, RWDT0 } }, - { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8, - { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, - 0, 0, 0, 0 } }, - /* IMR1A3 / IMCR1A3 */ - { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8, - { 0, 0, USBH_INT, USBH_OHCI, - USBH_EHCI, USBH_PME, USBH_BIND, 0 } }, - /* IMR3A3 / IMCR3A3 */ - { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8, - { HDMI, 0, 0, 0, - RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } }, - { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8, - { SPU2_0, SPU2_1, FSI, FMSI, - 0, HDMI_SSS, HDMI_KEY, 0 } }, - { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8, - { 0, IPMMU, 0, 0, - AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } }, - { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8, - { MFIS2, CPORTR2S, CMT14, CMT15, - 0, MMCIF_0, MMCIF_1, MMCIF_2 } }, - /* IMR8A3 / IMCR8A3 */ - { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8, - { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, - STPRO_0, STPRO_1, STPRO_2, STPRO_3 } }, - { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8, - { STPRO_4, 0, 0, 0, - 0, 0, 0, 0 } }, -}; - -static struct intc_prio_reg intca_prio_registers[] __initdata = { - { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } }, - { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, - { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } }, - { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } }, - { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } }, - { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2, - SGX540, CMT1_0 } }, - { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, - SCIFA2, SCIFA3 } }, - { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC, - FLCTL, SDHI0 } }, - { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } }, - { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, - AP_ARM_L2CINT, 0 } }, - { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } }, - { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6, - SCIFA7, GbEther } }, - { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } }, - { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } }, - { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, - { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } }, - /* IPRBA3 */ - /* IPRCA3 */ - /* IPRDA3 */ - { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } }, - { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } }, - /* IPRGA3 */ - /* IPRHA3 */ - { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { HDMI, 0, 0, 0 } }, - { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } }, - { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } }, - { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, HDMI_SSS, HDMI_KEY, 0 } }, - { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } }, - { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, - { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, - CMT14, CMT15 } }, - { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } }, - /* IPRQA3 */ - /* IPRRA3 */ - { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI, - SIM_TXI, SIM_TEI } }, - { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1, - STPRO_2, STPRO_3 } }, - { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } }, -}; - -static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca", - intca_vectors, intca_groups, - intca_mask_registers, intca_prio_registers, - NULL); - -INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, - INTC_VECT, "r8a7740-intca-irq-pins"); - - -/* - * INTCS - */ -enum { - UNUSED_INTCS = 0, - - INTCS, - - /* interrupt sources INTCS */ - - /* HUDI */ - /* STPRO */ - /* RTDMAC(1) */ - VPU5HA2, - _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT, - /* MFI */ - /* BBIF2 */ - VPU5F, - _2DG_BRK_INT, - /* SGX540 */ - /* 2DDMAC */ - /* IPMMU */ - /* RTDMAC 2 */ - /* KEYSC */ - /* MSIOF */ - IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI, - TMU0_0, TMU0_1, TMU0_2, - CMT0, - /* CMT2 */ - LMB, - CTI, - VOU, - /* RWDT0 */ - ICB, - VIO6C, - CEU20, CEU21, - JPU, - LCDC0, - LCRC, - /* RTDMAC2(1) */ - /* RTDMAC2(2) */ - LCDC1, - /* SPU2 */ - /* FSI */ - /* FMSI */ - TMU1_0, TMU1_1, TMU1_2, - CMT4, - DISP, - DSRV, - /* MFIS2 */ - CPORTS2R, - - /* interrupt groups INTCS */ - _2DG1, - IIC0, TMU1, -}; - -static struct intc_vect intcs_vectors[] = { - /* HUDI */ - /* STPRO */ - /* RTDMAC(1) */ - INTCS_VECT(VPU5HA2, 0x0880), - INTCS_VECT(_2DG_TRAP, 0x08A0), - INTCS_VECT(_2DG_GPM_INT, 0x08C0), - INTCS_VECT(_2DG_CER_INT, 0x08E0), - /* MFI */ - /* BBIF2 */ - INTCS_VECT(VPU5F, 0x0980), - INTCS_VECT(_2DG_BRK_INT, 0x09A0), - /* SGX540 */ - /* 2DDMAC */ - /* IPMMU */ - /* RTDMAC(2) */ - /* KEYSC */ - /* MSIOF */ - INTCS_VECT(IIC0_ALI, 0x0E00), - INTCS_VECT(IIC0_TACKI, 0x0E20), - INTCS_VECT(IIC0_WAITI, 0x0E40), - INTCS_VECT(IIC0_DTEI, 0x0E60), - INTCS_VECT(TMU0_0, 0x0E80), - INTCS_VECT(TMU0_1, 0x0EA0), - INTCS_VECT(TMU0_2, 0x0EC0), - INTCS_VECT(CMT0, 0x0F00), - /* CMT2 */ - INTCS_VECT(LMB, 0x0F60), - INTCS_VECT(CTI, 0x0400), - INTCS_VECT(VOU, 0x0420), - /* RWDT0 */ - INTCS_VECT(ICB, 0x0480), - INTCS_VECT(VIO6C, 0x04E0), - INTCS_VECT(CEU20, 0x0500), - INTCS_VECT(CEU21, 0x0520), - INTCS_VECT(JPU, 0x0560), - INTCS_VECT(LCDC0, 0x0580), - INTCS_VECT(LCRC, 0x05A0), - /* RTDMAC2(1) */ - /* RTDMAC2(2) */ - INTCS_VECT(LCDC1, 0x1780), - /* SPU2 */ - /* FSI */ - /* FMSI */ - INTCS_VECT(TMU1_0, 0x1900), - INTCS_VECT(TMU1_1, 0x1920), - INTCS_VECT(TMU1_2, 0x1940), - INTCS_VECT(CMT4, 0x1980), - INTCS_VECT(DISP, 0x19A0), - INTCS_VECT(DSRV, 0x19C0), - /* MFIS2 */ - INTCS_VECT(CPORTS2R, 0x1A20), - - INTC_VECT(INTCS, 0xf80), -}; - -static struct intc_group intcs_groups[] __initdata = { - INTC_GROUP(_2DG1, /*FIXME*/ - _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP), - INTC_GROUP(IIC0, - IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI), - INTC_GROUP(TMU1, - TMU1_0, TMU1_1, TMU1_2), -}; - -static struct intc_mask_reg intcs_mask_registers[] = { - /* IMR0SA / IMCR0SA */ /* all 0 */ - { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8, - { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2, - 0, 0, 0, 0 /*STPRO*/ } }, - { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8, - { 0/*STPRO*/, 0, CEU21, VPU5F, - 0/*BBIF2*/, 0, 0, 0/*MFI*/ } }, - { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8, - { 0, 0, 0, 0, /*2DDMAC*/ - VIO6C, 0, 0, ICB } }, - { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8, - { 0, 0, VOU, CTI, - JPU, 0, LCRC, LCDC0 } }, - /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/ - /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/ - { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8, - { 0, TMU0_2, TMU0_1, TMU0_0, - 0, 0, 0, 0 } }, - { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8, - { 0, 0, 0, 0, - CEU20, 0, 0, 0 } }, - { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8, - { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0, - 0, 0, 0, 0 } }, - /* IMR10SA / IMCR10SA */ /*IPMMU*/ - { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8, - { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI, - 0, _2DG_BRK_INT, LMB, 0 } }, - /* IMR12SA / IMCR12SA */ - /* IMR13SA / IMCR13SA */ - /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/ - /* IMR1SA3 / IMCR1SA3 */ - /* IMR2SA3 / IMCR2SA3 */ - /* IMR3SA3 / IMCR3SA3 */ - { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8, - { 0, 0, 0, 0, - LCDC1, 0, 0, 0 } }, - /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */ - { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8, - { TMU1_0, TMU1_1, TMU1_2, 0, - CMT4, DISP, DSRV, 0 } }, - { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8, - { 0/*MFIS2*/, CPORTS2R, 0, 0, - 0, 0, 0, 0 } }, - { /* INTAMASK */ 0xffd20104, 0, 16, - { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, INTCS } }, -}; - -/* Priority is needed for INTCA to receive the INTCS interrupt */ -static struct intc_prio_reg intcs_prio_registers[] = { - { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } }, - { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } }, - /* IPRCS */ /*BBIF2*/ - /* IPRDS */ - { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2, - 0/*MFI*/, VPU5F } }, - { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/, - 0/*CMT2*/, CMT0 } }, - { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1, - TMU0_2, _2DG1 } }, - { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/, - _2DG_BRK_INT/*FIXME*/ } }, - { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } }, - { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } }, - { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } }, - { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } }, - /* IPRMS */ /*RWDT0*/ - /* IPRAS3 */ /*RTDMAC2(1)*/ - /* IPRBS3 */ /*RTDMAC2(2)*/ - /* IPRCS3 */ - /* IPRDS3 */ - /* IPRES3 */ - /* IPRFS3 */ - /* IPRGS3 */ - /* IPRHS3 */ - /* IPRIS3 */ - { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } }, - /* IPRKS3 */ /*SPU2/FSI/FMSi*/ - /* IPRLS3 */ - { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } }, - { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } }, - { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } }, - /* IPRPS3 */ -}; - -static struct resource intcs_resources[] __initdata = { - [0] = { - .start = 0xffd20000, - .end = 0xffd201ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0xffd50000, - .end = 0xffd501ff, - .flags = IORESOURCE_MEM, - } -}; - -static struct intc_desc intcs_desc __initdata = { - .name = "r8a7740-intcs", - .resource = intcs_resources, - .num_resources = ARRAY_SIZE(intcs_resources), - .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, - intcs_prio_registers, NULL, NULL), -}; - -static void intcs_demux(unsigned int irq, struct irq_desc *desc) -{ - void __iomem *reg = (void *)irq_get_handler_data(irq); - unsigned int evtcodeas = ioread32(reg); - - generic_handle_irq(intcs_evt2irq(evtcodeas)); -} +#include void __init r8a7740_init_irq(void) { - void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); - - register_intc_controller(&intca_desc); - register_intc_controller(&intca_irq_pins_desc); - register_intc_controller(&intcs_desc); - - /* demux using INTEVTSA */ - irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); - irq_set_chained_handler(evt2irq(0xf80), intcs_demux); + void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000); + void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000); + void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); + void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); + void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); + + /* initialize the Generic Interrupt Controller PL390 r0p0 */ + gic_init(0, 29, gic_dist_base, gic_cpu_base); + + /* route signals to GIC */ + iowrite32(0x0, pfc_inta_ctrl); + + /* + * To mask the shared interrupt to SPI 149 we must ensure to set + * PRIO *and* MASK. Else we run into IRQ floods when registering + * the intc_irqpin devices + */ + iowrite32(0x0, intc_prio_base + 0x0); + iowrite32(0x0, intc_prio_base + 0x4); + iowrite32(0x0, intc_prio_base + 0x8); + iowrite32(0x0, intc_prio_base + 0xc); + iowrite8(0xff, intc_msk_base + 0x0); + iowrite8(0xff, intc_msk_base + 0x4); + iowrite8(0xff, intc_msk_base + 0x8); + iowrite8(0xff, intc_msk_base + 0xc); + + iounmap(intc_prio_base); + iounmap(intc_msk_base); + iounmap(pfc_inta_ctrl); } diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 8b85d4d8fab6..228d7aba4a7c 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -94,6 +95,126 @@ void __init r8a7740_pinmux_init(void) platform_device_register(&r8a7740_pfc_device); } +static struct renesas_intc_irqpin_config irqpin0_platform_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ +}; + +static struct resource irqpin0_resources[] = { + DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ + DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ + DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ + DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ + DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */ +}; + +static struct platform_device irqpin0_device = { + .name = "renesas_intc_irqpin", + .id = 0, + .resource = irqpin0_resources, + .num_resources = ARRAY_SIZE(irqpin0_resources), + .dev = { + .platform_data = &irqpin0_platform_data, + }, +}; + +static struct renesas_intc_irqpin_config irqpin1_platform_data = { + .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ +}; + +static struct resource irqpin1_resources[] = { + DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ + DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ + DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ + DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ + DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */ +}; + +static struct platform_device irqpin1_device = { + .name = "renesas_intc_irqpin", + .id = 1, + .resource = irqpin1_resources, + .num_resources = ARRAY_SIZE(irqpin1_resources), + .dev = { + .platform_data = &irqpin1_platform_data, + }, +}; + +static struct renesas_intc_irqpin_config irqpin2_platform_data = { + .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ +}; + +static struct resource irqpin2_resources[] = { + DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ + DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */ + DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */ + DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */ + DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */ +}; + +static struct platform_device irqpin2_device = { + .name = "renesas_intc_irqpin", + .id = 2, + .resource = irqpin2_resources, + .num_resources = ARRAY_SIZE(irqpin2_resources), + .dev = { + .platform_data = &irqpin2_platform_data, + }, +}; + +static struct renesas_intc_irqpin_config irqpin3_platform_data = { + .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ +}; + +static struct resource irqpin3_resources[] = { + DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */ + DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ + DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ + DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ + DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */ + DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */ +}; + +static struct platform_device irqpin3_device = { + .name = "renesas_intc_irqpin", + .id = 3, + .resource = irqpin3_resources, + .num_resources = ARRAY_SIZE(irqpin3_resources), + .dev = { + .platform_data = &irqpin3_platform_data, + }, +}; + /* SCIFA0 */ static struct plat_sci_port scif0_platform_data = { .mapbase = 0xe6c40000, @@ -101,7 +222,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)), + .irqs = SCIx_IRQ_MUXED(gic_spi(100)), }; static struct platform_device scif0_device = { @@ -119,7 +240,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)), + .irqs = SCIx_IRQ_MUXED(gic_spi(101)), }; static struct platform_device scif1_device = { @@ -137,7 +258,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)), + .irqs = SCIx_IRQ_MUXED(gic_spi(102)), }; static struct platform_device scif2_device = { @@ -155,7 +276,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)), + .irqs = SCIx_IRQ_MUXED(gic_spi(103)), }; static struct platform_device scif3_device = { @@ -173,7 +294,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)), + .irqs = SCIx_IRQ_MUXED(gic_spi(104)), }; static struct platform_device scif4_device = { @@ -191,7 +312,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)), + .irqs = SCIx_IRQ_MUXED(gic_spi(105)), }; static struct platform_device scif5_device = { @@ -209,7 +330,7 @@ static struct plat_sci_port scif6_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)), + .irqs = SCIx_IRQ_MUXED(gic_spi(106)), }; static struct platform_device scif6_device = { @@ -227,7 +348,7 @@ static struct plat_sci_port scif7_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)), + .irqs = SCIx_IRQ_MUXED(gic_spi(107)), }; static struct platform_device scif7_device = { @@ -245,7 +366,7 @@ static struct plat_sci_port scifb_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFB, - .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)), + .irqs = SCIx_IRQ_MUXED(gic_spi(108)), }; static struct platform_device scifb_device = { @@ -273,7 +394,7 @@ static struct resource cmt10_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = evt2irq(0x0b00), + .start = gic_spi(58), .flags = IORESOURCE_IRQ, }, }; @@ -304,7 +425,7 @@ static struct resource tmu00_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0xe80), + .start = gic_spi(198), .flags = IORESOURCE_IRQ, }, }; @@ -334,7 +455,7 @@ static struct resource tmu01_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0xea0), + .start = gic_spi(199), .flags = IORESOURCE_IRQ, }, }; @@ -364,7 +485,7 @@ static struct resource tmu02_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0xec0), + .start = gic_spi(200), .flags = IORESOURCE_IRQ, }, }; @@ -411,6 +532,10 @@ static struct platform_device ipmmu_device = { }; static struct platform_device *r8a7740_early_devices[] __initdata = { + &irqpin0_device, + &irqpin1_device, + &irqpin2_device, + &irqpin3_device, &scif0_device, &scif1_device, &scif2_device, @@ -525,14 +650,14 @@ static struct resource r8a7740_dmae0_resources[] = { }, { .name = "error_irq", - .start = evt2irq(0x20c0), - .end = evt2irq(0x20c0), + .start = gic_spi(34), + .end = gic_spi(34), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-5 */ - .start = evt2irq(0x2000), - .end = evt2irq(0x20a0), + .start = gic_spi(28), + .end = gic_spi(33), .flags = IORESOURCE_IRQ, }, }; @@ -553,14 +678,14 @@ static struct resource r8a7740_dmae1_resources[] = { }, { .name = "error_irq", - .start = evt2irq(0x21c0), - .end = evt2irq(0x21c0), + .start = gic_spi(41), + .end = gic_spi(41), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-5 */ - .start = evt2irq(0x2100), - .end = evt2irq(0x21a0), + .start = gic_spi(35), + .end = gic_spi(40), .flags = IORESOURCE_IRQ, }, }; @@ -581,14 +706,14 @@ static struct resource r8a7740_dmae2_resources[] = { }, { .name = "error_irq", - .start = evt2irq(0x22c0), - .end = evt2irq(0x22c0), + .start = gic_spi(48), + .end = gic_spi(48), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-5 */ - .start = evt2irq(0x2200), - .end = evt2irq(0x22a0), + .start = gic_spi(42), + .end = gic_spi(47), .flags = IORESOURCE_IRQ, }, }; @@ -677,8 +802,8 @@ static struct resource r8a7740_usb_dma_resources[] = { }, { /* IRQ for channels */ - .start = evt2irq(0x0a00), - .end = evt2irq(0x0a00), + .start = gic_spi(49), + .end = gic_spi(49), .flags = IORESOURCE_IRQ, }, }; @@ -702,8 +827,8 @@ static struct resource i2c0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = intcs_evt2irq(0xe00), - .end = intcs_evt2irq(0xe60), + .start = gic_spi(201), + .end = gic_spi(204), .flags = IORESOURCE_IRQ, }, }; @@ -716,8 +841,8 @@ static struct resource i2c1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = evt2irq(0x780), /* IIC1_ALI1 */ - .end = evt2irq(0x7e0), /* IIC1_DTEI1 */ + .start = gic_spi(70), /* IIC1_ALI1 */ + .end = gic_spi(73), /* IIC1_DTEI1 */ .flags = IORESOURCE_IRQ, }, }; @@ -738,8 +863,8 @@ static struct platform_device i2c1_device = { static struct resource pmu_resources[] = { [0] = { - .start = evt2irq(0x19a0), - .end = evt2irq(0x19a0), + .start = gic_spi(83), + .end = gic_spi(83), .flags = IORESOURCE_IRQ, }, }; @@ -904,7 +1029,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") .map_io = r8a7740_map_io, .init_early = r8a7740_add_early_devices_dt, .init_irq = r8a7740_init_irq, - .handle_irq = shmobile_handle_irq_intc, .init_machine = r8a7740_add_standard_devices_dt, .init_time = shmobile_timer_init, .dt_compat = r8a7740_boards_compat_dt, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index 214788c4a606..2b528280e3c1 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -2545,38 +2545,38 @@ static struct pinmux_data_reg pinmux_data_regs[] = { }; static struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */ - PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */ - PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */ - PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */ - PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */ - PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */ - PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */ - PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */ - PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */ - PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */ - PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */ - PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */ - PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */ - PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */ - PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */ - PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */ - PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */ - PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */ - PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */ - PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */ - PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */ - PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */ - PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */ - PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */ - PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */ - PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */ - PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */ - PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */ - PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */ - PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */ - PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */ - PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */ + PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */ + PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */ + PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */ + PINMUX_IRQ(irq_pin(3), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */ + PINMUX_IRQ(irq_pin(4), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */ + PINMUX_IRQ(irq_pin(5), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */ + PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */ + PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */ + PINMUX_IRQ(irq_pin(8), GPIO_PORT119), /* IRQ8A */ + PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */ + PINMUX_IRQ(irq_pin(10), GPIO_PORT19), /* IRQ10A */ + PINMUX_IRQ(irq_pin(11), GPIO_PORT104), /* IRQ11A */ + PINMUX_IRQ(irq_pin(12), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */ + PINMUX_IRQ(irq_pin(13), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */ + PINMUX_IRQ(irq_pin(14), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */ + PINMUX_IRQ(irq_pin(15), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */ + PINMUX_IRQ(irq_pin(16), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */ + PINMUX_IRQ(irq_pin(17), GPIO_PORT69), /* IRQ17A */ + PINMUX_IRQ(irq_pin(18), GPIO_PORT70), /* IRQ18A */ + PINMUX_IRQ(irq_pin(19), GPIO_PORT71), /* IRQ19A */ + PINMUX_IRQ(irq_pin(20), GPIO_PORT67), /* IRQ20A */ + PINMUX_IRQ(irq_pin(21), GPIO_PORT202), /* IRQ21A */ + PINMUX_IRQ(irq_pin(22), GPIO_PORT95), /* IRQ22A */ + PINMUX_IRQ(irq_pin(23), GPIO_PORT96), /* IRQ23A */ + PINMUX_IRQ(irq_pin(24), GPIO_PORT180), /* IRQ24A */ + PINMUX_IRQ(irq_pin(25), GPIO_PORT38), /* IRQ25A */ + PINMUX_IRQ(irq_pin(26), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */ + PINMUX_IRQ(irq_pin(27), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */ + PINMUX_IRQ(irq_pin(28), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */ + PINMUX_IRQ(irq_pin(29), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */ + PINMUX_IRQ(irq_pin(30), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */ + PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */ }; struct sh_pfc_soc_info r8a7740_pinmux_info = { -- cgit v1.2.1 From fe7aa82d62d13d97c9a786707c467357cb8bddc3 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 7 Mar 2013 20:00:48 +0100 Subject: ARM: shmobile: sh73a0: add a TWD clock Add a TWD clock on sh73a0 for the smp_twd driver to properly update the clock's frequency upon cpufreq events. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh73a0.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 34b5c5ae4cbd..a57ec151674e 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -288,6 +288,20 @@ static struct clk div4_clks[DIV4_NR] = { [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0), }; +static unsigned long twd_recalc(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 4; +} + +static struct sh_clk_ops twd_clk_ops = { + .recalc = twd_recalc, +}; + +static struct clk twd_clk = { + .parent = &div4_clks[DIV4_Z], + .ops = &twd_clk_ops, +}; + enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, DIV6_FSIA, DIV6_FSIB, DIV6_SUB, @@ -482,6 +496,7 @@ static struct clk dsi1phy_clk = { static struct clk *late_main_clks[] = { &dsi0phy_clk, &dsi1phy_clk, + &twd_clk, }; enum { MSTP001, @@ -546,6 +561,7 @@ static struct clk mstp_clks[MSTP_NR] = { static struct clk_lookup lookups[] = { /* main clocks */ CLKDEV_CON_ID("r_clk", &r_clk), + CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */ /* DIV6 clocks */ CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), -- cgit v1.2.1 From 1f7ccd88717d993c5189280034f1d3b6b5af9693 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:55:07 -0700 Subject: ARM: shmobile: sh73a0: remove DIV4_ZT* clocks DIV4_ZT* clocks are for debugging and trace bus clock. It is not necessary to control it from Linux/Software. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh73a0.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index a57ec151674e..26a580324105 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -269,7 +269,7 @@ static struct clk_div4_table div4_table = { }; enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, - DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR }; + DIV4_Z, DIV4_ZX, DIV4_HP, DIV4_NR }; #define DIV4(_reg, _bit, _mask, _flags) \ SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags) @@ -282,8 +282,6 @@ static struct clk div4_clks[DIV4_NR] = { [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0), - [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0), - [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0), [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0), }; -- cgit v1.2.1 From b3186c68805911599cbacceae23f60debb5e2210 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:55:24 -0700 Subject: ARM: shmobile: sh7372: remove DIV4_ZT* clocks DIV4_ZT* clocks are for debugging and trace bus clock. It is not necessary to control it from Linux/Software. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh7372.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 45d21fe317f4..6c23e3f22d62 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -342,7 +342,7 @@ static struct clk_div4_table div4_table = { }; enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, - DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, + DIV4_ZX, DIV4_HP, DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_DDRP, DIV4_NR }; @@ -355,8 +355,6 @@ static struct clk div4_clks[DIV4_NR] = { [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0), - [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0), - [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0), [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0), [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0), [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0), @@ -516,8 +514,6 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]), - CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]), - CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]), CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]), CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]), -- cgit v1.2.1 From f5942c76217e3f4c2a62a72c9d64997b8765f9e2 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:55:41 -0700 Subject: ARM: shmobile: add struct clk_ratio and fixed ratio clock macro Renesas chip has many clocks inside, and some of them are using fixed ratio via parent clock. Current shmobile clock code is using own divX_recalc function and divX_clk_ops. This patch can reduce these code Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock.c | 13 ++++++++++ arch/arm/mach-shmobile/include/mach/clock.h | 39 +++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 arch/arm/mach-shmobile/include/mach/clock.h diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c index e816ca9bd213..ad7df629d995 100644 --- a/arch/arm/mach-shmobile/clock.c +++ b/arch/arm/mach-shmobile/clock.c @@ -23,6 +23,19 @@ #include #include #include +#include +#include + +unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk) +{ + struct clk_ratio *p = clk->priv; + + return clk->parent->rate / p->div * p->mul; +}; + +struct sh_clk_ops shmobile_fixed_ratio_clk_ops = { + .recalc = shmobile_fixed_ratio_clk_recalc, +}; int __init shmobile_clk_init(void) { diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h new file mode 100644 index 000000000000..76ac61292e48 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/clock.h @@ -0,0 +1,39 @@ +#ifndef CLOCK_H +#define CLOCK_H + +unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk); +extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops; + +/* clock ratio */ +struct clk_ratio { + int mul; + int div; +}; + +#define SH_CLK_RATIO(name, m, d) \ +static struct clk_ratio name ##_ratio = { \ + .mul = m, \ + .div = d, \ +} + +#define SH_FIXED_RATIO_CLKg(name, p, r) \ +struct clk name = { \ + .parent = &p, \ + .ops = &shmobile_fixed_ratio_clk_ops,\ + .priv = &r ## _ratio, \ +} + +#define SH_FIXED_RATIO_CLK(name, p, r) \ +static SH_FIXED_RATIO_CLKg(name, p, r); + +#define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \ + SH_CLK_RATIO(name, m, d); \ + SH_FIXED_RATIO_CLK(name, p, name); + +#define SH_CLK_SET_RATIO(p, m, d) \ +{ \ + (p)->mul = m; \ + (p)->div = d; \ +} + +#endif -- cgit v1.2.1 From 99fb32b88be4e9b12c44f61b613a0936a62454b7 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:55:54 -0700 Subject: ARM: shmobile: sh7372: use fixed ratio clock Current clock-sh7372 is using own implement for each divX clocks. This patch switches to use fixed ratio clock, and was tesed on mackerel board. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh7372.c | 44 ++++++----------------------------- 1 file changed, 7 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 6c23e3f22d62..7e105932c09d 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -21,6 +21,7 @@ #include #include #include +#include #include /* SH7372 registers */ @@ -83,39 +84,12 @@ struct clk sh7372_extal2_clk = { .rate = 48000000, }; -/* A fixed divide-by-2 block */ -static unsigned long div2_recalc(struct clk *clk) -{ - return clk->parent->rate / 2; -} - -static struct sh_clk_ops div2_clk_ops = { - .recalc = div2_recalc, -}; +SH_CLK_RATIO(div2, 1, 2); -/* Divide dv_clki by two */ -struct clk sh7372_dv_clki_div2_clk = { - .ops = &div2_clk_ops, - .parent = &sh7372_dv_clki_clk, -}; - -/* Divide extal1 by two */ -static struct clk extal1_div2_clk = { - .ops = &div2_clk_ops, - .parent = &sh7372_extal1_clk, -}; - -/* Divide extal2 by two */ -static struct clk extal2_div2_clk = { - .ops = &div2_clk_ops, - .parent = &sh7372_extal2_clk, -}; - -/* Divide extal2 by four */ -static struct clk extal2_div4_clk = { - .ops = &div2_clk_ops, - .parent = &extal2_div2_clk, -}; +SH_FIXED_RATIO_CLKg(sh7372_dv_clki_div2_clk, sh7372_dv_clki_clk, div2); +SH_FIXED_RATIO_CLK(extal1_div2_clk, sh7372_extal1_clk, div2); +SH_FIXED_RATIO_CLK(extal2_div2_clk, sh7372_extal2_clk, div2); +SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_div2_clk, div2); /* PLLC0 and PLLC1 */ static unsigned long pllc01_recalc(struct clk *clk) @@ -147,10 +121,7 @@ static struct clk pllc1_clk = { }; /* Divide PLLC1 by two */ -static struct clk pllc1_div2_clk = { - .ops = &div2_clk_ops, - .parent = &pllc1_clk, -}; +SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2); /* PLLC2 */ @@ -650,5 +621,4 @@ void __init sh7372_clock_init(void) shmobile_clk_init(); else panic("failed to setup sh7372 clocks\n"); - } -- cgit v1.2.1 From 891cab3e7a71365eb8c79098e487b8f2056a1a73 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:56:14 -0700 Subject: ARM: shmobile: sh73a0: use fixed ratio clock Current clock-sh73a0 is using own implement for each divX clocks. This patch switches to use fixed ratio clock, and was tesed on kzm9g board. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh73a0.c | 72 ++++++----------------------------- 1 file changed, 12 insertions(+), 60 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 26a580324105..784fbaa4cc55 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #define FRQCRA IOMEM(0xe6150000) @@ -83,61 +84,16 @@ struct clk sh73a0_extal2_clk = { .rate = 48000000, }; -/* A fixed divide-by-2 block */ -static unsigned long div2_recalc(struct clk *clk) -{ - return clk->parent->rate / 2; -} - -static struct sh_clk_ops div2_clk_ops = { - .recalc = div2_recalc, -}; - -static unsigned long div7_recalc(struct clk *clk) -{ - return clk->parent->rate / 7; -} - -static struct sh_clk_ops div7_clk_ops = { - .recalc = div7_recalc, -}; - -static unsigned long div13_recalc(struct clk *clk) -{ - return clk->parent->rate / 13; -} - -static struct sh_clk_ops div13_clk_ops = { - .recalc = div13_recalc, -}; - -/* Divide extal1 by two */ -static struct clk extal1_div2_clk = { - .ops = &div2_clk_ops, - .parent = &sh73a0_extal1_clk, -}; - -/* Divide extal2 by two */ -static struct clk extal2_div2_clk = { - .ops = &div2_clk_ops, - .parent = &sh73a0_extal2_clk, -}; - static struct sh_clk_ops main_clk_ops = { .recalc = followparent_recalc, }; /* Main clock */ static struct clk main_clk = { + /* .parent wll be set on sh73a0_clock_init() */ .ops = &main_clk_ops, }; -/* Divide Main clock by two */ -static struct clk main_div2_clk = { - .ops = &div2_clk_ops, - .parent = &main_clk, -}; - /* PLL0, PLL1, PLL2, PLL3 */ static unsigned long pll_recalc(struct clk *clk) { @@ -193,21 +149,17 @@ static struct clk pll3_clk = { .enable_bit = 3, }; -/* Divide PLL */ -static struct clk pll1_div2_clk = { - .ops = &div2_clk_ops, - .parent = &pll1_clk, -}; - -static struct clk pll1_div7_clk = { - .ops = &div7_clk_ops, - .parent = &pll1_clk, -}; +/* A fixed divide block */ +SH_CLK_RATIO(div2, 1, 2); +SH_CLK_RATIO(div7, 1, 7); +SH_CLK_RATIO(div13, 1, 13); -static struct clk pll1_div13_clk = { - .ops = &div13_clk_ops, - .parent = &pll1_clk, -}; +SH_FIXED_RATIO_CLK(extal1_div2_clk, sh73a0_extal1_clk, div2); +SH_FIXED_RATIO_CLK(extal2_div2_clk, sh73a0_extal2_clk, div2); +SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2); +SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); +SH_FIXED_RATIO_CLK(pll1_div7_clk, pll1_clk, div7); +SH_FIXED_RATIO_CLK(pll1_div13_clk, pll1_clk, div13); /* External input clock */ struct clk sh73a0_extcki_clk = { -- cgit v1.2.1 From 5d14ff082badf94c5f5eaf9bc3f53075792c4f44 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:56:40 -0700 Subject: ARM: shmobile: r8a7740: tidyup comment/implementation mismatch Current clock-r8a7740's DIV4/DIV6/MSTP implemented area and its comment are mismatching. This patch tidyup its comment/implementation area. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7740.c | 60 ++++++++++++++++++---------------- 1 file changed, 31 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index 1feb9a2286a8..161e128e2157 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -323,6 +323,7 @@ struct clk *main_clks[] = { &fsibck_clk, }; +/* DIV4 clocks */ static void div4_kick(struct clk *clk) { unsigned long value; @@ -346,6 +347,26 @@ static struct clk_div4_table div4_table = { .kick = div4_kick, }; +enum { + DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP, + DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP, + DIV4_NR +}; + +struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0), + [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0), + [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0), + [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0), + [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0), + [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0), + [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0), +}; + /* DIV6 reparent */ enum { DIV6_HDMI, @@ -391,6 +412,16 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2), }; +/* DIV6 clocks */ +enum { + DIV6_SUB, + DIV6_NR +}; + +static struct clk div6_clks[DIV6_NR] = { + [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0), +}; + /* HDMI1/2 clock */ static unsigned long hdmi12_recalc(struct clk *clk) { @@ -455,35 +486,6 @@ static struct clk fsidivs[] = { }; /* MSTP */ -enum { - DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP, - DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP, - DIV4_NR -}; - -struct clk div4_clks[DIV4_NR] = { - [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0), - [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0), - [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0), - [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0), - [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0), - [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0), - [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0), -}; - -enum { - DIV6_SUB, - DIV6_NR -}; - -static struct clk div6_clks[DIV6_NR] = { - [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0), -}; - enum { MSTP128, MSTP127, MSTP125, MSTP116, MSTP111, MSTP100, MSTP117, -- cgit v1.2.1 From 10d6db2ba2a68fd7d5639ce4f422ec9dff2af0e7 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:56:57 -0700 Subject: ARM: shmobile: r8a7740: use fixed ratio clock Current clock-r8a7740 is using own implement for each divX clocks. This patch switches to use fixed ratio clock, and was tesed on armadillo board. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7740.c | 54 ++++++---------------------------- 1 file changed, 9 insertions(+), 45 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index 161e128e2157..c0d39aa6de50 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -97,42 +98,13 @@ static struct clk dv_clk = { .rate = 27000000, }; -static unsigned long div_recalc(struct clk *clk) -{ - return clk->parent->rate / (int)(clk->priv); -} - -static struct sh_clk_ops div_clk_ops = { - .recalc = div_recalc, -}; +SH_CLK_RATIO(div2, 1, 2); +SH_CLK_RATIO(div1k, 1, 1024); -/* extal1 / 2 */ -static struct clk extal1_div2_clk = { - .ops = &div_clk_ops, - .priv = (void *)2, - .parent = &extal1_clk, -}; - -/* extal1 / 1024 */ -static struct clk extal1_div1024_clk = { - .ops = &div_clk_ops, - .priv = (void *)1024, - .parent = &extal1_clk, -}; - -/* extal1 / 2 / 1024 */ -static struct clk extal1_div2048_clk = { - .ops = &div_clk_ops, - .priv = (void *)1024, - .parent = &extal1_div2_clk, -}; - -/* extal2 / 2 */ -static struct clk extal2_div2_clk = { - .ops = &div_clk_ops, - .priv = (void *)2, - .parent = &extal2_clk, -}; +SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2); +SH_FIXED_RATIO_CLK(extal1_div1024_clk, extal1_clk, div1k); +SH_FIXED_RATIO_CLK(extal1_div2048_clk, extal1_div2_clk, div1k); +SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2); static struct sh_clk_ops followparent_clk_ops = { .recalc = followparent_recalc, @@ -143,11 +115,7 @@ static struct clk system_clk = { .ops = &followparent_clk_ops, }; -static struct clk system_div2_clk = { - .ops = &div_clk_ops, - .priv = (void *)2, - .parent = &system_clk, -}; +SH_FIXED_RATIO_CLK(system_div2_clk, system_clk, div2); /* r_clk */ static struct clk r_clk = { @@ -184,11 +152,7 @@ static struct clk pllc1_clk = { }; /* PLLC1 / 2 */ -static struct clk pllc1_div2_clk = { - .ops = &div_clk_ops, - .priv = (void *)2, - .parent = &pllc1_clk, -}; +SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2); /* USB clock */ /* -- cgit v1.2.1 From ec0728d67985690f329592e68f0f1fe1f2388e70 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 27 Mar 2013 00:57:38 -0700 Subject: ARM: shmobile: r8a7779: remove DIV4 clocks and use fixed ratio clock R-Car H1 has many clocks, and it is possible to read/use clock ratio of these clocks from FRQMRx as DIV4 clocks. But, these ratio are fixed value and these are decided by MD pin status. This means that we can use fixed ratio clock via MD pin status, instead of DIV4 clocks. This patch reads MD pin status, and sets PLLA clock (= root clock), and used fixed ratio clock for other clocks. It was tesed on marzen board. Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7779.c | 196 ++++++++++++++++++--------------- 1 file changed, 109 insertions(+), 87 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index d9edeaf66007..7d86bfbb5b06 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -17,13 +17,17 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#include #include #include #include #include #include +#include #include +#define MD(nr) BIT(nr) + #define FRQMR IOMEM(0xffc80014) #define MSTPCR0 IOMEM(0xffc80030) #define MSTPCR1 IOMEM(0xffc80034) @@ -36,6 +40,9 @@ #define MSTPCR6 IOMEM(0xffc80058) #define MSTPCR7 IOMEM(0xffc80040) +#define MODEMR 0xffcc0020 + + /* ioremap() through clock mapping mandatory to avoid * collision with ARM coherent DMA virtual memory range. */ @@ -50,40 +57,39 @@ static struct clk_mapping cpg_mapping = { * from the platform code. */ static struct clk plla_clk = { - .rate = 1500000000, + /* .rate will be updated on r8a7779_clock_init() */ .mapping = &cpg_mapping, }; +/* + * clock ratio of these clock will be updated + * on r8a7779_clock_init() + */ +SH_FIXED_RATIO_CLK_SET(clkz_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clkzs_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clki_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clks_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clks1_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clks3_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clks4_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clkb_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clkout_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clkp_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(clkg_clk, plla_clk, 1, 1); + static struct clk *main_clks[] = { &plla_clk, -}; - -static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 }; - -static struct clk_div_mult_table div4_div_mult_table = { - .divisors = divisors, - .nr_divisors = ARRAY_SIZE(divisors), -}; - -static struct clk_div4_table div4_table = { - .div_mult_table = &div4_div_mult_table, -}; - -enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR }; - -static struct clk div4_clks[DIV4_NR] = { - [DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20, - 0x0018, CLK_ENABLE_ON_INIT), - [DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16, - 0x0700, CLK_ENABLE_ON_INIT), - [DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12, - 0x0040, CLK_ENABLE_ON_INIT), - [DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8, - 0x0010, CLK_ENABLE_ON_INIT), - [DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4, - 0x0060, CLK_ENABLE_ON_INIT), - [DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0, - 0x0300, CLK_ENABLE_ON_INIT), + &clkz_clk, + &clkzs_clk, + &clki_clk, + &clks_clk, + &clks1_clk, + &clks3_clk, + &clks4_clk, + &clkb_clk, + &clkout_clk, + &clkp_clk, + &clkg_clk, }; enum { MSTP323, MSTP322, MSTP321, MSTP320, @@ -96,52 +102,28 @@ enum { MSTP323, MSTP322, MSTP321, MSTP320, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { - [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */ - [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ - [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ - [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ - [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */ - [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1, 3, 0), /* DU */ - [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ - [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */ - [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */ - [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */ - [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */ - [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), /* I2C3 */ - [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */ - [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */ - [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */ - [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */ - [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */ - [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */ - [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */ - [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */ - [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */ - [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR0, 7, 0), /* HSPI */ -}; - -static unsigned long mul4_recalc(struct clk *clk) -{ - return clk->parent->rate * 4; -} - -static struct sh_clk_ops mul4_clk_ops = { - .recalc = mul4_recalc, -}; - -struct clk clkz_clk = { - .ops = &mul4_clk_ops, - .parent = &div4_clks[DIV4_S], -}; - -struct clk clkzs_clk = { - /* clks x 4 / 4 = clks */ - .parent = &div4_clks[DIV4_S], -}; - -static struct clk *late_main_clks[] = { - &clkz_clk, - &clkzs_clk, + [MSTP323] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 23, 0), /* SDHI0 */ + [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */ + [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */ + [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */ + [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */ + [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */ + [MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 1, 0), /* USB2 */ + [MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 0, 0), /* USB0/1 */ + [MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */ + [MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */ + [MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */ + [MSTP027] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 27, 0), /* I2C3 */ + [MSTP026] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 26, 0), /* SCIF0 */ + [MSTP025] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 25, 0), /* SCIF1 */ + [MSTP024] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 24, 0), /* SCIF2 */ + [MSTP023] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 23, 0), /* SCIF3 */ + [MSTP022] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 22, 0), /* SCIF4 */ + [MSTP021] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 21, 0), /* SCIF5 */ + [MSTP016] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 16, 0), /* TMU0 */ + [MSTP015] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 15, 0), /* TMU1 */ + [MSTP014] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 14, 0), /* TMU2 */ + [MSTP007] = SH_CLK_MSTP32(&clks_clk, MSTPCR0, 7, 0), /* HSPI */ }; static struct clk_lookup lookups[] = { @@ -151,12 +133,12 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("clkzs_clk", &clkzs_clk), /* DIV4 clocks */ - CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]), - CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]), - CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]), - CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]), - CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]), - CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + CLKDEV_CON_ID("shyway_clk", &clks_clk), + CLKDEV_CON_ID("bus_clk", &clkout_clk), + CLKDEV_CON_ID("shyway4_clk", &clks4_clk), + CLKDEV_CON_ID("shyway3_clk", &clks3_clk), + CLKDEV_CON_ID("shyway1_clk", &clks1_clk), + CLKDEV_CON_ID("peripheral_clk", &clkp_clk), /* MSTP32 clocks */ CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ @@ -190,20 +172,60 @@ static struct clk_lookup lookups[] = { void __init r8a7779_clock_init(void) { + void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); + u32 mode; int k, ret = 0; + BUG_ON(!modemr); + mode = ioread32(modemr); + iounmap(modemr); + + if (mode & MD(1)) { + plla_clk.rate = 1500000000; + + SH_CLK_SET_RATIO(&clkz_clk_ratio, 2, 3); + SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 6); + SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2); + SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 6); + SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 12); + SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8); + SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16); + SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 24); + SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24); + if (mode & MD(2)) { + SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 36); + SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 36); + } else { + SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24); + SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24); + } + } else { + plla_clk.rate = 1600000000; + + SH_CLK_SET_RATIO(&clkz_clk_ratio, 1, 2); + SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 8); + SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2); + SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 8); + SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 16); + SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8); + SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16); + SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 32); + SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24); + if (mode & MD(2)) { + SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 32); + SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 32); + } else { + SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24); + SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24); + } + } + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); - if (!ret) - ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); - if (!ret) ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); - for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) - ret = clk_register(late_main_clks[k]); - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); if (!ret) -- cgit v1.2.1 From daf9aa98293528abcf24b015ae8aa6e075d37298 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 28 Mar 2013 01:48:19 -0700 Subject: ARM: shmobile: sh7372: move global functions to sh7372.h There is no reason each CPU's own function has to exist in common.h. sh7372_xxx() go to sh7372.h Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 15 --------------- arch/arm/mach-shmobile/include/mach/sh7372.h | 12 ++++++++++++ 2 files changed, 12 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 03f73def2fc6..d01a5511a5ac 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -19,21 +19,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); -extern void sh7372_init_irq(void); -extern void sh7372_map_io(void); -extern void sh7372_earlytimer_init(void); -extern void sh7372_add_early_devices(void); -extern void sh7372_add_standard_devices(void); -extern void sh7372_add_early_devices_dt(void); -extern void sh7372_add_standard_devices_dt(void); -extern void sh7372_clock_init(void); -extern void sh7372_pinmux_init(void); -extern void sh7372_pm_init(void); -extern void sh7372_resume_core_standby_sysc(void); -extern int sh7372_do_idle_sysc(unsigned long sleep_mode); -extern struct clk sh7372_extal1_clk; -extern struct clk sh7372_extal2_clk; - extern void sh73a0_init_delay(void); extern void sh73a0_init_irq(void); extern void sh73a0_init_irq_dt(void); diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index b582facc1cf6..f0ea60d6648a 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -478,6 +478,18 @@ extern struct clk sh7372_dv_clki_clk; extern struct clk sh7372_dv_clki_div2_clk; extern struct clk sh7372_pllc2_clk; +extern void sh7372_init_irq(void); +extern void sh7372_map_io(void); +extern void sh7372_earlytimer_init(void); +extern void sh7372_add_early_devices(void); +extern void sh7372_add_standard_devices(void); +extern void sh7372_add_early_devices_dt(void); +extern void sh7372_add_standard_devices_dt(void); +extern void sh7372_clock_init(void); +extern void sh7372_pinmux_init(void); +extern void sh7372_pm_init(void); +extern void sh7372_resume_core_standby_sysc(void); +extern int sh7372_do_idle_sysc(unsigned long sleep_mode); extern void sh7372_intcs_suspend(void); extern void sh7372_intcs_resume(void); extern void sh7372_intca_suspend(void); -- cgit v1.2.1 From 014f93a08361282a0af0dd155c3b434431ea36df Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 28 Mar 2013 01:48:30 -0700 Subject: ARM: shmobile: sh73a0: move global functions to sh73a0.h There is no reason each CPU's own function has to exist in common.h. sh73a0_xxx() go to sh73a0.h Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 16 ---------------- arch/arm/mach-shmobile/include/mach/sh73a0.h | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index d01a5511a5ac..48eeca9d25a3 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -19,22 +19,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); -extern void sh73a0_init_delay(void); -extern void sh73a0_init_irq(void); -extern void sh73a0_init_irq_dt(void); -extern void sh73a0_map_io(void); -extern void sh73a0_earlytimer_init(void); -extern void sh73a0_add_early_devices(void); -extern void sh73a0_add_standard_devices(void); -extern void sh73a0_add_standard_devices_dt(void); -extern void sh73a0_clock_init(void); -extern void sh73a0_pinmux_init(void); -extern void sh73a0_pm_init(void); -extern struct clk sh73a0_extal1_clk; -extern struct clk sh73a0_extal2_clk; -extern struct clk sh73a0_extcki_clk; -extern struct clk sh73a0_extalr_clk; - extern void r8a7740_meram_workaround(void); extern void r8a7740_init_irq(void); extern void r8a7740_map_io(void); diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h index 606d31d02a4e..936da1b4a9c5 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -557,6 +557,21 @@ enum { #define SH73A0_PINT0_IRQ(irq) ((irq) + 700) #define SH73A0_PINT1_IRQ(irq) ((irq) + 732) +extern void sh73a0_init_delay(void); +extern void sh73a0_init_irq(void); +extern void sh73a0_init_irq_dt(void); +extern void sh73a0_map_io(void); +extern void sh73a0_earlytimer_init(void); +extern void sh73a0_add_early_devices(void); +extern void sh73a0_add_standard_devices(void); +extern void sh73a0_add_standard_devices_dt(void); +extern void sh73a0_clock_init(void); +extern void sh73a0_pinmux_init(void); +extern void sh73a0_pm_init(void); +extern struct clk sh73a0_extal1_clk; +extern struct clk sh73a0_extal2_clk; +extern struct clk sh73a0_extcki_clk; +extern struct clk sh73a0_extalr_clk; extern struct smp_operations sh73a0_smp_ops; #endif /* __ASM_SH73A0_H__ */ -- cgit v1.2.1 From f96c764dac2c2761fc05164255c0ed689b8ac496 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 28 Mar 2013 01:49:15 -0700 Subject: ARM: shmobile: r8a7740: move global functions to r8a7740.h There is no reason each CPU's own function has to exist in common.h. r8a7740_xxx() go to r8a7740.h Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 9 --------- arch/arm/mach-shmobile/include/mach/r8a7740.h | 9 +++++++++ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 48eeca9d25a3..4d5410de00d6 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -19,15 +19,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); -extern void r8a7740_meram_workaround(void); -extern void r8a7740_init_irq(void); -extern void r8a7740_map_io(void); -extern void r8a7740_add_early_devices(void); -extern void r8a7740_add_standard_devices(void); -extern void r8a7740_clock_init(u8 md_ck); -extern void r8a7740_pinmux_init(void); -extern void r8a7740_pm_init(void); - extern void r8a7779_init_delay(void); extern void r8a7779_init_irq(void); extern void r8a7779_init_irq_extpin(int irlm); diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h index 59d252f4cf97..5a879bbe145f 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7740.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h @@ -606,6 +606,15 @@ enum { SHDMA_SLAVE_USBHS_RX, }; +extern void r8a7740_meram_workaround(void); +extern void r8a7740_init_irq(void); +extern void r8a7740_map_io(void); +extern void r8a7740_add_early_devices(void); +extern void r8a7740_add_standard_devices(void); +extern void r8a7740_clock_init(u8 md_ck); +extern void r8a7740_pinmux_init(void); +extern void r8a7740_pm_init(void); + #ifdef CONFIG_PM extern void __init r8a7740_init_pm_domains(void); #else -- cgit v1.2.1 From 60e3a566897dcdd8621464ff46f4537903c2255a Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 28 Mar 2013 01:49:27 -0700 Subject: ARM: shmobile: r8a7779: move global functions to r8a7779.h There is no reason each CPU's own function has to exist in common.h. r8a7779_xxx() go to r8a7779.h Signed-off-by: Kuninori Morimoto Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 14 -------------- arch/arm/mach-shmobile/include/mach/r8a7779.h | 13 +++++++++++++ 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 4d5410de00d6..e002cfd9d2df 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -19,20 +19,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); -extern void r8a7779_init_delay(void); -extern void r8a7779_init_irq(void); -extern void r8a7779_init_irq_extpin(int irlm); -extern void r8a7779_init_irq_dt(void); -extern void r8a7779_map_io(void); -extern void r8a7779_earlytimer_init(void); -extern void r8a7779_add_early_devices(void); -extern void r8a7779_add_standard_devices(void); -extern void r8a7779_add_standard_devices_dt(void); -extern void r8a7779_clock_init(void); -extern void r8a7779_pinmux_init(void); -extern void r8a7779_pm_init(void); -extern void r8a7779_register_twd(void); - #ifdef CONFIG_SUSPEND int shmobile_suspend_init(void); #else diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index 8ab0cd6ad6b0..af38750f38f7 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -343,6 +343,19 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d) return &container_of(d, struct r8a7779_pm_domain, genpd)->ch; } +extern void r8a7779_init_delay(void); +extern void r8a7779_init_irq(void); +extern void r8a7779_init_irq_extpin(int irlm); +extern void r8a7779_init_irq_dt(void); +extern void r8a7779_map_io(void); +extern void r8a7779_earlytimer_init(void); +extern void r8a7779_add_early_devices(void); +extern void r8a7779_add_standard_devices(void); +extern void r8a7779_add_standard_devices_dt(void); +extern void r8a7779_clock_init(void); +extern void r8a7779_pinmux_init(void); +extern void r8a7779_pm_init(void); +extern void r8a7779_register_twd(void); extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch); extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch); -- cgit v1.2.1 From 0468b2d6b6ae71699c22e67701e23d6ca8ff3046 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 Mar 2013 00:49:34 +0900 Subject: ARM: shmobile: Initial r8a7790 SoC support Add initial support for the r8a7790 SoC including: - Single Cortex-A15 CPU Core - GIC - Architecture timer No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 54 ++++++++++++++++++++++++ arch/arm/mach-shmobile/Kconfig | 7 +++ arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/clock-r8a7790.c | 61 +++++++++++++++++++++++++++ arch/arm/mach-shmobile/include/mach/r8a7790.h | 7 +++ arch/arm/mach-shmobile/setup-r8a7790.c | 51 ++++++++++++++++++++++ 6 files changed, 181 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7790.dtsi create mode 100644 arch/arm/mach-shmobile/clock-r8a7790.c create mode 100644 arch/arm/mach-shmobile/include/mach/r8a7790.h create mode 100644 arch/arm/mach-shmobile/setup-r8a7790.c diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi new file mode 100644 index 000000000000..1c58ffb6cccf --- /dev/null +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -0,0 +1,54 @@ +/* + * Device Tree Source for the r8a7790 SoC + * + * Copyright (C) 2013 Renesas Solutions Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "renesas,r8a7790"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1300000000>; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xf1001000 0x1000>, + <0xf1002000 0x1000>, + <0xf1004000 0x2000>, + <0xf1006000 0x2000>; + interrupts = <1 9 0xf04>; + + gic-cpuif@4 { + compatible = "arm,gic-cpuif"; + cpuif-id = <4>; + cpu = <&cpu0>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; +}; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index d569c34b1c86..749dfb4c63c0 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -51,6 +51,13 @@ config ARCH_R8A7779 select USB_ARCH_HAS_OHCI select RENESAS_INTC_IRQPIN +config ARCH_R8A7790 + bool "R-Car H2 (R8A77900)" + select ARM_GIC + select CPU_V7 + select ARM_ARCH_TIMER + select SH_CLK_CPG + config ARCH_EMEV2 bool "Emma Mobile EV2" select ARCH_WANT_OPTIONAL_GPIOLIB diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 2d42de46db8d..709b9b421f93 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o +obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o clock-r8a7790.o obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o # SMP objects diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c new file mode 100644 index 000000000000..6869798effa3 --- /dev/null +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -0,0 +1,61 @@ +/* + * r8a7790 clock framework support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include + +#define CPG_BASE 0xe6150000 +#define CPG_LEN 0x1000 + +static struct clk_mapping cpg_mapping = { + .phys = CPG_BASE, + .len = CPG_LEN, +}; + +static struct clk *main_clks[] = { +}; + +enum { MSTP_NR }; +static struct clk mstp_clks[MSTP_NR] = { +}; + +static struct clk_lookup lookups[] = { +}; + +void __init r8a7790_clock_init(void) +{ + int k, ret = 0; + + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + + if (!ret) + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + if (!ret) + shmobile_clk_init(); + else + panic("failed to setup r8a7790 clocks\n"); +} diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h new file mode 100644 index 000000000000..f38ded61285f --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h @@ -0,0 +1,7 @@ +#ifndef __ASM_R8A7790_H__ +#define __ASM_R8A7790_H__ + +void r8a7790_add_standard_devices(void); +void r8a7790_clock_init(void); + +#endif /* __ASM_R8A7790_H__ */ diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c new file mode 100644 index 000000000000..af432ba11020 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -0,0 +1,51 @@ +/* + * r8a7790 processor support + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +void __init r8a7790_add_standard_devices(void) +{ +} + +#ifdef CONFIG_USE_OF +void __init r8a7790_add_standard_devices_dt(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char *r8a7790_boards_compat_dt[] __initdata = { + "renesas,r8a7790", + NULL, +}; + +DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") + .init_irq = irqchip_init, + .init_machine = r8a7790_add_standard_devices_dt, + .init_time = shmobile_timer_init, + .dt_compat = r8a7790_boards_compat_dt, +MACHINE_END +#endif /* CONFIG_USE_OF */ -- cgit v1.2.1 From 55d9fab280e6e587d634d2ec2effe94eabe90e9c Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 Mar 2013 00:49:44 +0900 Subject: ARM: shmobile: r8a7790 SCIF support Add SCIF serial port support to the r8a7790 SoC by adding platform devices for SCIFA0 -> SCIFA2 as well as SCIFB0 -> SCIFB2 and SCIF0 -> SCIF1 together with clock bindings. DT device description is excluded at this point since such bindings are still under development. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7790.c | 34 ++++++++++++++++++++- arch/arm/mach-shmobile/setup-r8a7790.c | 55 ++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index 6869798effa3..bad9bf2e34d6 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -27,19 +27,51 @@ #define CPG_BASE 0xe6150000 #define CPG_LEN 0x1000 +#define SMSTPCR2 0xe6150138 +#define SMSTPCR7 0xe615014c + static struct clk_mapping cpg_mapping = { .phys = CPG_BASE, .len = CPG_LEN, }; +static struct clk p_clk = { + .rate = 65000000, /* shortcut for now */ + .mapping = &cpg_mapping, +}; + +static struct clk mp_clk = { + .rate = 52000000, /* shortcut for now */ + .mapping = &cpg_mapping, +}; + static struct clk *main_clks[] = { + &p_clk, + &mp_clk, }; -enum { MSTP_NR }; +enum { MSTP721, MSTP720, + MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { + [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ + [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ + [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ + [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ + [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ + [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ }; static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), + CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), + CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), }; void __init r8a7790_clock_init(void) diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index af432ba11020..3bb5bf16000c 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -22,13 +22,68 @@ #include #include #include +#include #include #include #include #include +#define SCIF_COMMON(scif_type, baseaddr, irq) \ + .type = scif_type, \ + .mapbase = baseaddr, \ + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ + .irqs = SCIx_IRQ_MUXED(irq) + +#define SCIFA_DATA(index, baseaddr, irq) \ +[index] = { \ + SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ + .scbrr_algo_id = SCBRR_ALGO_4, \ + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ +} + +#define SCIFB_DATA(index, baseaddr, irq) \ +[index] = { \ + SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ + .scbrr_algo_id = SCBRR_ALGO_4, \ + .scscr = SCSCR_RE | SCSCR_TE, \ +} + +#define SCIF_DATA(index, baseaddr, irq) \ +[index] = { \ + SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ + .scbrr_algo_id = SCBRR_ALGO_2, \ + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ +} + +enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 }; + +static const struct plat_sci_port scif[] = { + SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ + SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ + SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ + SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ + SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ + SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ + SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ + SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ +}; + +static inline void r8a7790_register_scif(int idx) +{ + platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], + sizeof(struct plat_sci_port)); +} + void __init r8a7790_add_standard_devices(void) { + r8a7790_register_scif(SCIFA0); + r8a7790_register_scif(SCIFA1); + r8a7790_register_scif(SCIFB0); + r8a7790_register_scif(SCIFB1); + r8a7790_register_scif(SCIFB2); + r8a7790_register_scif(SCIFA2); + r8a7790_register_scif(SCIF0); + r8a7790_register_scif(SCIF1); } #ifdef CONFIG_USE_OF -- cgit v1.2.1 From 8f5ec0a57ef503e7609d763cadba55f12b9486ce Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 Mar 2013 00:49:54 +0900 Subject: ARM: shmobile: r8a7790 IRQC support Add IRQC interrupt controller support to r8a7790 by hooking up a single IRQC instances to handle 4 external IRQ signals. The IRQC controller is tied to SPIs of the GIC. On r8a7790 the external IRQ pins routing is handled by the PFC which is excluded from this patch. Both platform devices and DT devices are added in this patch. The platform device versions are used to provide a static interrupt map configuration for board code written in C. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 9 +++++++++ arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/setup-r8a7790.c | 21 +++++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 1c58ffb6cccf..a1e0e0c64c3c 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -51,4 +51,13 @@ <1 11 0xf08>, <1 10 0xf08>; }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe61c0000 0x200>; + interrupt-parent = <&gic>; + interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; + }; }; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 749dfb4c63c0..ccaea6aecea0 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -57,6 +57,7 @@ config ARCH_R8A7790 select CPU_V7 select ARM_ARCH_TIMER select SH_CLK_CPG + select RENESAS_IRQC config ARCH_EMEV2 bool "Emma Mobile EV2" diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index 3bb5bf16000c..9b4ccd7b5031 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -74,6 +75,25 @@ static inline void r8a7790_register_scif(int idx) sizeof(struct plat_sci_port)); } +static struct renesas_irqc_config irqc0_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ +}; + +static struct resource irqc0_resources[] = { + DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ + DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ + DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ + DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ + DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ +}; + +#define r8a7790_register_irqc(idx) \ + platform_device_register_resndata(&platform_bus, "renesas_irqc", \ + idx, irqc##idx##_resources, \ + ARRAY_SIZE(irqc##idx##_resources), \ + &irqc##idx##_data, \ + sizeof(struct renesas_irqc_config)) + void __init r8a7790_add_standard_devices(void) { r8a7790_register_scif(SCIFA0); @@ -84,6 +104,7 @@ void __init r8a7790_add_standard_devices(void) r8a7790_register_scif(SCIFA2); r8a7790_register_scif(SCIF0); r8a7790_register_scif(SCIF1); + r8a7790_register_irqc(0); } #ifdef CONFIG_USE_OF -- cgit v1.2.1 From 69e351d029985a31abd41b2b8729788a01e8588d Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 Mar 2013 00:50:03 +0900 Subject: ARM: shmobile: r8a7790 PFC support Add a platform device for the r8a7790 PFC. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/include/mach/r8a7790.h | 1 + arch/arm/mach-shmobile/setup-r8a7790.c | 10 ++++++++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index ccaea6aecea0..ff674c5f2d03 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -53,6 +53,7 @@ config ARCH_R8A7779 config ARCH_R8A7790 bool "R-Car H2 (R8A77900)" + select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_GIC select CPU_V7 select ARM_ARCH_TIMER diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h index f38ded61285f..9bd6f5c894bb 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h @@ -3,5 +3,6 @@ void r8a7790_add_standard_devices(void); void r8a7790_clock_init(void); +void r8a7790_pinmux_init(void); #endif /* __ASM_R8A7790_H__ */ diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index 9b4ccd7b5031..481201a4f3f5 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -29,6 +29,16 @@ #include #include +static const struct resource pfc_resources[] = { + DEFINE_RES_MEM(0xe6060000, 0x250), +}; + +void __init r8a7790_pinmux_init(void) +{ + platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, + ARRAY_SIZE(pfc_resources)); +} + #define SCIF_COMMON(scif_type, baseaddr, irq) \ .type = scif_type, \ .mapbase = baseaddr, \ -- cgit v1.2.1 From 26a0d2d47f5bfb75cd14d961f9d825338d471317 Mon Sep 17 00:00:00 2001 From: Takashi Yoshii Date: Fri, 29 Mar 2013 16:45:56 +0900 Subject: ARM: shmobile: r8a73a4 SoC 64-bit DT support The r8a73a4 SoC supports LPAE and has memory window up to 0x2ffffffff. Convert to 64-bit addresses by enlarging #addr-cells and #size-cells to 2. Signed-off-by: Takashi Yoshii Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 7db5b504e64c..fde2a337d1ff 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -9,11 +9,11 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" - / { compatible = "renesas,r8a73a4"; interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; cpus { #address-cells = <1>; @@ -32,10 +32,10 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0xf1001000 0x1000>, - <0xf1002000 0x1000>, - <0xf1004000 0x2000>, - <0xf1006000 0x2000>; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; interrupts = <1 9 0xf04>; gic-cpuif@4 { @@ -57,7 +57,7 @@ compatible = "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; - reg = <0xe61c0000 0x200>; + reg = <0 0xe61c0000 0 0x200>; interrupt-parent = <&gic>; interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>, <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>, @@ -73,7 +73,7 @@ compatible = "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; - reg = <0xe61c0200 0x200>; + reg = <0 0xe61c0200 0 0x200>; interrupt-parent = <&gic>; interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>, <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>, @@ -86,8 +86,8 @@ thermal@e61f0000 { compatible = "renesas,rcar-thermal"; - reg = <0xe61f0000 0x14>, <0xe61f0100 0x38>, - <0xe61f0200 0x38>, <0xe61f0300 0x38>; + reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, + <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; interrupt-parent = <&gic>; interrupts = <0 69 4>; }; -- cgit v1.2.1 From 8585deb18580d04209a2986430aa0959ef38fce2 Mon Sep 17 00:00:00 2001 From: Takashi Yoshii Date: Fri, 29 Mar 2013 16:49:17 +0900 Subject: ARM: shmobile: r8a7790 SoC 64-bit DT support The r8a7790 SoC supports LPAE and has memory window up to 0x2ffffffff. Convert to 64-bit addresses by enlarging #addr-cells and #size-cells to 2. Signed-off-by: Takashi Yoshii Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index a1e0e0c64c3c..7a1711027e41 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -8,11 +8,11 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" - / { compatible = "renesas,r8a7790"; interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; cpus { #address-cells = <1>; @@ -31,10 +31,10 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0xf1001000 0x1000>, - <0xf1002000 0x1000>, - <0xf1004000 0x2000>, - <0xf1006000 0x2000>; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; interrupts = <1 9 0xf04>; gic-cpuif@4 { @@ -56,7 +56,7 @@ compatible = "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; - reg = <0xe61c0000 0x200>; + reg = <0 0xe61c0000 0 0x200>; interrupt-parent = <&gic>; interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; }; -- cgit v1.2.1