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* ASoC: Move register I/O code into a separate fileMark Brown2011-06-131-380/+0
| | | | | | | | | For clarity and to help ongoing refactoring in this area create a new file to contain the physical I/O functions, separating them out from the cache operations. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com>
* ASoC: Factor out redundant read() functionsMark Brown2011-06-131-44/+8
| | | | | | | | | We've got a whole bunch of functions which just call straight through to do_hw_read(). Simplify this situation by removing them and using hw_read() directly. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com>
* ASoC: Suppress restore of default register values for rbtree cache syncMark Brown2011-06-081-1/+6
| | | | | | | | | | | | | | Currently the rbtree code will write out the entire register map when doing a cache sync which is wasteful and will slow things down. Check to see if the value we're about to write is the default and don't bother restoring it if it is, either the value will have been retained or the device will have been reset and holds the value already. We should really store the defaults in the nodes but this resolves the immediate issue. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com>
* Merge branch 'for-3.0' into for-3.1Mark Brown2011-06-061-0/+3
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| * ASoC: Check for NULL register bank in snd_soc_get_cache_val()Mark Brown2011-06-061-0/+3
| | | | | | | | | | Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com>
* | Merge branch 'for-2.6.40' into for-2.6.41Mark Brown2011-05-301-126/+14
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| * ASoC: Reintroduce do_spi_write()Mark Brown2011-05-151-1/+15
| | | | | | | | | | | | | | | | | | There is an unfortunate difference in return values between spi_write() and i2c_master_send() so we need an adaptor function to translate. Reported-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com>
| * ASoC: Use spi_write() for SPI writesMark Brown2011-05-111-128/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | do_spi_write() is just an open coded copy of do_spi_write() so we can delete it and just call spi_write() directly. Indeed, as a result of recent refactoring all the SPI write functions are just very long wrappers around spi_write() which don't add anything except for some pointless copies so we can just use spi_write() as the hw_write operation directly. It should be as type safe to do this as it is to do the same thing with I2C and it saves us a bunch of code. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com>
| * ASoC: Remove byte swap in 4x12 SPI writeMark Brown2011-05-111-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | snd_soc_4_12_spi_write() contains a byte swap. Since this code was written for an Analog CODEC on a Blackfin reference board it appears that this is done because while Blackfin is little endian the CODEC is big endian (as are most CODECs). Push this up into the generic 4x12 write function and use cpu_to_be16() to do the byte swap so things are more regular and things work on both CPU endiannesses. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com>
| * ASoC: Don't squash 16x8 registers down to 8 bitsMark Brown2011-05-111-1/+0
| | | | | | | | | | | | | | | | Currently we'll force all registers to fit in 8 bits before passing down to the I/O function. Looks like a cut'n'paste bug. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com>
* | ASoC: Use explicit endianness conversion in snd_soc_16_8_write()Mark Brown2011-05-271-2/+2
| | | | | | | | | | Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com>
* | ASoC: Use cpu_to_be16() in 8x16 writeMark Brown2011-05-271-2/+2
| | | | | | | | | | Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com>
* | ASoC: Convert 7x9 write to use cpu_to_be16()Mark Brown2011-05-271-4/+3
| | | | | | | | | | | | | | Run the data through cpu_to_be16() so it's at least clear what we're up to. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com>
* | ASoC: Convert 16x16 write to use cpu_to_be16()Mark Brown2011-05-241-6/+4
| | | | | | | | | | | | | | Make it clear what we're doing. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com>
* | ASoC: soc-cache: Cache a pointer to the last accessed rbnodeDimitris Papastamos2011-05-201-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | Whenever we are doing a read or a write through the rbtree code, we'll cache a pointer to the rbnode. To avoid looking up the register everytime we do a read or a write, we first check if it can be found in the cached register block, otherwise we traverse the rbtree and finally cache the rbnode for future use. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* | ASoC: soc-cache: Block based rbtree compressionDimitris Papastamos2011-05-201-55/+177
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch prepares the ground for the actual rbtree optimization patch which will save a pointer to the last accessed rbnode that was used in either the read() or write() functions. Each rbnode manages a variable length block of registers. There can be no two nodes with overlapping blocks. Each block has a base register and a currently top register, all the other registers, if any, lie in between these two and in ascending order. The reasoning behind the construction of this rbtree is simple. In the snd_soc_rbtree_cache_init() function, we iterate over the register defaults provided by the driver. For each register value that is non-zero we insert it in the rbtree. In order to determine in which rbnode we need to add the register, we first look if there is another register already added that is adjacent to the one we are about to add. If that is the case we append it in that rbnode block, otherwise we create a new rbnode with a single register in its block and add it to the tree. In the next patch, where a cached rbnode is used by both the write() and the read() functions, we also check if the register we are about to add is in the cached rbnode (the least recently accessed one) and if so we append it in that rbnode block. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Allow codec->cache_bypass to be used with ↵Dimitris Papastamos2011-05-081-5/+6
| | | | | | | | | | | snd_soc_hw_bulk_write_raw() If we specifically want to write a block of data to the hw bypassing the cache, then allow this to happen inside snd_soc_hw_bulk_write_raw(). Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: remove unused commentLu Guanqun2011-04-201-1/+0
| | | | | | | | | `type` parameter is not longer used in `snd_soc_codec_set_cache_io`, so remove this line. Signed-off-by: Lu Guanqun <guanqun.lu@intel.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: Fix comment width in soc-cache.cMark Brown2011-04-051-4/+5
| | | | | | Lines should be less than 80 columns. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: Remove excessively verbose logging on I2C writeMark Brown2011-04-051-1/+0
| | | | | | We don't need to log every I2C transfer, and certainly not at error level. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: Fix to avoid compile errorSeungwhan Youn2011-04-051-0/+4
| | | | | | | | This patch fixes to avoid compile error when ASoC codec doesn't use I2C nor SPI on snd_soc_hw_bulk_write_raw(). Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Warn on syncing any non-writable registersDimitris Papastamos2011-03-311-0/+6
| | | | | | | | | | When syncing the cache, if the driver has given us a writable_register() callback, use it to check if we are syncing a non-writable register and if so warn the user. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Fix indentation issuesDimitris Papastamos2011-03-311-9/+9
| | | | | | Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: Add default snd_soc_default_writable_register() callbackDimitris Papastamos2011-03-261-0/+14
| | | | | | | | | | By using struct snd_soc_reg_access for the read/write/vol attributes of the registers, we provide callbacks that automatically determine whether a given register is readable/writable or volatile. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Return -ENOSYS instead of -EINVALDimitris Papastamos2011-03-261-5/+5
| | | | | | | | | | These functions fail with -EINVAL if the corresponding callbacks are not implemented. Change them to return -ENOSYS as it is more appropriate for unimplemented callbacks. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Factor-out the SPI write codeDimitris Papastamos2011-03-261-96/+30
| | | | | | | | | The handling of all snd_soc_x_y_spi_write() functions is similar. Create a separate function and update all callers to use it. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Factor-out the hw_read() specific codeDimitris Papastamos2011-03-261-96/+18
| | | | | | | | | The handling of all snd_soc_x_y_read() functions is similar. Factor it out into a separate function and update all callers. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Factor-out the hw_write() specific codeDimitris Papastamos2011-03-261-120/+33
| | | | | | | | | | The handling of all snd_soc_x_y_write() functions is similar. Factor it out into a separate function and update all functions to use it. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Introduce raw bulk write supportDimitris Papastamos2011-03-261-0/+39
| | | | | | | | | | | | As it has become more common to have to write firmware or similar large chunks of data to the hardware, add a function to perform raw bulk writes that bypass the cache. This only handles volatile registers as we should avoid getting out of sync with the actual cache. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Factor-out the I2C read codeDimitris Papastamos2011-03-261-68/+32
| | | | | | | | | The handling of all snd_soc_x_y_read_i2c() functions is similar. Make a generic I2C read function and update all callers to use it. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: dereferencing before checkingDan Carpenter2011-02-081-13/+12
| | | | | | | | | | | | | The patch c358e640a66 "ASoC: soc-cache: Add trace event for snd_soc_cache_sync()" introduced a dereference of "codec->cache_ops" before we had checked it for NULL. I pulled the check forward, and then pulled everything in an indent level. Signed-off-by: Dan Carpenter <error27@gmail.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Add trace event for snd_soc_cache_sync()Dimitris Papastamos2011-01-211-0/+10
| | | | | | | | | | This patch makes it easy to see when the syncing process begins and ends. You can also enable the snd_soc_reg_write tracepoint to see which registers are being synced. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Apply the cache_bypass optionDimitris Papastamos2011-01-201-0/+4
| | | | | | | | | | | Incorporate the use of the cache_bypass functionality in the syncing functions. The snd_soc_flat_cache_sync() need not be hooked as there is no performance benefit from using the cache_bypass option. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Introduce the cache_bypass optionDimitris Papastamos2011-01-201-12/+24
| | | | | | | | | | This is primarily needed to avoid writing back to the cache whenever we are syncing the cache with the hardware. This gives a performance benefit especially for large register maps. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Add support for default readable()/volatile() functionsDimitris Papastamos2011-01-131-0/+49
| | | | | | | | | | | | For common scenarios, device drivers can provide a table of all the registers that are at least either readable/writable/volatile. The idea is that if a register lookup fails, all of its read/write/vol members will be zero and will be treated as default. This also reduces the size of the register access array. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* Merge branch 'for-2.6.38' into for-2.6.39Mark Brown2011-01-131-1/+1
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| * ASoC: soc-cache: Fix invalid memory access during snd_soc_lzo_cache_sync()Dimitris Papastamos2011-01-111-1/+1
| | | | | | | | | | | | | | | | | | | | The size of the lzo syncing bitmap was incorrectly set to the size of the cache times the word size, however, the correct size is the size of the cache. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* | ASoC: soc-cache: Add reg_size as a member to snd_soc_codecDimitris Papastamos2011-01-121-18/+8
| | | | | | | | | | | | | | | | | | | | Simplify the use of reg_size, by calculating it once and storing it in the codec structure for later reference. The value of reg_size is reg_cache_size * reg_word_size. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* | ASoC: soc-cache: Ensure flat compression uses a copy of the defaults cacheDimitris Papastamos2011-01-121-12/+4
| | | | | | | | | | | | | | | | | | | | | | With the addition of the cache fallback functionality, it is necessary to ensure that if the register defaults cache was marked as __devinitconst and the LZO compression is not compiled in the kernel, the fallback to flat compression will still use a copy of the defaults cache. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* | ASoC: soc-cache: Clean up the cache manipulation codeDimitris Papastamos2011-01-111-148/+82
|/ | | | | | | | | Use Takashi's clean up code to make the cache manipulation code more readable. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: Make LZO cache compression optionalMark Brown2010-12-211-0/+4
| | | | | | | | | Make LZO cache compression optional as it pulls in the kernel wide LZO implementation and rbtree compression is generally more efficient for typical register maps, especially in terms of CPU performance. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
* ASoC: If we can't find a cache compression type default to flatMark Brown2010-12-211-3/+6
| | | | | | | | This makes it easier to make cache types build time configurable as we don't have a hard dependency on a given cache being built in. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
* ASoC: soc-cache: A few minor stylistic changesDimitris Papastamos2010-12-141-7/+7
| | | | | | | | | Remove redundant parentheses/spaces in the use of the sizeof operator. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Add optional cache name member to snd_soc_cache_opsDimitris Papastamos2010-12-061-2/+16
| | | | | | | | | | | Added an optional name member to snd_soc_cache_ops to enable more sensible diagnostic messages during cache init, exit and sync. Remove redundant newline in source code. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: Constify struct snd_soc_codec_driverMark Brown2010-12-031-6/+6
| | | | | | | | Allow the CODEC driver structure to be marked const by making all the APIs that use it do so. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
* ASoC: soc-cache: Use reg_def_copy instead of reg_cache_defaultDimitris Papastamos2010-12-031-12/+24
| | | | | | | | | | | | Make sure to use codec->reg_def_copy instead of codec_drv->reg_cache_default wherever necessary. This change is necessary because in the next patch we move the cache initialization code outside snd_soc_register_codec() and by that time any data marked as __devinitconst such as the original reg_cache_default array might have already been freed by the kernel. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: Add compress_type as a member to snd_soc_codecDimitris Papastamos2010-12-031-2/+2
| | | | | | | | | | | | | | We need to keep a copy of the compress_type supplied by the codec driver so that we can override it if necessary with whatever the machine driver has provided us with. The reason for not modifying the codec->driver struct directly is that ideally we'd like to keep it const. Adjust the code in soc-cache and soc-core to make use of the compress_type member in the snd_soc_codec struct. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: Move active copy of CODEC read and write into runtime structureMark Brown2010-12-031-2/+2
| | | | | | | | | | We shouldn't be assigning to the driver structure (which really ought to be const, further patch to follow) though there's unlikely to be any actual problem except in the unlikely case that two devices with the same driver but different bus types appear in the same system. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
* ASoC: soc-cache: Fix memory overflow in LZO initializationDimitris Papastamos2010-11-301-1/+1
| | | | | | | | | | | | The bitmap_zero() nbits argument was improperly set to reg_size but the underlying buffer was bmp_size long. This caused the memset to zero past the end of the allocated buffer and into the kernel heap causing strange kernel crashes sometimes by overwriting critical kernel structures. Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* ASoC: soc-cache: Ensure consistent cache namingDimitris Papastamos2010-11-291-1/+1
| | | | | | Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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