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* [SPARC64]: Hypervisor TSB context switching.David S. Miller2006-03-202-10/+16
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Implement sun4v TSB miss handlers.David S. Miller2006-03-201-0/+20
| | | | | | | | | | | When we register a TSB with the hypervisor, so that it or hardware can handle TLB misses and do the TSB walk for us, the hypervisor traps down to these trap when it incurs a TSB miss. Processing is simple, we load the missing virtual address and context, and do a full page table walk. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Detect sun4v early in boot process.David S. Miller2006-03-202-0/+9
| | | | | | | | | | | | | We look for "SUNW,sun4v" in the 'compatible' property of the root OBP device tree node. Protect every %ver register access, to make sure it is not touched on sun4v, as %ver is hyperprivileged there. Lock kernel TLB entries using hypervisor calls instead of calls into OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sun4v cross-call sending support.David S. Miller2006-03-201-2/+12
| | | | | | | | | | | Technically the hypervisor call supports sending in a list of all cpus to get the cross-call, but I only pass in one cpu at a time for now. The multi-cpu support is there, just ifdef'd out so it's easy to enable or delete it later. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sun4v interrupt handling.David S. Miller2006-03-201-8/+14
| | | | | | | | | | | | | | | | | Sun4v has 4 interrupt queues: cpu, device, resumable errors, and non-resumable errors. A set of head/tail offset pointers help maintain a work queue in physical memory. The entries are 64-bytes in size. Each queue is allocated then registered with the hypervisor as we bring cpus up. The two error queues each get a kernel side buffer that we use to quickly empty the main interrupt queue before we call up to C code to log the event and possibly take evasive action. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add sun4v mondo queue bases to struct trap_per_cpu.David S. Miller2006-03-201-8/+15
| | | | | | | Also, correct TRAP_PER_CPU_FAULT_INFO define, it should be 0x40 not 0x20. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix some comment typos in asm/hypervisor.hDavid S. Miller2006-03-201-2/+4
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Patch up mmu context register writes for sun4v.David S. Miller2006-03-201-5/+10
| | | | | | sun4v uses ASI_MMU instead of ASI_DMMU Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Register per-cpu fault status area with sun4v hypervisor.David S. Miller2006-03-201-0/+1
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: asm/cpudata.h needs asm/asi.hDavid S. Miller2006-03-201-1/+2
| | | | | | For the expansion of __GET_CPUID() on SMP. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patchDavid S. Miller2006-03-201-4/+7
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Initial sun4v TLB miss handling infrastructure.David S. Miller2006-03-202-2/+17
| | | | | | | | | | Things are a little tricky because, unlike sun4u, we have to: 1) do a hypervisor trap to do the TLB load. 2) do the TSB lookup calculations by hand Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sanitize %pstate writes for sun4v.David S. Miller2006-03-201-0/+6
| | | | | | | | If we're just switching between different alternate global sets, nop it out on sun4v. Also, get rid of all of the alternate global save/restore in the OBP CIF trampoline code. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill all %pstate changes in context switch code.David S. Miller2006-03-201-5/+0
| | | | | | | | | | | | | | | They are totally unnecessary because: 1) Interrupts are already disabled when switch_to() runs. 2) We don't use hard-coded alternate globals any longer. This found a case in rtrap, which still assumed alternate global %g6 was current_thread_info(), and that is fixed by this changeset as well. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add initial code to twiddle %gl on trap entry/exit.David S. Miller2006-03-202-0/+9
| | | | | | | Instead of setting/clearing PSTATE_AG we have to change the %gl register value on sun4v. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add define for "GL" field of sun4v %tstate register.David S. Miller2006-03-201-2/+3
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add sun4v case to __GET_CPUID() patch tables.David S. Miller2006-03-201-0/+8
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sun4v interrupt queue register definitions.David S. Miller2006-03-201-0/+15
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sun4v scratchpad register layout.David S. Miller2006-03-201-0/+14
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sun4v specific ASI defines.David S. Miller2006-03-201-0/+9
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add Niagara init-store twin-load ASI defines.David S. Miller2006-03-201-1/+8
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add 'hypervisor' to ultra_tlb_type enumeration.David S. Miller2006-03-201-0/+1
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: SUN4V hypervisor interface defines.David S. Miller2006-03-201-0/+2072
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Refine register window trap handling.David S. Miller2006-03-201-1/+233
| | | | | | | | | | | When saving and restoing trap state, do the window spill/fill handling inline so that we never trap deeper than 2 trap levels. This is important for chips like Niagara. The window fixup code is massively simplified, and many more improvements are now possible. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add explicit register args to trap state loading macros.David S. Miller2006-03-201-44/+44
| | | | | | | This, as well as making the code cleaner, allows a simplification in the TSB miss handling path. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Refine code sequences to get the cpu id.David S. Miller2006-03-203-47/+71
| | | | | | | | | | | | | | | | | | On uniprocessor, it's always zero for optimize that. On SMP, the jmpl to the stub kills the return address stack in the cpu branch prediction logic, so expand the code sequence inline and use a code patching section to fix things up. This also always better and explicit register selection, which will be taken advantage of in a future changeset. The hard_smp_processor_id() function is big, so do not inline it. Fix up tests for Jalapeno to also test for Serrano chips too. These tests want "jbus Ultra-IIIi" cases to match, so that is what we should test for. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Correctable ECC errors cannot occur at trap level > 0.David S. Miller2006-03-201-6/+3
| | | | | | | | | | | | | The are distrupting, which by the sparc v9 definition means they can only occur when interrupts are enabled in the %pstate register. This never occurs in any of the trap handling code running at trap levels > 0. So just mark it as an unexpected trap. This allows us to kill off the cee_stuff member of struct thread_info. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Access TSB with physical addresses when possible.David S. Miller2006-03-202-6/+91
| | | | | | | | | | | | | This way we don't need to lock the TSB into the TLB. The trick is that every TSB load/store is registered into a special instruction patch section. The default uses virtual addresses, and the patch instructions use physical address load/stores. We can't do this on all chips because only cheetah+ and later have the physical variant of the atomic quad load. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill out-of-date commentary in asm-sparc64/tsb.hDavid S. Miller2006-03-201-8/+0
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix race in LOAD_PER_CPU_BASE()David S. Miller2006-03-201-7/+12
| | | | | | | | | | Since we use %g5 itself as a temporary, it can get clobbered if we take an interrupt mid-stream and thus cause end up with the final %g5 value too early as a result of rtrap processing. Set %g5 at the very end, atomically, to avoid this problem. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Increase swapper_tsb size to 32K.David S. Miller2006-03-201-3/+10
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill sole argument passed to setup_tba().David S. Miller2006-03-201-0/+1
| | | | | | No longer used, and move extern declaration to a header file. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix incorrect TSB lock bit handling.David S. Miller2006-03-201-2/+3
| | | | | | | | | | The TSB_LOCK_BIT define is actually a special value shifted down by 32-bits for the assembler code macros. In C code, this isn't what we want. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Preload TSB entries from update_mmu_cache().David S. Miller2006-03-201-0/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Dynamically grow TSB in response to RSS growth.David S. Miller2006-03-202-0/+8
| | | | | | | | | As the RSS grows, grow the TSB in order to reduce the likelyhood of hash collisions and thus poor hit rates in the TSB. This definitely needs some serious tuning. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add infrastructure for dynamic TSB sizing.David S. Miller2006-03-203-6/+24
| | | | | | | | | | | | | | | This also cleans up tsb_context_switch(). The assembler routine is now __tsb_context_switch() and the former is an inline function that picks out the bits from the mm_struct and passes it into the assembler code as arguments. setup_tsb_parms() computes the locked TLB entry to map the TSB. Later when we support using the physical address quad load instructions of Cheetah+ and later, we'll simply use the physical address for the TSB register value and set the map virtual and PTE both to zero. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: TSB refinements.David S. Miller2006-03-202-30/+6
| | | | | | | | | | Move {init_new,destroy}_context() out of line. Do not put huge pages into the TSB, only base page size translations. There are some clever things we could do here, but for now let's be correct instead of fancy. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Elminate all usage of hard-coded trap globals.David S. Miller2006-03-203-11/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UltraSPARC has special sets of global registers which are switched to for certain trap types. There is one set for MMU related traps, one set of Interrupt Vector processing, and another set (called the Alternate globals) for all other trap types. For what seems like forever we've hard coded the values in some of these trap registers. Some examples include: 1) Interrupt Vector global %g6 holds current processors interrupt work struct where received interrupts are managed for IRQ handler dispatch. 2) MMU global %g7 holds the base of the page tables of the currently active address space. 3) Alternate global %g6 held the current_thread_info() value. Such hardcoding has resulted in some serious issues in many areas. There are some code sequences where having another register available would help clean up the implementation. Taking traps such as cross-calls from the OBP firmware requires some trick code sequences wherein we have to save away and restore all of the special sets of global registers when we enter/exit OBP. We were also using the IMMU TSB register on SMP to hold the per-cpu area base address, which doesn't work any longer now that we actually use the TSB facility of the cpu. The implementation is pretty straight forward. One tricky bit is getting the current processor ID as that is different on different cpu variants. We use a stub with a fancy calling convention which we patch at boot time. The calling convention is that the stub is branched to and the (PC - 4) to return to is in register %g1. The cpu number is left in %g6. This stub can be invoked by using the __GET_CPUID macro. We use an array of per-cpu trap state to store the current thread and physical address of the current address space's page tables. The TRAP_LOAD_THREAD_REG loads %g6 with the current thread from this table, it uses __GET_CPUID and also clobbers %g1. TRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load the current processor's IRQ software state into %g6. It also uses __GET_CPUID and clobbers %g1. Finally, TRAP_LOAD_PGD_PHYS loads the physical address base of the current address space's page tables into %g7, it clobbers %g1 and uses __GET_CPUID. Many refinements are possible, as well as some tuning, with this stuff in place. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill pgtable quicklists and use SLAB.David S. Miller2006-03-203-145/+29
| | | | | | | | | Taking a nod from the powerpc port. With the per-cpu caching of both the page allocator and SLAB, the pgtable quicklist scheme becomes relatively silly and primitive. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: No need to D-cache color page tables any longer.David S. Miller2006-03-202-57/+49
| | | | | | | Unlike the virtual page tables, the new TSB scheme does not require this ugly hack. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Move away from virtual page tables, part 1.David S. Miller2006-03-207-57/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We now use the TSB hardware assist features of the UltraSPARC MMUs. SMP is currently knowingly broken, we need to find another place to store the per-cpu base pointers. We hid them away in the TSB base register, and that obviously will not work any more :-) Another known broken case is non-8KB base page size. Also noticed that flush_tlb_all() is not referenced anywhere, only the internal __flush_tlb_all() (local cpu only) is used by the sparc64 port, so we can get rid of flush_tlb_all(). The kernel gets it's own 8KB TSB (swapper_tsb) and each address space gets it's own private 8K TSB. Later we can add code to dynamically increase the size of per-process TSB as the RSS grows. An 8KB TSB is good enough for up to about a 4MB RSS, after which the TSB starts to incur many capacity and conflict misses. We even accumulate OBP translations into the kernel TSB. Another area for refinement is large page size support. We could use a secondary address space TSB to handle those. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Mark __ex_table section correctly.David S. Miller2006-03-042-7/+7
| | | | | | | | | | We must use the "a" (allocate) attribute every time we emit an entry into the __ex_table section. For consistency, use "a" instead of #alloc which is some Solaris compat cruft GNU as provides on Sparc. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Make cpu_present_map available earlier.David S. Miller2006-02-261-0/+6
| | | | | | | | | | | | The change to kernel/sched.c's init code to use for_each_cpu() requires that the cpu_possible_map be setup much earlier. Set it up via setup_arch(), constrained to NR_CPUS, and later constrain it to max_cpus in smp_prepare_cpus(). This fixes SMP booting on sparc64. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Implement futex_atomic_op_inuser().David S. Miller2006-02-261-4/+84
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [PATCH] add asm-generic/mman.hMichael S. Tsirkin2006-02-151-29/+2
| | | | | | | | | | | | | | Make new MADV_REMOVE, MADV_DONTFORK, MADV_DOFORK consistent across all arches. The idea is to make it possible to use them portably even before distros include them in libc headers. Move common flags to asm-generic/mman.h Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il> Cc: Roland Dreier <rolandd@cisco.com> Cc: Badari Pulavarty <pbadari@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] madvise MADV_DONTFORK/MADV_DOFORKMichael S. Tsirkin2006-02-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Currently, copy-on-write may change the physical address of a page even if the user requested that the page is pinned in memory (either by mlock or by get_user_pages). This happens if the process forks meanwhile, and the parent writes to that page. As a result, the page is orphaned: in case of get_user_pages, the application will never see any data hardware DMA's into this page after the COW. In case of mlock'd memory, the parent is not getting the realtime/security benefits of mlock. In particular, this affects the Infiniband modules which do DMA from and into user pages all the time. This patch adds madvise options to control whether memory range is inherited across fork. Useful e.g. for when hardware is doing DMA from/into these pages. Could also be useful to an application wanting to speed up its forks by cutting large areas out of consideration. Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il> Acked-by: Hugh Dickins <hugh@veritas.com> Cc: Michael Kerrisk <mtk-manpages@gmx.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [SPARC]: sys_newfstatat --> sys_fstatat64David S. Miller2006-02-121-1/+1
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC]: Wire up sys_unshare().David S. Miller2006-02-071-3/+4
| | | | | | | | Also, the Solaris syscall table is sized differrently, and does not go beyond entry 255, so trim off the excess entries. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Implement __raw_read_trylock()David S. Miller2006-01-231-1/+23
| | | | | | | generic__raw_read_trylock() just does a raw_read_lock() so that isn't very useful. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC]: Add support for *at(), ppoll, and pselect syscalls.David S. Miller2006-01-192-6/+23
| | | | | | | | | | This also includes by necessity _TIF_RESTORE_SIGMASK support, which actually resulted in a lot of cleanups. The sparc signal handling code is quite a mess and I should clean it up some day. Signed-off-by: David S. Miller <davem@davemloft.net>
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