summaryrefslogtreecommitdiffstats
path: root/include/asm-powerpc
Commit message (Collapse)AuthorAgeFilesLines
* [POWERPC] ps3: Missed renames of CONFIG_PS3 to CONFIG_PPC_PS3Geert Uytterhoeven2006-12-041-2/+2
| | | | | | | | | | When renaming CONFIG_PS3 to CONFIG_PPC_PS3, a few occurrences have been missed. I also fixed up the alignment in arch/powerpc/platforms/Makefile. Signed-off-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
* [POWERPC] cell: fix building without spufsArnd Bergmann2006-12-041-1/+1
| | | | | | | | | It may be desireable to build a kernel for cell without spufs, e.g. as the initial kboot kernel. This requires that the SPU specific parts of the core dump and the xmon code depend on CONFIG_SPU_BASE instead of CONFIG_PPC_CELL. Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
* [POWERPC] ps3: add ps3 platform system bus supportGeoff Levand2006-12-041-0/+73
| | | | | | | | Adds a PS3 system bus driver. This system bus is a virtual bus used to present the PS3 system devices in the LDM. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
* [POWERPC] ps3: add lpar addressingGeoff Levand2006-12-041-0/+6
| | | | | | | | | Adds some needed bits for a config option PS3_USE_LPAR_ADDR that disables the PS3 lpar address translation mechanism. This is a currently needed workaround for limitations in the design of the generic cell spu support. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
* [POWERPC] ps3: add repository supportGeoff Levand2006-12-041-0/+139
| | | | | | | Adds support for the PS3 repository. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
* [POWERPC] ps3: add feature bitsGeoff Levand2006-12-041-0/+8
| | | | | | | Adds the needed firmware feature bits for the PS3. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
* [POWERPC] ps3: add lv1 hvcallsGeoff Levand2006-12-041-0/+345
| | | | | | | Adds the PS3 hvcalls. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
* [POWERPC] ps3: add support for ps3 platformGeoff Levand2006-12-041-0/+250
| | | | | | | | Adds the core platform support for the PS3 game console and other devices using the PS3 hypervisor. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
* [POWERPC] cell: abstract spu management routinesGeoff Levand2006-12-042-9/+36
| | | | | | | | | | | | | | | | | This adds a platform specific spu management abstraction and the coresponding routines to support the IBM Cell Blade. It also removes the hypervisor only resources that were included in struct spu. Three new platform specific routines are introduced, spu_enumerate_spus(), spu_create_spu() and spu_destroy_spu(). The underlying design uses a new type, struct spu_management_ops, to hold function pointers that the platform setup code is expected to initialize to instances appropriate to that platform. For the IBM Cell Blade support, I put the hypervisor only resources that were in struct spu into a platform specific data structure struct spu_pdata. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
* [POWERPC] add virq_to_hw accessor routineGeoff Levand2006-12-041-0/+4
| | | | | | | | | | This adds an accessor routine virq_to_hw() to the virq routines which hides the implementation details of the virq to hwirq map. Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
* [POWERPC] Make 64-bit cpu features defined on 32-bitMichael Ellerman2006-12-041-2/+2
| | | | | | | | It saves #ifdef'ing in callers if we at least define the 64-bit cpu features for 32-bit also. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
* [POWERPC] coredump: Add SPU elf notes to coredump.Dwayne Grant McConnell2006-12-042-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SPU elf notes to the coredump. It creates a separate note for each of /regs, /fpcr, /lslr, /decr, /decr_status, /mem, /signal1, /signal1_type, /signal2, /signal2_type, /event_mask, /event_status, /mbox_info, /ibox_info, /wbox_info, /dma_info, /proxydma_info, /object-id. A new macro, ARCH_HAVE_EXTRA_NOTES, was created for architectures to specify they have extra elf core notes. A new macro, ELF_CORE_EXTRA_NOTES_SIZE, was created so the size of the additional notes could be calculated and added to the notes phdr entry. A new macro, ELF_CORE_WRITE_EXTRA_NOTES, was created so the new notes would be written after the existing notes. The SPU coredump code resides in spufs. Stub functions are provided in the kernel which are hooked into the spufs code which does the actual work via register_arch_coredump_calls(). A new set of __spufs_<file>_read/get() functions was provided to allow the coredump code to read from the spufs files without having to lock the SPU context for each file read from. Cc: <linux-arch@vger.kernel.org> Signed-off-by: Dwayne Grant McConnell <decimal@us.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
* [POWERPC] Distinguish POWER6 partition modes and tell userspacePaul Mackerras2006-12-041-2/+11
| | | | | | | | | | | | | | | | | This adds code to look at the properties firmware puts in the device tree to determine what compatibility mode the partition is in on POWER6 machines, and set the ELF aux vector AT_HWCAP and AT_PLATFORM entries appropriately. Specifically, we look at the cpu-version property in the cpu node(s). If that contains a "logical" PVR value (of the form 0x0f00000x), we call identify_cpu again with this PVR value. A value of 0x0f000001 indicates the partition is in POWER5+ compatibility mode, and a value of 0x0f000002 indicates "POWER6 architected" mode, with various extensions disabled. We also look for various other properties: ibm,dfp, ibm,purr and ibm,spurr. Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] cell: Add oprofile supportMaynard Johnson2006-12-043-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PPU event-based and cycle-based profiling support to Oprofile for Cell. Oprofile is expected to collect data on all CPUs simultaneously. However, there is one set of performance counters per node. There are two hardware threads or virtual CPUs on each node. Hence, OProfile must multiplex in time the performance counter collection on the two virtual CPUs. The multiplexing of the performance counters is done by a virtual counter routine. Initially, the counters are configured to collect data on the even CPUs in the system, one CPU per node. In order to capture the PC for the virtual CPU when the performance counter interrupt occurs (the specified number of events between samples has occurred), the even processors are configured to handle the performance counter interrupts for their node. The virtual counter routine is called via a kernel timer after the virtual sample time. The routine stops the counters, saves the current counts, loads the last counts for the other virtual CPU on the node, sets interrupts to be handled by the other virtual CPU and restarts the counters, the virtual timer routine is scheduled to run again. The virtual sample time is kept relatively small to make sure sampling occurs on both CPUs on the node with a relatively small granularity. Whenever the counters overflow, the performance counter interrupt is called to collect the PC for the CPU where data is being collected. The oprofile driver relies on a firmware RTAS call to setup the debug bus to route the desired signals to the performance counter hardware to be counted. The RTAS call must set the routing registers appropriately in each of the islands to pass the signals down the debug bus as well as routing the signals from a particular island onto the bus. There is a second firmware RTAS call to reset the debug bus to the non pass thru state when the counters are not in use. Signed-off-by: Carl Love <carll@us.ibm.com> Signed-off-by: Maynard Johnson <mpjohn@us.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] cell: Add routines for managing PMU interruptsKevin Corry2006-12-041-0/+5
| | | | | | | | | | | | | | | | | | | The following routines are added to arch/powerpc/platforms/cell/pmu.c: cbe_clear_pm_interrupts() cbe_enable_pm_interrupts() cbe_disable_pm_interrupts() cbe_query_pm_interrupts() cbe_pm_irq() cbe_init_pm_irq() This also adds a routine in arch/powerpc/platforms/cell/interrupt.c and some macros in cbe_regs.h to manipulate the IIC_IR register: iic_set_interrupt_routing() Signed-off-by: Kevin Corry <kevcorry@us.ibm.com> Signed-off-by: Carl Love <carll@us.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] cell: Move PMU-related stuff to include/asm-powerpc/cell-pmu.hKevin Corry2006-12-041-0/+90
| | | | | | | | | | | | | Move some PMU-related macros and function prototypes from cbe_regs.h and pmu.h in arch/powerpc/platforms/cell/ to a new header at include/asm-powerpc/cell-pmu.h This is cleaner to use from the oprofile code, since that sits in arch/powerpc/oprofile, not in the cell platform directory. Signed-off-by: Kevin Corry <kevcorry@us.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] spufs: Add /lslr, /dma_info and /proxydma filesDwayne Grant McConnell2006-12-042-0/+55
| | | | | | | | | | | | | The /lslr file gives read access to the SPU_LSLR register in hex; 0x3fff for example The /dma_info file provides read access to the SPU Command Queue in a binary format. The /proxydma_info files provides read access access to the Proxy Command Queue in a binary format. The spu_info.h file provides data structures for interpreting the binary format of /dma_info and /proxydma_info. Signed-off-by: Dwayne Grant McConnell <decimal@us.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Change ppc_rtas declaration to weakGeoff Levand2006-12-041-10/+2
| | | | | | | | | | | | | | Change the definition of powerpc's cond_syscall() to use the standard gcc weak attribute specifier which provides proper support for C linkage as needed by spu_syscall_table[]. Fixes this powerpc build error with CONFIG_SPU_FS=y, CONFIG_PPC_RTAS=n: arch/powerpc/platforms/built-in.o: undefined reference to `ppc_rtas' Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Xserve cpu-meter driverBenjamin Herrenschmidt2006-12-041-1/+7
| | | | | | | | | | This is a small driver for the Xserve G5 CPU-meter blue LEDs on the front-panel. It might work on the Xserve G4 as well though that was not tested. It's pretty basic and could use some improvements if somebody cares doing them. :) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Wrap cpu_die() with CONFIG_HOTPLUG_CPULinas Vepstas2006-12-041-2/+0
| | | | | | | | | | Per email discussion, it appears that rtas_stop_self() and pSeries_mach_cpu_die() should not be compiled if CONFIG_HOTPLUG_CPU is not defined. This patch adds #ifdefs around these bits of code. Signed-off-by: Linas Vepstas <linas@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Make soft_enabled irqs preempt safeHugh Dickins2006-12-041-5/+15
| | | | | | | | | Rewrite local_get_flags and local_irq_disable to use r13 explicitly, to avoid the risk that gcc will split get_paca()->soft_enabled into a sequence unsafe against preemption. Similar care in local_irq_restore. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Fix __raw* accessorsBenjamin Herrenschmidt2006-12-041-47/+45
| | | | | | | | | The new IO accessor code allows to stick a token in the top bit of MMIO addresses which gets masked out during actual accesses. However, the __raw_* accessors forgot to mask it out. This fixes it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Merge 32 and 64 bits asm-powerpc/io.hBenjamin Herrenschmidt2006-12-045-147/+254
| | | | | | | | | | | | | powerpc: Merge 32 and 64 bits asm-powerpc/io.h The rework on io.h done for the new hookable accessors made it easier, so I just finished the work and merged 32 and 64 bits io.h for arch/powerpc. arch/ppc still uses the old version in asm-ppc, there is just too much gunk in there that I really can't be bothered trying to cleanup. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Cell iommu supportJeremy Kerr2006-12-041-3/+3
| | | | | | | | | | | | | | This patch adds full cell iommu support (and iommu disabled mode). It implements mapping/unmapping of iommu pages on demand using the standard powerpc iommu framework. It also supports running with iommu disabled for machines with less than 2GB of memory. (The default is off in that case, though it can be forced on with the kernel command line option iommu=force). Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Add an optional offset to direct DMA on 64 bitsBenjamin Herrenschmidt2006-12-041-0/+2
| | | | | | | | | | | | This patch adds an optional global offset that can be added to DMA addresses when using the direct DMA operations. That brings it a step closer to the 32 bits direct DMA operations, and makes it useable on Cell when the MMU is disabled and we are using a spider southbridge. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bitsBenjamin Herrenschmidt2006-12-045-355/+471
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reworks the way iSeries hooks on PCI IO operations (both MMIO and PIO) and provides a generic way for other platforms to do so (we have need to do that for various other platforms). While reworking the IO ops, I ended up doing some spring cleaning in io.h and eeh.h which I might want to split into 2 or 3 patches (among others, eeh.h had a lot of useless stuff in it). A side effect is that EEH for PIO should work now (it used to pass IO ports down to the eeh address check functions which is bogus). Also, new are MMIO "repeat" ops, which other archs like ARM already had, and that we have too now: readsb, readsw, readsl, writesb, writesw, writesl. In the long run, I might also make EEH use the hooks instead of wrapping at the toplevel, which would make things even cleaner and relegate EEH completely in platforms/iseries, but we have to measure the performance impact there (though it's really only on MMIO reads) Since I also need to hook on ioremap, I shuffled the functions a bit there. I introduced ioremap_flags() to use by drivers who want to pass explicit flags to ioremap (and it can be hooked). The old __ioremap() is still there as a low level and cannot be hooked, thus drivers who use it should migrate unless they know they want the low level version. The patch "arch provides generic iomap missing accessors" (should be number 4 in this series) is a pre-requisite to provide full iomap API support with this patch. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Generic OF platform driver for PCI host bridges.Benjamin Herrenschmidt2006-12-042-6/+10
| | | | | | | | | | | | | | | | | When enabled in Kconfig, it will pick up any of_platform_device matching it's match list (currently type "pci", "pcix", "pcie", or "ht" and setup a PHB for it. Platform must provide a ppc_md.pci_setup_phb() for it to work (for doing the necessary initialisations specific to a given PHB like setting up the config space ops). It's currently only available on 64 bits as the 32 bits PCI code can't quite cope with it in it's current form. I will fix that later. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Add "parent" struct device for PCI host bridgesBenjamin Herrenschmidt2006-12-041-0/+1
| | | | | | | | | | | Add a "parent" struct device to our PCI host bridge data structure so that PCI can be rooted off another device in sysfs. Note that arch/ppc doesn't use it, only arch/powerpc, though it's available for both 32 and 64 bits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Refactor 64 bits DMA operationsBenjamin Herrenschmidt2006-12-049-59/+180
| | | | | | | | | | | | | | | | | This patch completely refactors DMA operations for 64 bits powerpc. 32 bits is untouched for now. We use the new dev_archdata structure to add the dma operations pointer and associated data to struct device. While at it, we also add the OF node pointer and numa node. In the future, we might want to look into merging that with pci_dn as well. The old vio, pci-iommu and pci-direct DMA ops are gone. They are now replaced by a set of generic iommu and direct DMA ops (non PCI specific) that can be used by bus types. The toplevel implementation is now inline. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Souped-up of_platform_device supportBenjamin Herrenschmidt2006-12-042-32/+62
| | | | | | | | | | | | | | | | | | | | | | | | This patch first splits of_device.c and of_platform.c, the later containing the bits relative to of_platform_device's. On the "breaks" side of things, drivers uisng of_platform_device(s) need to include asm/of_platform.h now and of_(un)register_driver is now of_(un)register_platform_driver. In addition to a few utility functions to locate of_platform_device(s), the main new addition is of_platform_bus_probe() which allows the platform code to trigger an automatic creation of of_platform_devices for a whole tree of devices. The function acts based on the type of the various "parent" devices encountered from a provided root, using either a default known list of bus types that can be "probed" or a passed-in list. It will only register devices on busses matching that list, which mean that typically, it will not register PCI devices, as expected (since they will be picked up by the PCI layer). This will be used by Cell platforms using 4xx-type IOs in the Axon bridge and can be used by any embedded-type device as well. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Improve MPIC driver auto-configuration from DTBenjamin Herrenschmidt2006-12-041-2/+2
| | | | | | | | | | | | This patch applies on top of the MPIC DCR support. It makes the MPIC driver capable of a lot more auto-configuration based on the device-tree, for example, it can retreive it's own physical address if not passed as an argument, find out if it's DCR or MMIO mapped, and set the BIG_ENDIAN flag automatically in the presence of a "big-endian" property in the device-tree node. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Support for DCR based MPICBenjamin Herrenschmidt2006-12-041-4/+31
| | | | | | | | | | | | | | | | This patch implements support for DCR based MPIC implementations. Such implementations have the MPIC_USES_DCR flag set and don't use the phys_addr argument of mpic_alloc (they require a valid dcr mapping in the device node) This version of the patch can use a little bif of cleanup still (I can probably consolidate rb->dbase/doff, at least once I'm sure on how the hardware is actually supposed to work vs. possible simulator issues) and it should be possible to build a DCR-only version of the driver. I need to cleanup a bit the CONFIG_* handling for that and probably introduce CONFIG_MPIC_MMIO and CONFIG_MPIC_DCR. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Generic DCR infrastructureBenjamin Herrenschmidt2006-12-043-0/+132
| | | | | | | | | | | This patch adds new dcr_map/dcr_read/dcr_write accessors for DCRs that can be used by drivers to transparently address either native DCRs or memory mapped DCRs. The implementation for memory mapped DCRs is done after the binding being currently worked on for SLOF and the Axon chipset. This patch enables it for the cell native platform Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Remove ppc_md.pci_map_irq & ppc_swizzle for ARCH=powerpcBenjamin Herrenschmidt2006-12-041-4/+0
| | | | | | | | | | | | | | These were inherited from ARCH=ppc, but are not needed since parsing of interrupts should be done via the of_* functions (who can do swizzling). If we ever need to do non-standard swizzling on bridges without a device-node, then we might add back a slightly different version of ppc_md.pci_swizzle but for now, that is not the case. I removed the couple of calls for these in 83xx. If that breaks something, then there is a problem with the device-tree on these. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Make pci_read_irq_line the defaultBenjamin Herrenschmidt2006-12-042-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | This patch reworks the way IRQs are fixed up on PCI for arch powerpc. It makes pci_read_irq_line() called by default in the PCI code for devices that are probed, and add an optional per-device fixup in ppc_md for platforms that really need to correct what they obtain from pci_read_irq_line(). It also removes ppc_md.irq_bus_setup which was only used by pSeries and should not be needed anymore. I've also removed the pSeries s7a workaround as it can't work with the current interrupt code anyway. I'm trying to get one of these machines working so I can test a proper fix for that problem. I also haven't updated the old-style fixup code from 85xx_cds.c because it's actually buggy :) It assigns pci_dev->irq hard coded numbers which is no good with the new IRQ mapping code. It should at least use irq_create_mapping(NULL, hard_coded_number); and possibly also set_irq_type() to set them as level low. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* Merge branch 'linux-2.6' into for-linusPaul Mackerras2006-12-0422-147/+317
|\
| * [NET]: POWERPC checksum annotations and cleanups.Al Viro2006-12-021-38/+21
| | | | | | | | | | | | | | | | * sanitize prototypes, annotate * kill useless shifts Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
| * Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6Linus Torvalds2006-12-011-13/+7
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6: (28 commits) PCI: make arch/i386/pci/common.c:pci_bf_sort static PCI: ibmphp_pci.c: fix NULL dereference pciehp: remove unnecessary pci_disable_msi pciehp: remove unnecessary free_irq PCI: rpaphp: change device tree examination PCI: Change memory allocation for acpiphp slots i2c-i801: SMBus patch for Intel ICH9 PCI: irq: irq and pci_ids patch for Intel ICH9 PCI: pci_{enable,disable}_device() nestable ports PCI: switch pci_{enable,disable}_device() to be nestable PCI: arch/i386/kernel/pci-dma.c: ioremap balanced with iounmap pci/i386: style cleanups PCI: Block on access to temporarily unavailable pci device pci: fix __pci_register_driver error handling pci: clear osc support flags if no _OSC method acpiphp: fix missing acpiphp_glue_exit() acpiphp: fix use of list_for_each macro Altix: Initial ACPI support - ROM shadowing. Altix: SN ACPI hotplug support. Altix: Add initial ACPI IO support ...
| | * PCI: Replace HAVE_ARCH_PCI_MWI with PCI_DISABLE_MWIMatthew Wilcox2006-12-011-13/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pSeries is the only architecture left using HAVE_ARCH_PCI_MWI and it's really inappropriate for its needs. It really wants to disable MWI altogether. So here are a pair of stub implementations for pci_set_mwi and pci_clear_mwi. Also rename pci_generic_prep_mwi to pci_set_cacheline_size since that better reflects what it does. Signed-off-by: Matthew Wilcox <matthew@wil.cx> Cc: Paul Mackerras <paulus@samba.org> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * | Driver core: add dev_archdata to struct deviceBenjamin Herrenschmidt2006-12-011-0/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Add arch specific dev_archdata to struct device Adds an arch specific struct dev_arch to struct device. This enables architecture to add specific fields to every device in the system, like DMA operation pointers, NUMA node ID, firmware specific data, etc... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Andi Kleen <ak@suse.de> Acked-By: David Howells <dhowells@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * [POWERPC] Revert "[POWERPC] Add powerpc get/set_rtc_time interface to new ↵Kim Phillips2006-11-221-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | generic rtc class" This reverts commit 7a69af63e788a324d162201a0b23df41bcf158dd. As advised by David Brownell: http://marc.theaimsgroup.com/?l=linux-kernel&m=116387226902131&w=2 Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * [POWERPC] Wire up sys_move_pagesStephen Rothwell2006-11-162-1/+3
| | | | | | | | | | | | | | | | All the infrastructure is already in place for this, so we only need to allocate a syscall number and hook it up. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * [POWERPC] Add the thread_siblings files to sysfsStephen Rothwell2006-11-161-1/+7
| | | | | | | | | | | | | | | | | | This adds the /sys/devices/system/cpu/*/topology/thread_siblings files on powerpc. These files are already available on other architectures. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * [PATCH] powerpc: wire up sys_migrate_pagesStephen Rothwell2006-11-032-2/+2
| | | | | | | | | | | | | | Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Christoph Lameter <clameter@sgi.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
| * [POWERPC] Make mmiowb's io_sync preempt safeHugh Dickins2006-11-011-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If mmiowb() is always used prior to releasing spinlock as Doc suggests, then it's safe against preemption; but I'm not convinced that's always the case. If preemption occurs between sync and get_paca()->io_sync = 0, I believe there's no problem. But in the unlikely event that gcc does the store relative to another register than r13 (as it did with current), then there's a small danger of setting another cpu's io_sync to 0, after it had just set it to 1. Rewrite ppc64 mmiowb to prevent that. The remaining io_sync assignments in io.h all get_paca()->io_sync = 1, which is harmless even if preempted to the wrong cpu (the context switch itself syncs); and those in spinlock.h are while preemption is disabled. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * [POWERPC] Make current preempt-safeHugh Dickins2006-11-011-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Repeated -j20 kernel builds on a G5 Quad running an SMP PREEMPT kernel would often collapse within a day, some exec failing with "Bad address". In each case examined, load_elf_binary was doing a kernel_read, but generic_file_aio_read's access_ok saw current->thread.fs.seg as USER_DS instead of KERNEL_DS. objdump of filemap.o shows gcc 4.1.0 emitting "mr r5,r13 ... ld r9,416(r5)" here for get_paca()->__current, instead of the expected and much more usual "ld r9,416(r13)"; I've seen other gcc4s do the same, but perhaps not gcc3s. So, if the task is preempted and rescheduled on a different cpu in between the mr and the ld, r5 will be looking at a different paca_struct from the one it's now on, pick up the wrong __current, and perhaps the wrong seg. Presumably much worse could happen elsewhere, though that split is rare. Other architectures appear to be safe (x86_64's read_pda is more limiting than get_paca), but ppc64 needs to force "current" into one instruction. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * [POWERPC] Use 4kB iommu pages even on 64kB-page systemsLinas Vepstas2006-11-012-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 10Gigabit ethernet device drivers appear to be able to chew up all 256MB of TCE mappings on pSeries systems, as evidenced by numerous error messages: iommu_alloc failed, tbl c0000000010d5c48 vaddr c0000000d875eff0 npages 1 Some experimentation indicates that this is essentially because one 1500 byte ethernet MTU gets mapped as a 64K DMA region when the large 64K pages are enabled. Thus, it doesn't take much to exhaust all of the available DMA mappings for a high-speed card. This patch changes the iommu allocator to work with its own unique, distinct page size. Although the patch is long, its actually quite simple: it just #defines a distinct IOMMU_PAGE_SIZE and then uses this in all the places that matter. As a side effect, it also dramatically improves network performance on platforms with H-calls on iommu translation inserts/removes (since we no longer call it 16 times for a 1500 bytes packet when the iommu HW is still 4k). In the future, we might want to make the IOMMU_PAGE_SIZE a variable in the iommu_table instance, thus allowing support for different HW page sizes in the iommu itself. Signed-off-by: Linas Vepstas <linas@austin.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * [POWERPC] Fix oprofile support for e500 in arch/powerpcAndy Fleming2006-11-012-15/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed a compile error in building the 85xx support with oprofile, and in the process cleaned up some issues with the fsl_booke performance monitor code. * Reorganized FSL Book-E performance monitoring code so that the 7450 wouldn't be built if the e500 was, and cleaned it up so it was more self-contained. * Added a cpu_setup function for FSL Book-E. The original cpu_setup function prototype had no arguments, assuming that the reg_setup function would copy the required information into variables which represented the registers. This was silly for e500, since it has 1 register per counter (rather than 3 for all counters), so the code has been restructured to have cpu_setup take the current counter config array as an argument, with op_powerpc_setup() invoking op_powerpc_cpu_setup() through on_each_cpu(), and op_powerpc_cpu_setup() invoking the model-specific cpu_setup function with an argument. The argument is ignored on all other platforms at present. * Fixed a confusing line where a trinary operator only had two arguments Signed-off-by: Andrew Fleming <afleming@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * [POWERPC] Fix rmb() for e500-based machines itAndy Fleming2006-11-011-3/+3
| | | | | | | | | | | | | | | | | | | | The e500 core generates an illegal instruction exception when it tries to execute the lwsync instruction, which we currently use for rmb(). This fixes it by using the LWSYNC macro, which turns into a plain sync on 32-bit machines. Signed-off-by: Andrew Fleming <afleming@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * [POWERPC] Fix CHRP platforms with only 8259Benjamin Herrenschmidt2006-10-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | On CHRP platforms with only a 8259 controller, we should set the default IRQ host to the 8259 driver's one for the IRQ probing fallbacks to work in case the IRQ tree is incorrect (like on Pegasos for example). Without this fix, we get a bunch of WARN_ON's during boot. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
OpenPOWER on IntegriCloud