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* [MIPS] Make ioremap() work on TX39/49 special unmapped segmentAtsushi Nemoto2007-07-105-0/+110
| | | | | | | | | | | | | TX39XX and TX49XX have "reserved" segment in CKSEG3 area. 0xff000000-0xff3fffff on TX49XX and 0xff000000-0xfffeffff on TX39XX are reserved (unmapped, uncached). Controllers on these SoCs are placed in this segment. This patch add plat_ioremap() and plat_iounmap() to override default behavior and implement these hooks for TX39/TX49. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] rbtx4938: Convert SPI codes to use generic SPI driversAtsushi Nemoto2007-07-102-61/+1
| | | | | | | | | | | Use rtc-rs5c348 and at25 spi protocol driver and spi_txx9 spi controller driver instead of platform dependent codes. This patch also removes dependencies to old RTC interfaces such as rtc_mips_get_time, etc. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SNI RM updatesThomas Bogendoerfer2007-07-101-3/+0
| | | | | | | | | | | | - use RTC_CLASS instead of GEN_RTC - get rid of ds1216 in favour of a RTC_CLASS driver - use correct console device for older RM400 - use physical addresses for 82596 device - use 128 byte L1 cache line size (this is needed because most of the SNI caches are using 128 L2 cache lines) Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] PMC MSP71xx PCI supportMarc St-Jean2007-07-101-0/+205
| | | | | | | Patch to add PCI support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] PMC MSP71xx mips commonMarc St-Jean2007-07-104-0/+58
| | | | | | | Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] PMC MSP71xx core platformMarc St-Jean2007-07-106-0/+1414
| | | | | | | Patch to add core platform support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Removes the few leftovers of the MOMENCO_JAGUAR_ATX removal.Adrian Bunk2007-07-101-8/+6
| | | | | Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] New files for lemote fulong mini-PC supportSongmao Tian2007-07-104-1/+90
| | | | | | Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Songmao Tian <tiansm@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang2007-07-103-1/+12
| | | | | Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Convert init_thread initialization to ISO C initializers.Ralf Baechle2007-07-101-37/+53
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Enable support for the userlocal hardware registerRalf Baechle2007-07-104-1/+12
| | | | | | | | Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] FP affinity: Coding style cleanups Ralf Baechle2007-07-101-7/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Put an end to <asm/serial.h>'s long and annyoing existenceRalf Baechle2007-07-101-110/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove Momenco Ocelot C supportFranck Bui-Huu2007-07-103-29/+3
| | | | | | | | | | | | | | | | | | | Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/configs/ocelot_c_defconfig delete mode 100644 arch/mips/momentum/ocelot_c/Makefile delete mode 100644 arch/mips/momentum/ocelot_c/cpci-irq.c delete mode 100644 arch/mips/momentum/ocelot_c/dbg_io.c delete mode 100644 arch/mips/momentum/ocelot_c/irq.c delete mode 100644 arch/mips/momentum/ocelot_c/ocelot_c_fpga.h delete mode 100644 arch/mips/momentum/ocelot_c/platform.c delete mode 100644 arch/mips/momentum/ocelot_c/prom.c delete mode 100644 arch/mips/momentum/ocelot_c/reset.c delete mode 100644 arch/mips/momentum/ocelot_c/setup.c delete mode 100644 arch/mips/momentum/ocelot_c/uart-irq.c delete mode 100644 arch/mips/pci/fixup-ocelot-c.c delete mode 100644 arch/mips/pci/pci-ocelot-c.c
* [MIPS] PCI: Make dev pointer argument of pcibios_map_irq const.Ralf Baechle2007-07-101-1/+1
| | | | | | | This is to break the code of people who think they are supposed to scribble into the pci device structure - it's off limits. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] EV64120: Remove supportYoichi Yuasa2007-07-103-87/+0
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove unused watchpoint support and arch/mips/lib-{32,64}Atsushi Nemoto2007-07-101-35/+0
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix PHYS_OFFSET for 64-bits kernels with 32-bits symbolsFranck Bui-Huu2007-07-101-4/+8
| | | | | | | | | | | | | | | | | | | The current implementation of __pa() for 64-bits kernels with 32-bits symbols is broken. In this configuration, we need 2 values for PAGE_OFFSET, one in XKPHYS and the other in CKSEG0 space. When the value in CKSEG0 space is used, it doesn't take into account of PHYS_OFFSET. Even worse we can't redefine this value. The patch restores CPHYSADDR() but in __pa()'s implementation because it removes the need of 2 PAGE_OFFSET. OTOH, CPHYSADDR() is quite bad when dealing with mapped kernels. So this patch assumes there's no need to deal with such kernel in 64-bits world. Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Move PHY_OFFSET definition in spaces.hFranck Bui-Huu2007-07-102-9/+9
| | | | | Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Make PAGE_OFFSET aware of PHYS_OFFSETFranck Bui-Huu2007-07-101-1/+1
| | | | | | | | | | | For platforms that use PHYS_OFFSET and do not use a mapped kernel, this patch automatically adds PHYS_OFFSET into PAGE_OFFSET. Therefore there are no more needs for them to redefine PAGE_OFFSET. For mapped kernel, they need to redefine PAGE_OFFSET anyways. Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Clean up asm-mips/mach-generic/spaces.hFranck Bui-Huu2007-07-101-38/+27
| | | | | | | | | | | | | PAGE_OFFSET definition is now using CAC_BASE by default. This patch also reorder some macros to make them appear in the same order for both 32 and 64 bits configs. It also makes use of const.h generic header file to annotate constants. Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Allow generic spaces.h to be included by platform specific onesFranck Bui-Huu2007-07-104-73/+23
| | | | | | | | | | | | | | | | | | | | | Before this patch, when a platform needed to customize one constant in spaces.h, they need to redefine all of them. Now they can just redefine one constant and include the generic file header at the end: #include <asm/mach-generic/spaces.h> This patch doesn't allow to redefine CAC_BASE, IO_BASE and UNCAC_BASE for 32 bits platforms because there's no need to do so. This will avoid some macro duplications. It's important specially if we'll add complex macros. Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 include/asm-mips/mach-ip32/spaces.h
* [MIPS] MIPSsim: Move code away from the other MIPS Inc. BSP code.Ralf Baechle2007-07-101-0/+0
| | | | | | It shares no code at all. While at it also fix up the beginning bitrot. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Cleanup TO_PHYS_MASK definitionRalf Baechle2007-07-101-23/+6
| | | | | | | | | No point in adding yet another #ifdef for Loongson since all this mask is being used for is converting an XKPHYS address into a physical address anyway. So replace all definitions by one with the highest architectural possible value. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add generic GPIO to Au1x00Florian Fainelli2007-07-102-20/+69
| | | | | | | | | | This patch adds support for the generic GPIO API to Au1x00 boards. It requires the generic GPIO patch for MIPS boards by Yoichi Yuasa. Now there is a MIPS target using it, can you queue these patchset for 2.6.22 ? Thank you very much in advance. Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Create fallback gpio.hAtsushi Nemoto2007-07-101-0/+15
| | | | | | | Create fallback gpio.h which only contains prototypes for gpio API. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add generic GPIO supportYoichi Yuasa2007-07-101-0/+6
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove unused cpu_callout_map and num_booting_cpus()Adrian Bunk2007-07-101-7/+0
| | | | | Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] "extern inline" -> "static inline"Adrian Bunk2007-07-101-1/+1
| | | | | | | | "extern inline" will have different semantics with gcc 4.3, and "static inline" is correct here. Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] remove unused definitions for CobaltYoichi Yuasa2007-07-101-5/+0
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips au1xxx_ide.h: use NULL as firmware-revision wildcardJunio C Hamano2007-07-091-14/+14
| | | | | | | | | | This updates the DMA whitelist in MIPS specific au1xxx ide driver to use NULL instead of "ALL" as the wildcard. Signed-off-by: Junio C Hamano <junkio@cox.net> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Dave Jones <davej@redhat.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
* [MIPS] Fix scheduling latency issue on 24K, 34K and 74K coresRalf Baechle2007-07-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | The idle loop goes to sleep using the WAIT instruction if !need_resched(). This has is suffering from from a race condition that if if just after need_resched has returned 0 an interrupt might set TIF_NEED_RESCHED but we've just completed the test so go to sleep anyway. This would be trivial to fix by just disabling interrupts during that sequence as in: local_irq_disable(); if (!need_resched()) __asm__("wait"); local_irq_enable(); but the processor architecture leaves it undefined if a processor calling WAIT with interrupts disabled will ever restart its pipeline and indeed some processors have made use of the freedom provided by the architecture definition. This has been resolved and the Config7.WII bit indicates that the use of WAIT is safe on 24K, 24KE and 34K cores. It also is safe on 74K starting revision 2.1.0 so enable the use of WAIT with interrupts disabled for 74K based on a c0_prid of at least that. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add macros to encode processor revisions.Ralf Baechle2007-07-061-0/+11
| | | | | | | | | Older processors used to encode processor version and revision in two 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores have switched to use the 8-bits as 3:3:2 bitfield with the last field as the patch number. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] RM7000: Enable ICACHE_REFILLS_WORKAROUND_WAR.Ralf Baechle2007-07-061-7/+11
| | | | | | | | | | | | The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra opposes it being called that) where invalid instructions in the same I-cache line worth of instructions being fetched may case spurious exceptions. The workaround for this was only enabled for E9000 cores; enable it also for all RM7000-based platforms. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] 64-bit TO_PHYS_MASK macro for RM9000 processorsAndrew Sharp2007-07-061-0/+1
| | | | | Signed-off-by: Andrew Sharp <tigerand@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add whitelists for checksyscalls.shAtsushi Nemoto2007-07-041-0/+16
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] die(): Properly declare as non-returningMaciej W. Rozycki2007-07-041-1/+1
| | | | | | | | | This marks the declaration of die() correctly, removing "control reaches end of non-void function" warnings from non-void functions that die() at the end. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix include wrapper symbol definitions in IP32 code.Kumba2007-07-041-3/+3
| | | | | | | Some IP35 defines snuck into some IP32-specific code during the DMA re-write. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC and non-SMTC kernel and modules are incompatibleRalf Baechle2007-06-261-1/+8
| | | | | | So don't allow mixing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove a duplicated local variable in test_and_clear_bit()Atsushi Nemoto2007-06-261-1/+1
| | | | | | | | | | Fix a sparse warning caused by 2c921d07f8c641e691b0dfd80a5cfe14c60ec489 include2/asm/bitops.h:313:23: warning: symbol 'res' shadows an earlier one include2/asm/bitops.h:309:16: originally declared here Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] use compat_siginfo in rt_sigframe_n32Pavel Kiryukhin2007-06-261-0/+62
| | | | | Signed-off-by: Pavel Kiryukhin <vksavl@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Don't drag a platform specific header into generic arch code.Ralf Baechle2007-06-205-23/+9
| | | | | | | | For some platforms it's definitions may conflict. So that's the one-liner. The rest is 10 square kilometers of collateral damage fixup this include used to paper over. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Malta: Fix for SOCitSC based MaltasChris Dearman2007-06-142-3/+20
| | | | | | | And an attempt to tidy up the core/controller differences. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix smp barriers in test_and_{change,clear,set}_bitRalf Baechle2007-06-111-32/+19
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Wire up utimensat, signalfd, timerfd, eventfdAtsushi Nemoto2007-06-111-6/+18
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix KMODE for the R3000Maciej W. Rozycki2007-06-111-24/+28
| | | | | | | | | | | This must be the oldest bug that we have got. Leaving interrupts "as they are" for the R3000 obviously means copying IEp to IEc. Since we have got STATMASK now, I took this opportunity to mask the status register "correctly" for the R3000 now too. Oh, and the R3000 hardly ever is 64-bit. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Drop __ARCH_WANT_SYS_FADVISE64Atsushi Nemoto2007-06-061-1/+0
| | | | | | | | sys_fadvise64() is not used on MIPS. The libc can implement both posix_fadvise() and posix_fadvise64() using sys_fadvise64_64(). Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove duplicate fpu enable hazard code.Chris Dearman2007-06-061-15/+0
| | | | | | | Use common code from hazards.h instead. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Atlas, Malta, SEAD: Remove scroll from interrupt handler.Ralf Baechle2007-06-061-0/+1
| | | | | | | | Aside of being handy for debugging this has never been a particularly good idea but is now getting in the way of dyntick / tickless kernels and general cleanups. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Detach sched.h from mm.hAlexey Dobriyan2007-05-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First thing mm.h does is including sched.h solely for can_do_mlock() inline function which has "current" dereference inside. By dealing with can_do_mlock() mm.h can be detached from sched.h which is good. See below, why. This patch a) removes unconditional inclusion of sched.h from mm.h b) makes can_do_mlock() normal function in mm/mlock.c c) exports can_do_mlock() to not break compilation d) adds sched.h inclusions back to files that were getting it indirectly. e) adds less bloated headers to some files (asm/signal.h, jiffies.h) that were getting them indirectly Net result is: a) mm.h users would get less code to open, read, preprocess, parse, ... if they don't need sched.h b) sched.h stops being dependency for significant number of files: on x86_64 allmodconfig touching sched.h results in recompile of 4083 files, after patch it's only 3744 (-8.3%). Cross-compile tested on all arm defconfigs, all mips defconfigs, all powerpc defconfigs, alpha alpha-up arm i386 i386-up i386-defconfig i386-allnoconfig ia64 ia64-up m68k mips parisc parisc-up powerpc powerpc-up s390 s390-up sparc sparc-up sparc64 sparc64-up um-x86_64 x86_64 x86_64-up x86_64-defconfig x86_64-allnoconfig as well as my two usual configs. Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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