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* [IA64] Move include/asm-ia64 to arch/ia64/include/asmTony Luck2008-08-011-905/+0
| | | | | | | | | | | | | | | After moving the the include files there were a few clean-ups: 1) Some files used #include <asm-ia64/xyz.h>, changed to <asm/xyz.h> 2) Some comments alerted maintainers to look at various header files to make matching updates if certain code were to be changed. Updated these comments to use the new include paths. 3) Some header files mentioned their own names in initial comments. Just deleted these self references. Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Kernel parameter for max number of concurrent global TLB purgesFenghua Yu2008-04-041-0/+4
| | | | | | | | | The patch defines kernel parameter "nptcg=". The parameter overrides max number of concurrent global TLB purges which is reported from either PAL_VM_SUMMARY or SAL PALO. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Multiple outstanding ptc.g instruction supportFenghua Yu2008-04-041-0/+17
| | | | | | | | | | | | | | | | | | | | According to SDM2.2, Itanium supports multiple outstanding ptc.g instructions. But current kernel function ia64_global_tlb_purge() uses a spinlock to serialize ptc.g instructions issued by multiple processors. This serialization might have scalability issue on a big SMP machine where many processors could purge TLB in parallel. The patch fixes this problem by issuing multiple ptc.g instructions in ia64_global_tlb_purge(). It also adds support for the "PALO" table to get a platform view of the max number of outstanding ptc.g instructions (which may be different from the processor view found from PAL_VM_SUMMARY). PALO specification can be found at: http://www.dig64.org/home/DIG64_PALO_R1_0.pdf spinaphore implementation by Matthew Wilcox. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] workaround tiger ia64_sal_get_physical_id_info hangAlex Chiang2008-03-041-0/+4
| | | | | | | | | | | | | | | | | This fixes regression introduced in 113134fcbca83619be4c68d0ca66db6093777b5d Intel Tiger platforms hang when calling SAL_GET_PHYSICAL_ID_INFO instead of properly returning -1 for unimplemented, so add a version check. SGI Altix platforms have an incorrect SAL version hard-coded into their prom -- they encode 2.9, but actually implement 3.2 -- so fix it up and allow ia64_sal_get_physical_id_info to keep working. Signed-off-by: Alex Chiang <achiang@hp.com> Acked-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Export three symbols for module useZhang, Xiantao2008-02-041-11/+3
| | | | | | | | Since kvm/module needs to use some unexported functions in kernel, so export them with this patch. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] abstract SAL_CALL wrapper to allow other firmware entry pointsBjorn Helgaas2007-10-121-6/+9
| | | | | | | | | | | | | | | SAL_CALL() always calls through the ia64_sal function pointer. I am adding new functionality that needs the same conventions as SAL_CALL (FP regs saved/restored, sal_lock acquired, etc), but doesn't use the ia64_sal function pointer. This patch pulls the body of SAL_CALL out into a new "IA64_FW_CALL" that takes care of these calling conventions, but allows the caller to specify either ia64_sal or some other firmware entry point. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] whitespace fixes for include/asm-ia64/sal.hHorms2007-03-081-2/+3
| | | | | | | | * Make use of spaces and tabs consistent * Make long line < 80col Signed-off-by: Simon Horman <horms@verge.net.au> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] move SAL_CACHE_FLUSH check later in bootTroy Heber2006-10-311-0/+1
| | | | | | | | | | | The check to see if the firmware drops interrupts during a SAL_CACHE_FLUSH is done to early in the boot. SAL_CACHE_FLUSH expects to be able to make PAL calls in virtual mode, on some cell based machines a fault occurs causing a MCA. This patch moves the check after mmu_context_init so the TLB and VHPT are properly setup. Signed-off-by Troy Heber <troy.heber@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] avoid broken SAL_CACHE_FLUSH implementationsBjorn Helgaas2006-02-021-9/+1
| | | | | | | | | | | | | If SAL_CACHE_FLUSH drops interrupts, complain about it and fall back to using PAL_CACHE_FLUSH instead. This is to work around a defect in HP rx5670 firmware: when an interrupt occurs during SAL_CACHE_FLUSH, SAL drops the interrupt but leaves it marked "in-service", which leaves the interrupt (and others of equal or lower priority) masked. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Split 16-bit severity field in sal_log_record_headerTony Luck2005-12-131-1/+2
| | | | | | | | | | ERR_SEVERITY item is defined as a 8 bits item in SAL documentation ($B.2.1 rev december 2003), but as an u16 in sal.h. This has the side effect that current code in mca.c may not call ia64_sal_clear_state_info() upon receiving corrected platform errors if there are bits set in the validation byte. Reported by Xavier Bru. Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] multi-core/multi-thread identificationSuresh Siddha2005-04-251-0/+12
| | | | | | | | | | | | | | | | | | | | | | Version 3 - rediffed to apply on top of Ashok's hotplug cpu patch. /proc/cpuinfo output in step with x86. This is an updated MC/MT identification patch based on the previous discussions on list. Add the Multi-core and Multi-threading detection for IPF. - Add new core and threading related fields in /proc/cpuinfo. Physical id Core id Thread id Siblings - setup the cpu_core_map and cpu_sibling_map appropriately - Handles Hot plug CPU Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Gordon Jin <gordon.jin@intel.com> Signed-off-by: Rohit Seth <rohit.seth@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] cpu hotplug: return offlined cpus to SALAshok Raj2005-04-221-0/+38
| | | | | | | | | | | | | | | | This patch is required to support cpu removal for IPF systems. Existing code just fakes the real offline by keeping it run the idle thread, and polling for the bit to re-appear in the cpu_state to get out of the idle loop. For the cpu-offline to work correctly, we need to pass control of this CPU back to SAL so it can continue in the boot-rendez mode. This gives the SAL control to not pick this cpu as the monarch processor for global MCA events, and addition does not wait for this cpu to checkin with SAL for global MCA events as well. The handoff is implemented as documented in SAL specification section 3.2.5.1 "OS_BOOT_RENDEZ to SAL return State" Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-161-0/+840
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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