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* [ARM] add Marvell 78xx0 ARM SoC supportStanislav Samsonov2008-06-2212-0/+436
| | | | | | | | | | | | | | | | | | | The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring (depending on the model) one or two Feroceon CPU cores with 512K of L2 cache and VFP coprocessors running at (depending on the model) between 800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe interfaces that can each run either in x4 or quad x1 mode, three USB 2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI interface, four UARTs, and depending on the model, two or four gigabit ethernet interfaces. This patch adds basic support for the platform, and allows booting on the MV78x00 development board, with functional UARTs, SATA, PCIe, GigE and USB ports. Signed-off-by: Stanislav Samsonov <samsonov@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: PCIe x4/x1 detection supportLennert Buytenhek2008-06-221-0/+1
| | | | | | | | | | The Discovery Duo (MV78xx0) has two x4 PCIe ports which can either be used in x4 mode or in quad x1 mode. This patch adds an accessor function to the generic plat-orion PCIe handling code to detect in which of the two modes we're running (which is determined by strap pins and/or configured by the bootloader). Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] add Marvell Kirkwood (88F6000) SoC supportSaeed Bishara2008-06-2212-0/+384
| | | | | | | | | | | | | | | | | | | | The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface, a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS interface, and IDMA/XOR engines, and depending on the model, also features one or two Gigabit Ethernet interfaces, two SATA II interfaces, one or two TWSI interfaces, one or two UARTs, a TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and an SDIO interface. This patch adds supports for the Marvell DB-88F6281-BP Development Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs, enabling support for the PCIe interface, the USB interface, the ethernet interfaces, the SATA interfaces, the TWSI interfaces, the UARTs, and the NAND controller. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Feroceon: L2 cache supportLennert Buytenhek2008-06-222-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the unified Feroceon L2 cache controller as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo families of ARM SoCs. Note that: - Page table walks are outer uncacheable on Kirkwood and Discovery Duo, since the ARMv5 spec provides no way to indicate outer cacheability of page table walks (specifying it in TTBR[4:3] is an ARMv6+ feature). This requires adding L2 cache clean instructions to proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to tlbflush.h ({flush,clean}_pmd_entry()). The latter case is handled by defining a new TLB type (TLB_FEROCEON) which is almost identical to the v4wbi one but provides a TLB_L2CLEAN_FR flag. - The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2 range by MVA' and 'invalidate L2 range by MVA') operations, and this patch uses those range operations for all Linux outer cache operations, as they are faster than the regular per-line operations. L2 range operations are not interruptible on this hardware, which avoids potential livelock issues, but can be bad for interrupt latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which allows you to select the maximum range size to operate on at once. (Valid range is between one cache line and one 4KiB page, and must be a multiple of the line size.) Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Feroceon: L1 cache range operation supportStanislav Samsonov2008-06-221-5/+1
| | | | | | | | | | | This patch adds support for the L1 D cache range operations that are supported by the Marvell Discovery Duo and Marvell Kirkwood ARM SoCs. Signed-off-by: Stanislav Samsonov <samsonov@marvell.com> Acked-by: Saeed Bishara <saeed@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] add Marvell Loki (88RC8480) SoC supportLennert Buytenhek2008-06-2212-0/+361
| | | | | | | | | | | | | | The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU core running at between 400 MHz and 1.0 GHz, and features a 64 bit DDR controller, 512K of internal SRAM, two x4 PCI-Express ports, two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs, two TWSI controllers, and IDMA/XOR engines. This patch adds support for the Marvell LB88RC8480 Development Board, enabling the use of the PCIe interfaces, the ethernet interfaces, the TWSI interfaces and the UARTs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR defineKe Wei2008-06-221-0/+1
| | | | | | | | | | | | Some Feroceon-based SoCs have an MBUS bridge interrupt controller that requires writing a one instead of a zero to clear edge interrupt sources such as timer expiry. This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: nuke orion5x_{read,write}Lennert Buytenhek2008-06-221-5/+2
| | | | | | Nuke the Orion-specific orion5x_{read,write} wrappers. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: use linux/serial_reg.h for Orion uncompress.hLennert Buytenhek2008-06-221-7/+22
| | | | Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: add 88F5181L (Orion-VoIP) supportLennert Buytenhek2008-06-221-2/+4
| | | | | Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <linux@arm.linux.org.uk>
* [ARM] Orion: delete unused IO_SPACE_REMAP defineLennert Buytenhek2008-06-221-1/+0
| | | | | | | This define isn't used anywhere in the kernel tree -- nuke it. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <linux@arm.linux.org.uk>
* [ARM] cache align destination pointer when copying memory for some processorsNicolas Pitre2008-06-221-0/+15
| | | | | | | | | | | | | | | The implementation for memory copy functions on ARM had a (disabled) provision for aligning the source pointer before loading registers with data. Turns out that aligning the _destination_ pointer is much more useful, as the read side is already sufficiently helped with the use of preload. So this changes the definition of the CALGN() macro to target the destination pointer instead, and turns it on for Feroceon processors where the gain is very noticeable. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] 5091/1: Add missing bitfield include to regs-lcd.hStefan Schmidt2008-06-121-1/+4
| | | | | | | | | | | Macros like Fld() or FShft used in regs-lcd.h are defined in bitfield.h, but the latter is not included. Also fix one whitespace issue while being there. Signed-off-by: Antonio Ospite <ao2@openezx.org> Signed-off-by: Stefan Schmidt <stefan@datenfreihafen.org> Acked-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5067/1: _raw_write_can_lock macro bugfixsurinder2008-06-021-1/+1
| | | | | | | | | | | The current __raw_write_can_lock macro tests whether the lock can be locked by checking if it is equal to 0x80000000, whereas the lock should be lockable if its value is 0 i.e. unlocked state is represented by 0. Hence the macro should test the value of lock against 0 and not 0x80000000. Signed-off-by: Surinder Pal Singh <srplsnh@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5070/1: pxa: add GPIO104_PSKTSEL to pxa27x MFP configurationPhilipp Zabel2008-06-021-0/+1
| | | | | | | | | PSKTSEL can be routed to GPIO pin 104. This configuration is used by HP iPAQ hx4700. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Acked-by: Jrgen Schindele <linux@schindele.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5068/1: PXA2xx Additional gpio definitionsJonathan Cameron2008-06-021-0/+9
| | | | | | | | | Some additional alternate gpio definitions relating to FFUART and USB on the pxa27x. These are used on the xbow imote2 platform. Signed-off-by: Jonathan Cameron <jic23@cam.ac.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5060/1: remove unnecessary include of asm/io.hGreg Ungerer2008-06-011-1/+0
| | | | | | | Remove unnecessary include of asm/io.h. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] fix AT91 include loopsRussell King2008-06-011-2/+0
| | | | | | | | | | | | | | | | | AT91 has one include loop in its header files: include/asm-arm/io.h <- include/asm-arm/arch-at91/io.h <- include/asm-arm/io.h Circular include dependencies are dangerous since they can result in inconsistent definitions being provided to other code, especially if '#ifndef' constructs are used. Solve this by removing the offending includes. Built tested using my AT91 configuration. Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] fix OMAP include loopsRussell King2008-05-234-4/+1
| | | | | | | | | | | | | | | | | | | | | OMAP has two include loops in its header files: asm-arm/hardware.h <- asm-arm/arch-omap/io.h <- asm-arm/arch-omap/hardware.h <- asm-arm/hardware.h asm-arm/arch-omap/board-palmte.h <- asm-arm/arch-omap/hardware.h <- asm-arm/hardware.h <- asm-arm/arch-omap/gpio.h <- asm-arm/arch-omap/board-palmte.h Circular include dependencies are dangerous since they can result in inconsistent definitions being provided to other code, especially if '#ifndef' constructs are used. Solve these by removing the offending includes, and add additional includes where necessary. Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5053/1: define before use of processor_idGreg Ungerer2008-05-231-14/+15
| | | | | | | | | For the simple read_cpuid() macro case the variable processor_id has no definition on use of the macro. Add an extern for it. Move all the processor ID macros into the #ifndef __ASSEMBLEY__ block. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5051/1: define pgtable_t for the !CONFIG_MMU case tooGreg Ungerer2008-05-231-2/+2
| | | | | | | | The non-MMU case also needs the type definition of pgtable_t. So move it out of a CONFIG_MMU conditional section. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: fix omap clk support build errorsRussell King2008-05-221-0/+5
| | | | | | | | | | arch/arm/plat-omap/clock.c:397: warning: "struct cpufreq_frequency_table" declared inside parameter list arch/arm/plat-omap/clock.c:397: warning: its scope is only this definition or declaration, which is probably not what you want arch/arm/plat-omap/clock.c: In function `clk_init_cpufreq_table': arch/arm/plat-omap/clock.c:402: error: structure has no member named `clk_init_cpufreq_table' arch/arm/plat-omap/clock.c:403: error: structure has no member named `clk_init_cpufreq_table' Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5025/2: fix collie cpu initialisationThomas Kunze2008-05-221-0/+4
| | | | | | | | | | collie.h: * add some meaningfull names to some gpios collie.c: * initialize cpu registers correctly Signed-off-by: Thomas Kunze <thommycheck@gmx.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'omap-fixes' of ↵Russell King2008-05-172-9/+19
|\ | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
| * ARM: OMAP: Add calls to omap2_set_globals_*()Paul Walmsley2008-05-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the omap2_set_globals_{242x,243x,343x}() functions. These functions are called early upon boot in the map_io() functions in the board-specific init files. This patch was accidentally left out of the earlier series. This fixes omap2 booting as noted by Kyungmin Park <kmpark@infradead.org>. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kyungmin Park <kmpark@infradead.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: OMAP: Update MMC header to fix compileTony Lindgren2008-05-091-9/+15
| | | | | | | | | | | | | | Update MMC header from linux-omap tree to match the recent MMC driver updates. Signed-off-by: Tony Lindgren <tony@atomide.com>
* | Merge branch 'sa1100'Russell King2008-05-172-9/+12
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| * | [ARM] 5026/1: locomo: add .settype for gpio and several small fixesThomas Kunze2008-05-172-9/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | irqs.h: * rename IRQ_LOCOMO_SPI_OVRN to IRQ_LOCOMO_SPI_REND locomo.h: * add some definition for locomo spi controller * correct some errors locomo.c: * correct some errors * add set_type for locomo gpio irq chip Signed-off-by: Thomas Kunze <thommycheck@gmx.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] fix parenthesis in include/asm-arm/arch-omap/control.hMariusz Kozlowski2008-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Parenthesis fix in include/asm-arm/arch-omap/control.h Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] pxa: Fix RCSR handlingRussell King2008-05-081-1/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | Related to d3930614e68bdf83a120d904c039a64e9f75dba1. RCSR is only present on PXA2xx CPUs, not on PXA3xx CPUs. Therefore, we should not be unconditionally writing to RCSR from generic code. Since we now clear the RCSR status from the SoC specific PXA PM code and before reset in the arch_reset() function, the duplication in the corgi, poodle, spitz and tosa code can be removed. Acked-by: Richard Purdie <rpurdie@rpsys.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 5027/1: Fixed random memory corruption on pxa suspend cycle.Robert Jarzmik2008-05-041-1/+1
|/ | | | | | | | | | | Each time a pxa type cpu went in suspend, a portion of kmalloc memory was corrupted. The issue was an incorrect length allocation introduced by the commit 711be5ccfe9a02ba560aa918a008c31ea4760163 for the save registers array (=> overflow). Signed-off-by: Robert Jarzmik <rjarzmik@free.fr> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* arm: types: use <asm-generic/int-*.h> for the arm architectureH. Peter Anvin2008-05-021-31/+2
| | | | | | | | | | This modifies <asm-arm/types.h> to use the <asm-generic/int-*.h> generic include files. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Lennert Buytenhek <kernel@wantstofly.org> Cc: Ben Dooks <ben-linux@fluff.org>
* rename div64_64 to div64_u64Roman Zippel2008-05-011-2/+0
| | | | | | | | | | | | | | | | | | | | | Rename div64_64 to div64_u64 to make it consistent with the other divide functions, so it clearly includes the type of the divide. Move its definition to math64.h as currently no architecture overrides the generic implementation. They can still override it of course, but the duplicated declarations are avoided. Signed-off-by: Roman Zippel <zippel@linux-m68k.org> Cc: Avi Kivity <avi@qumranet.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: David Howells <dhowells@redhat.com> Cc: Jeff Dike <jdike@addtoit.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Patrick McHardy <kaber@trash.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* pxafb: preliminary smart panel interface supportEric Miao2008-04-302-4/+56
| | | | | | | | | Signed-off-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Eric Miao <eric.miao@marvell.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* pxafb: introduce register independent LCD connection type for pxafberic miao2008-04-301-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | Reasons: 1. straight forward: the name "LCD_COLOR_DSTN_16BPP" is much better than "LCCR0_Pas | LCCR0_Color | LCCR0_Dual" 2. by defining LCD connection types as constants, it allows only valid possibilities 3. by removing the dependency of register bits definitions, those can be later moved into the body of pxafb.c, instead of having a regs-lcd.h around Currently, only lubbock, mainstone, zylonite and littleton have been modified to support these types (see coming patches after this). Other platforms are encouraged to change their way describing the LCD controller connections. Signed-off-by: eric miao <eric.miao@marvell.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* pxafb: convert fb driver to use ioremap() and __raw_{readl, writel}eric miao2008-04-303-196/+140
| | | | | | | | | | | | | | | | | | This is part of the effort moving peripheral registers outside of pxa-regs.h, and using ioremap() make it possible the same IP can be re-used on different processors with different registers space As a result, the fixed mapping in pxa_map_io() is removed. The regs-lcd.h can actually moved to where closer to pxafb.c but some of its bit definitions are directly used by various platform code, though this is not a good style. Signed-off-by: eric miao <eric.miao@marvell.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2008-04-295-55/+18
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: (26 commits) [ARM] pxa: fix 1c104e0e4f6ab396960c058e95e18bdedcac945b [ARM] serial: s3c2410: platform_get_irq() may return signed unnoticed [ARM] am79c961a: platform_get_irq() may return signed unnoticed [ARM] Feroceon: Feroceon-specific WA-cache compatible {copy,clear}_user_page() [ARM] Feroceon: fix function alignment in proc-feroceon.S [ARM] Orion: catch a couple more alternative spellings of PCIe [ARM] Orion: fix orion-ehci platform resource end addresses [ARM] Orion: fix ->map_irq() PCIe bus number check [ARM] Orion: fix ioremap() optimization [ARM] feroceon: remove CONFIG_CPU_CACHE_ROUND_ROBIN check [ARM] feroceon: remove CONFIG_CPU_DCACHE_WRITETHROUGH check kprobes/arm: fix decoding of arithmetic immediate instructions kprobes/arm: fix cache flush address for instruction stub [ARM] 5022/1: Race in ARM MMCI PL18x driver, V2 [ARM] 5021/1: at91: buildfix for sam9263 + PM [ARM] 5018/1: RealView: Fix the ARM11MPCore Oprofile compilation [ARM] 5016/1: AT91: typo in mci configuration for at91cap at91sam9263 [ARM] 5017/1: pxa3xx: Report unsupported wakeup sources in pxa3xx_set_wake() [ARM] 5020/1: magician: remove __devinit marker from pasic3_leds_info [ARM] 5014/1: Cleanup reset state before entering suspend or resetting. ...
| * Merge branch 'orion-fixes2'Russell King2008-04-291-0/+8
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| | * [ARM] Feroceon: Feroceon-specific WA-cache compatible {copy,clear}_user_page()Lennert Buytenhek2008-04-281-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a set of Feroceon-specific {copy,clear}_user_page() routines that perform more optimally than the generic implementations. This also deals with write-allocate caches (Feroceon can run L1 D in WA mode) which otherwise prevents Linux from booting. [nico: optimized the code even further] Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Tested-by: Sylver Bruneau <sylver.bruneau@googlemail.com> Tested-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
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| *-. \ Merge branches 'pxa' and 'orion-fixes1'Russell King2008-04-294-55/+10
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| | | * [ARM] Orion: fix ioremap() optimizationNicolas Pitre2008-04-281-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ioremap() optimization used for internal register didn't cope with the fact that paddr + size can wrap to zero if the area extends to the end of the physical address space. Issue isolated by Sylver Bruneau <sylver.bruneau@googlemail.com>. Signed-off-by: Nicolas Pitre <nico@marvell.com>
| | * | [ARM] 5014/1: Cleanup reset state before entering suspend or resetting.Dmitry Baryshkov2008-04-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel should clean stale bits from reset status, so that they won't confuse the bootloader. Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | [ARM] 5013/1: Change ITE8152 interrupt numbersMike Rapoport2008-04-241-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch kills the use of IRQ_GPIO() and adds #if NR_IRQS < (IT8152_LAST_IRQ+1) statement. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | [ARM] 5009/1: magician: remove to-be-deprecated defines for pxa_gpio_modePhilipp Zabel2008-04-211-49/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alternate function and direction setting is now handled by the MFP config code or the generic GPIO API. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | kernel: Move arches to use common unaligned accessHarvey Harrison2008-04-291-168/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unaligned access is ok for the following arches: cris, m68k, mn10300, powerpc, s390, x86 Arches that use the memmove implementation for native endian, and the byteshifting for the opposite endianness. h8300, m32r, xtensa Packed struct for native endian, byteshifting for other endian: alpha, blackfin, ia64, parisc, sparc, sparc64, mips, sh m86knommu is generic_be for Coldfire, otherwise unaligned access is ok. frv, arm chooses endianness based on compiler settings, uses the byteshifting versions. Remove the unaligned trap handler from frv as it is now unused. v850 is le, uses the byteshifting versions for both be and le. Remove the now unused asm-generic implementation. Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Acked-by: David S. Miller <davem@davemloft.net> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | | mm: introduce pte_special pte bitNick Piggin2008-04-281-0/+3
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | s390 for one, cannot implement VM_MIXEDMAP with pfn_valid, due to their memory model (which is more dynamic than most). Instead, they had proposed to implement it with an additional path through vm_normal_page(), using a bit in the pte to determine whether or not the page should be refcounted: vm_normal_page() { ... if (unlikely(vma->vm_flags & (VM_PFNMAP|VM_MIXEDMAP))) { if (vma->vm_flags & VM_MIXEDMAP) { #ifdef s390 if (!mixedmap_refcount_pte(pte)) return NULL; #else if (!pfn_valid(pfn)) return NULL; #endif goto out; } ... } This is fine, however if we are allowed to use a bit in the pte to determine refcountedness, we can use that to _completely_ replace all the vma based schemes. So instead of adding more cases to the already complex vma-based scheme, we can have a clearly seperate and simple pte-based scheme (and get slightly better code generation in the process): vm_normal_page() { #ifdef s390 if (!mixedmap_refcount_pte(pte)) return NULL; return pte_page(pte); #else ... #endif } And finally, we may rather make this concept usable by any architecture rather than making it s390 only, so implement a new type of pte state for this. Unfortunately the old vma based code must stay, because some architectures may not be able to spare pte bits. This makes vm_normal_page a little bit more ugly than we would like, but the 2 cases are clearly seperate. So introduce a pte_special pte state, and use it in mm/memory.c. It is currently a noop for all architectures, so this doesn't actually result in any compiled code changes to mm/memory.o. BTW: I haven't put vm_normal_page() into arch code as-per an earlier suggestion. The reason is that, regardless of where vm_normal_page is actually implemented, the *abstraction* is still exactly the same. Also, while it depends on whether the architecture has pte_special or not, that is the only two possible cases, and it really isn't an arch specific function -- the role of the arch code should be to provide primitive functions and accessors with which to build the core code; pte_special does that. We do not want architectures to know or care about vm_normal_page itself, and we definitely don't want them being able to invent something new there out of sight of mm/ code. If we made vm_normal_page an arch function, then we have to make vm_insert_mixed (next patch) an arch function too. So I don't think moving it to arch code fundamentally improves any abstractions, while it does practically make the code more difficult to follow, for both mm and arch developers, and easier to misuse. [akpm@linux-foundation.org: build fix] Signed-off-by: Nick Piggin <npiggin@suse.de> Acked-by: Carsten Otte <cotte@de.ibm.com> Cc: Jared Hulbert <jaredeh@gmail.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | ide: add struct ide_io_ports (take 3)Bartlomiej Zolnierkiewicz2008-04-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add struct ide_io_ports and use it instead of `unsigned long io_ports[]` in ide_hwif_t. * Rename io_ports[] in hw_regs_t to io_ports_array[]. * Use un-named union for 'unsigned long io_ports_array[]' and 'struct ide_io_ports io_ports' in hw_regs_t. * Remove IDE_*_OFFSET defines. v2: * scc_pata.c build fix from Stephen Rothwell. v3: * Fix ctl_adrr typo in Sparc-specific part of ns87415.c. (Noticed by Andrew Morton) Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
* | | [MTD] [NAND] S3C2410 Allow ECC disable to be specified by the boardBen Dooks2008-04-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add support to disable ECC checking for a given chip when passed by the board via the platform data. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: David Woodhouse <dwmw2@infradead.org>
* | | [MTD] [NAND] S3C2410 Allow ECC layout to be passed through platform dataBen Dooks2008-04-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add support for the ECC layout to be passed via the platform data specified by the board. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: David Woodhouse <dwmw2@infradead.org>
* | | [MTD] [NAND] S3C2410 Allow unset ecc to be ignored for ecc correctionBen Dooks2008-04-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a block's ecc field is all 0xff, then ignore the ECC correction. This is for systems where some of the blocks, such as the initial cramfs are written without ECC and need to be loaded on start. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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