Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | video: exynos_dp: Fix incorrect setting for INT_CTL | Ajay Kumar | 2012-11-29 | 1 | -1/+2 |
* | video: exynos_dp: increase AUX channel voltage level | Jingoo Han | 2012-09-22 | 1 | -1/+1 |
* | video: exynos_dp: add bit-masking for LINK_TRAINING_CTL register | Jingoo Han | 2012-09-22 | 1 | -0/+1 |
* | video: exynos_dp: add analog and pll control setting | Jingoo Han | 2012-04-16 | 1 | -0/+29 |
* | video: support DP controller driver | Jingoo Han | 2012-02-13 | 1 | -0/+335 |