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path: root/drivers/video/da8xx-fb.c
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* video: da8xx-fb: remove unwanted defineManish Badarkhe2013-10-301-1/+0
| | | | | | | Remove unwanted define "WSI_TIMEOUT" present in code. Signed-off-by: Manish Badarkhe <badarkhe.manish@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* Video / da8xx-fb: Use module_platform_driver() to simplify codeHanjun Guo2013-09-301-13/+1
| | | | | | | Convert to module_platform_driver() to simplify code. Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: Staticize reg_contextSachin Kamat2013-09-261-1/+1
| | | | | | | 'reg_context' is local to this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: use dev_get_platdata()Jingoo Han2013-09-201-2/+2
| | | | | | | | | Use the wrapper function for retrieving the platform data instead of accessing dev->platform_data directly. This is a cosmetic change to make the code simpler and enhance the readability. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: fix the polarities of the hsync/vsync pulseDarren Etheridge2013-08-301-2/+2
| | | | | | | | | The polarities were being set to active low when fbdev was requesting active high. This patch reverses it so that what is set into the LCD controller is correct. Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: support lcdc v2 timing register expansionDarren Etheridge2013-08-301-0/+15
| | | | | | | | | | | TI LCD controller version 2 adds some extra bits in a register to increase the available size to represent horizontal timings. This patch allows the fbdev driver to utilize those extra bits. This will become important for driving an HDMI encoder from the lcd controller where some of the VESA/CEA modes require quite large porches. Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: fixing timing off by one errorsDarren Etheridge2013-08-301-4/+4
| | | | | | | | | | | | The LCD controller represents some of the timing fields with a 0 in the register representing 1. This was not taken into account when these registers were being set. Interestingly enough not all of the LCDC controller timing registers implement this representation so carefully went through the technical reference manual to only "fix" the correct timings. Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb fixing incorrect porch mappingsDarren Etheridge2013-08-301-4/+4
| | | | | | | | | | | | | | | | The driver was mapping the wrong fbdev margins to the front porch / back porch for both vertical and horizontal timings. This patch corrects it so that: hfp = right margin hbp = left margin vbp = upper margin vfp = lower margin Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: let compiler decide what to inlineDarren Etheridge2013-08-091-9/+8
| | | | | | | | Remove use of explicit inline compiler directive and let the compiler make the decision as per Documentation/CodingStyle. Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: make clock naming consistentDarren Etheridge2013-08-091-12/+12
| | | | | | | | | Clean up the code, so that the names of the various clock variables are consistent to it is clear what variable is associated with what clock. Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: set upstream clock rate (if reqd)Darren Etheridge2013-08-091-20/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on original patch by: Afzal Mohammed <afzal@ti.com> LCDC IP has a clock divider to adjust pixel clock, this limits pixel clock range to fck/255 - fck/2(fck - rate of input clock to LCDC IP). In the case of AM335x, where this IP is present, default fck is not sufficient to provide normal pixel clock rates, hence rendering this driver unusable on AM335x. If input clock too is configurable, allowable range of pixel clock would increase. Here initially it is checked whether with present fck, divider in IP could be configured to obtain required rate, if not, fck is adjusted. This makes it usable on AM335x. Note: Another solution would be to model an inherited basic clock divider of CCF, an advantage would be a better possible resolution for pixel clk. And trying to instantiate a CCF clock would mean that to be consistent, 3 bits being turned on to enable clocks of LCDC IP would have to be modeled as gate clocks. Now that would bring in a total of 4 clocks, including necessity to create a new inherited divider clock, and that mean a branch of clock tree would be present in LCDC driver. This would add complexity to LCDC driver bringing in considerable amount of clock handling code, and this would not bring in much advantage for existing use cases other than providing a higher resolution of pixel clock. And existing use cases work without relying on clock modeling. Another fact is that out of the two platform's using this driver DaVinci is not yet converted to CCF. In future if higher resolution of pixel clock is required, and probably after DaVinci is CCF'ed, modeling clock nodes inside driver may be considered. v2: purely cosmetic changes to try and clarify what variables are being used for in the clock rate / divider calculations Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: reorganize panel detectionAfzal Mohammed2013-08-091-16/+26
| | | | | | | | | Move panel detection to a separate function, this helps in readability as well as makes DT support cleaner. Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: ensure non-null cfg in pdataAfzal Mohammed2013-08-091-0/+5
| | | | | | | | Ensure that platform data contains pointer for lcd_ctrl_config. Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: use devresDarren Etheridge2013-08-091-33/+8
| | | | | | | | | | | | Replace existing resource handling in the driver with managed device resource. v2: implement some changes as recommended by Prabhakar Lad <prabhakar.csengg@gmail.com> Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: enable sync lost intr for v2 ipAfzal Mohammed2013-08-091-1/+1
| | | | | | | | | | | | | The interrupt handler explicitly has code that handles the sync lost interrupt. However the sync lost interrupt is never actually being enabled in the LCD controller, therefore this interrupt code path is not being exercised. This fix simply enables the generation of the sync lost interrupt by the LCD controller so it can be dealt with appropriately by the interrupt handler. Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: fix 24bpp raster configurationDarren Etheridge2013-08-091-1/+2
| | | | | | | | | | | | | | | | | Based on original patch by: Manjunathappa, Prakash <prakash.pm@ti.com> and Afzal Mohammed <afzal@ti.com> Set only LCD_V2_TFT_24BPP_MODE bit for 24bpp and LCD_V2_TFT_24BPP_UNPACK bit along with LCD_V2_TFT_24BPP_MODE for 32bpp configuration. Patch is tested on am335x-evm for 24bpp and da850-evm for 16bpp configurations. v2: removes confusing fall through in case statement for pixel depth configuration. Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: improve readability of codeDarren Etheridge2013-08-091-11/+13
| | | | | | | | | Change the lcd_disable_raster funtion from using a bool to an enum as the function is very confusing with the current api. This helps make it clearer what the parameter is really doing. Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: fb_set_par supportDarren Etheridge2013-08-091-11/+47
| | | | | | | | | | | | | | | | | | | | v1: original from Afzal Mohammed <afzal@ti.com> fb_set_par helps in runtime configuration of lcd controller like changing resolution, pixel clock etc. (eg. using fbset utility) Reconfigure lcd controller based on information passed by framework. Enable raster back if it was already enabled. As fb_set_par would get invoked indirectly from probe via fb_set_var, remove existing lcdc initialization in probe and do lcdc reset in probe so that reset happens only at the begining. v2: changes from Darren Etheridge <detheridge@ti.com> remove unnecessary conditional branch where we attempt to disable something that we already checked to see if it was disabled. Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: report correct pixclockAfzal Mohammed2013-08-091-0/+11
| | | | | | | | | Update "var" pixclock with the value that is configurable in hardware. This lets user know the actual pixclock. Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: store struct device *Afzal Mohammed2013-08-091-0/+2
| | | | | | | | | store struct device pointer so that dev_dbg/err can be used outside of probe. Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: pix clk and clk div handling cleanupDarren Etheridge2013-08-091-30/+18
| | | | | | | | | | | | | | | | | | | Based on original patch by: Afzal Mohammed <afzal@ti.com> Use the new modedb field to store pix clk. Reorganize existing clock divider functions with names now corresponding to what they do, add common function prefix. Fix existing panel modedb pixclock to be in ps instead of Hz. This needed a change in the way clock divider is calculated. As modedb pixclock information is now in ps, override on "var" pixclock over modedb to var conversion is removed. v2: Changed pixel clock configuration to use KHZ2PICOS macro Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: store clk rate even if !CPUFREQAfzal Mohammed2013-08-091-3/+1
| | | | | | | | | | store lcd clk rate always, i.e. irrespective of whether CPUFREQ is enabled or not. This can be used to get clk rate directly instead of enquiring with clock framework with clk handle every time. Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: store current display informationAfzal Mohammed2013-08-091-0/+4
| | | | | | | | | | | | | | | store current videomode and controller data so that reconfiguring can be done easily. Reconfiguring would be required in fb_set_par, which is going to be added soon. If these details are not stored, the work probe does to retrieve these information would have to repeated at the place of reconfiguring and modifying platform data would be necessary to handle controller data changes like bpp. Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: remove unneeded "var" initializationAfzal Mohammed2013-08-091-21/+1
| | | | | | | | | modedb helper now updates "var" information based on the detected panel, remove the unnecessary initialization. Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: use modedb helper to update varAfzal Mohammed2013-08-091-16/+2
| | | | | | | | | | | | | | | | modedb structure is now used to store panel information, run modedb helper over it for initial update of "var" information instead of equating each fields. While at it, remove redundant update of bits_per_pixel. Note: pixclock is overridden with proper value using an existing code as currently modedb is having it in Hz instead of ps, this would be fixed in a later change and this overide would be removed. Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: simplify lcd_resetAfzal Mohammed2013-08-091-2/+2
| | | | | | | | lcd_reset function doesn't require any arguement, remove it. Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: fb_check_var enhancementAfzal Mohammed2013-08-091-0/+18
| | | | | | | | | | | | | Check whether "struct fb_var_screeninfo" fields are sane, if not update it to be within allowed limits. If user sends down buggy "var" values, this will bring those within allowable limits. And fb_set_par is not supposed to change "var" values, fb_check_var has to ensure that values are proper. Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* Drivers: video: remove __dev* attributes.Greg Kroah-Hartman2013-01-031-5/+5
| | | | | | | | | | | | | | CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, __devinitconst, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* da8xx: Fix revision check on the da8xx driverPantelis Antoniou2012-12-041-0/+1
| | | | | | | | The revision check fails for the beaglebone; Add new revision ID. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com> Acked-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* video: da8xx-fb: clk_get on connection id fckManjunathappa2012-11-271-1/+1
| | | | | | | | | | | | | | do clk_get on connection id "fck" to support OMAP based platforms having multiple clocks for module. Without this driver change clk_get fails on am335x. This patch is based on the discussion in community http://marc.info/?l=linux-kernel&m=135166018907827&w=2 Signed-off-by: Manjunathappa <prakash.pm@ti.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* da8xx-fb: cleanup LCDC configurationsManjunathappa, Prakash2012-11-271-26/+17
| | | | | | | | | | | | | | | Configure below LCDC configurations to optimal values, also have an option configure these optional parameters for platform. 1) AC bias configuration: Required only for passive panels 2) Dma_burst_size: 3) FIFO_DMA_DELAY: 4) FIFO threshold: Does not apply for da830 LCDC. Patch is verified for 16bpp and 24bpp configurations on da830, da850 and am335x EVMs. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* da8xx-fb: adopt fb_videomode data for panel informationManjunathappa, Prakash2012-11-271-70/+60
| | | | | | | | | Adopt fb_videomode data instead of defining driver private structure to hold panel information. This is the way standard FB drivers maintain the panel information. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* Merge tag 'fbdev-updates-for-3.7' of git://github.com/schandinat/linux-2.6Linus Torvalds2012-10-121-63/+220
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull fbdev updates from Florian Tobias Schandinat: "This includes: - large updates for OMAP - basic OMAP5 DSS support for DPI and DSI outputs - large cleanups and restructuring - some update to Exynos and da8xx-fb - removal of the pnx4008 driver (arch removed) - various other small patches" Fix up some trivial conflicts (mostly just include line changes, but also some due to the renaming of the deferred work functions by Tejun). * tag 'fbdev-updates-for-3.7' of git://github.com/schandinat/linux-2.6: (193 commits) gbefb: fix compile error video: mark nuc900fb_map_video_memory as __devinit video/mx3fb: set .owner to prevent module unloading while being used video: exynos_dp: use clk_prepare_enable and clk_disable_unprepare drivers/video/exynos/exynos_mipi_dsi.c: fix error return code drivers/video/savage/savagefb_driver.c: fix error return code video: s3c-fb: use clk_prepare_enable and clk_disable_unprepare da8xx-fb: save and restore LCDC context across suspend/resume cycle da8xx-fb: add pm_runtime support video/udlfb: fix line counting in fb_write OMAPDSS: add missing include for string.h OMAPDSS: DISPC: Configure color conversion coefficients for writeback OMAPDSS: DISPC: Add manager like functions for writeback OMAPDSS: DISPC: Configure writeback FIFOs OMAPDSS: DISPC: Configure writeback specific parameters in dispc_wb_setup() OMAPDSS: DISPC: Configure overlay-like parameters in dispc_wb_setup OMAPDSS: DISPC: Add function to set channel in for writeback OMAPDSS: DISPC: Don't set chroma resampling bit for writeback OMAPDSS: DISPC: Downscale chroma if plane is writeback OMAPDSS: DISPC: Configure input and output sizes for writeback ...
| * da8xx-fb: save and restore LCDC context across suspend/resume cycleManjunathappa, Prakash2012-10-101-0/+65
| | | | | | | | | | | | | | | | Save and restore register context of LCDC respectively before suspend and after resume. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
| * da8xx-fb: add pm_runtime supportManjunathappa, Prakash2012-10-101-14/+13
| | | | | | | | | | | | | | Add pm_runtime support to the da8xx-fb frame buffer driver. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
| * da8xx-fb: enable LCDC if FB is unblankedManjunathappa, Prakash2012-09-221-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | It is expected that LCDC to continue to be disabled after resume if it is blanked before suspend. This is also true for DVFS. But it is observed that LCDC being enabled after suspend/resume cycle or DVFS. Correcting it by having check for FB_BLANK_UNBLANK before enabling. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
| * da8xx-fb: allow frame to complete after disabling LCDCManjunathappa, Prakash2012-09-221-12/+40
| | | | | | | | | | | | | | | | | | | | | | | | Wait for active frame transfer to complete after disabling LCDC. At the same this wait is not be required when there are sync and underflow errors. Patch applies for revision 2 of LCDC present am335x. More information on disable and reset sequence can be found in section 13.4.6 of AM335x TRM @www.ti.com/am335x. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
| * da8xx-fb: add 24bpp LCD configuration supportManjunathappa, Prakash2012-08-231-33/+95
| | | | | | | | | | | | | | | | | | | | | | LCD controller on am335x supports 24bpp raster configuration in addition to ones on da850. LCDC also supports 24bpp in unpacked format having ARGB:8888 32bpp format data in DDR, but it doesn't interpret alpha component of the data. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
* | video: da8xx-fb: use __iomem pointers for MMIOArnd Bergmann2012-09-191-4/+4
|/ | | | | | | | | ARM is moving to stricter checks on readl/write functions, so we need to use the correct types everywhere. Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Cc: linux-fbdev@vger.kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* da8xx-fb: fix compile issue due to missing includeFlorian Tobias Schandinat2012-07-291-0/+1
| | | | Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
* da8xx-fb: do not turn ON LCD backlight unless LCDC is enabledManjunathappa, Prakash2012-07-291-4/+5
| | | | | | | | | | LCD blink is observed during suspend/resume and blank/unblank operations as backlight is ON during LCDC disable and enable. So make sure to turn OFF backlight before disabling and turn it ON after enabling. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
* video: da8xx-fb: do clock reset of revision 2 LCDC before enablingManjunathappa, Prakash2012-07-291-4/+8
| | | | | | | | | | As in specification software reset should be applied for several cycles before bringing it out of reset. Without this patch particularly during suspend and resume clock reset is not guaranteed to happen. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
* video: da8xx-fb: configure FIFO threshold to reduce underflow errorsManjunathappa, Prakash2012-07-291-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch works around the below silicon errata: During LCDC initialization, there is the potential for a FIFO underflow condition to occur. A FIFO underflow condition occurs when the input FIFO is completely empty and the LCDC raster controller logic that drives data to the output pins attempts to fetch data from the FIFO. When a FIFO underflow condition occurs, incorrect data will be driven out on the LCDC data pins. Software should poll the FUF bit field in the LCD_STAT register to check if an error condition has occurred or service the interrupt if FUF_EN is enabled when FUF occurs. If the FUF bit field has been set to 1, this will indicate an underflow condition has occurred and then the software should execute a reset of the LCDC via the LPSC. This problem may occur if the LCDC FIFO threshold size (LCDDMA_CTRL[TH_FIFO_READY]) is left at its default value after reset. Increasing the FIFO threshold size will reduce or eliminate underflows. Setting the threshold size to 256 double words or larger is recommended. Above issue is described in section 2.1.3 of silicon errata http://www.ti.com/lit/er/sprz313e/sprz313e.pdf Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
* video: da8xx-fb: fix flicker due to 1 frame delay in updated frameManjunathappa, Prakash2012-07-291-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flicker/tearing effect is observed with current FB driver. Issue is because of 2 active DMA channels ping ponging among them along with usage of 2 DDR ping pong buffers in driver. Application unaware of active DMA channel keeps updating frame being displayed, this leads to tearing effect. Below steps describes the issue: 1)Initially assume both buffers FB0 and FB1 are programmed for buffer-0. 2)On EOF0: Program FB0 for buffer-1, indicate(wake up) application to fill up buffer-0. As FB1 is active and continues to DMA buffer-0 (which is being filled), leading to tearing/flickering issue. 3)On EOF1: Program FB1 for buffer-0, indicate(wake up) application to fill up buffer-1. As FB0 is active and continues to DMA buffer-1(which is being filled), leading to tearing/flickering issue. 4)On EOF0: Program FB0 for buffer-1, indicate(wake up) application to fill up buffer-0. As FB1 is active and continues to DMA buffer-0(which is being filled), leading to tearing/flickering issue. ... Above steps depict that issue is because of 1 frame delay in frame panned by application. Patch fixes the issue by keeping track free DMA channel and configures it in drivers PAN callback so that panned frame from application gets displayed in next frame period. Wiki below describes the issue in detail and it also has link to application with which issue can be reproduced. http://processors.wiki.ti.com/index.php/DA8xx_LCDC_Linux_FB_FAQs Signed-off-by: Nellutla, Aditya <aditya.n@ti.com> Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
* video: da8xx-fb rev2: fix disabling of palette completion interruptManjunathappa, Prakash2012-07-291-5/+2
| | | | | | | | | | | Writing '1' to particular bit of IRQENABLE_CLEAR register disables the corresponding interrupt on revision 2 LCDC. This register was wrongly configured to disable all previous enabled interrupts instead of disabling only palette completion interrupt. Patch fixes it by clearing only palette completion interrupt bit. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
* da8xx-fb: add missing FB_BLANK operationsYegor Yefremov2012-07-291-0/+3
| | | | | | | | | add FB_BLANK_NORMAL, FB_BLANK_VSYNC_SUSPEND and FB_BLANK_HSYNC_SUSPEND modes (copy drivers/video/omap2/omapfb/omapfb-main.c implementation). Otherwise X-server will complain about invalid parameter. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
* da8xx-fb: Rounding FB size to satisfy SGX buffer requirementsAditya Nellutla2012-06-271-1/+4
| | | | | | | | | | | | | | | | | | | | In the real time use-case when SGX is used for rendering to FB buffers it has been observed that, the available memory from framebuffer driver is not sufficient for SGX under certain cases (like 16-bit WVGA resolution). SGX requires 2 swap buffers with each of the buffers aligned to lcm(line_length, PAGE_SIZE). Inorder to satisfy this requirement, we have two options, - Increase number of FB buffers (LCD_NUM_BUFFERS) to 3. This is not recommended as we end up wasting huge memory in most of the cases. - Align FB buffers to lcm(line_length, PAGE_SIZE).This ensures framebuffer size is increased to satisfy SGX requirements keeping alignment intact. This patch makes sure that FB allocates buffers aligned to above formula. Signed-off-by: Aditya Nellutla <aditya.n@ti.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
* fbdev: da8xx: add support for SP10Q010 displayAnatolij Gustschin2012-03-191-1/+37
| | | | | | | | | | | | | | | Add timing data for Hitachi SP10Q010 display and allow configuration of the 4bpp palette. For 4bpp framebuffer enable reversed order of pixels in a byte. This requires defining FB_CFB_REV_PIXELS_IN_BYTE and additionally setting var.nonstd to the value FB_NONSTD_REV_PIX_IN_B. Note that it is not enough to set da8xx_fb_var.nonstd to this value statically, since FBIOPUT_VSCREENINFO ioctl might pass var struct with .nonstd field set to zero or another value. Therefore this setting must be adjusted in fb_check_var() according to the requested bpp value. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
* fbdev: da8xx:: fix reporting of the display timing infoAnatolij Gustschin2012-03-191-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Timing info is not properly reported by the driver, e.g.: $ fbset -i mode "480x272-35" # D: 7.895 MHz, H: 12.165 kHz, V: 35.158 Hz geometry 480 272 480 544 16 timings 126666 64 64 32 32 41 10 According to the timing values defined for LK043T1DG01 display it should be reported as: mode "480x272-53" # D: 7.895 MHz, H: 15.038 kHz, V: 52.579 Hz geometry 480 272 480 544 16 timings 126666 2 2 2 2 41 10 Initialize additional fb_var_screeninfo fields so fix this problem. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
* video:da8xx-fb: calculate pixel clock period for the panelManjunathappa, Prakash2012-02-131-1/+18
| | | | | | | | | Patch calculates pixel clock period in pico seconds and updates the same in variable screen information structure. fbset utility uses this information. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
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