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* Merge tag 'pinctrl-v4.10-1' of ↵Linus Torvalds2016-12-1366-1345/+5688
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pinctrl updates from Linus Walleij: "Bulk pin control changes for the v4.10 kernel cycle: No core changes this time. Mainly gradual improvement and feature growth in the drivers. New drivers: - New driver for TI DA850/OMAP-L138/AM18XX pinconf - The SX150x was moved over from the GPIO subsystem and reimagined as a pin control driver with GPIO support in a joint effort by three independent users of this hardware. The result was amazingly good! - New subdriver for the Oxnas OX820 Improvements: - The sunxi driver now supports the generic pin control bindings rather than the sunxi-specific. Add debouncing support to the driver. - Simplifications in pinctrl-single adding a generic parser. - Two downstream fixes and move the Raspberry Pi BCM2835 over to use the generic GPIOLIB_IRQCHIP" * tag 'pinctrl-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (92 commits) pinctrl: sx150x: use new nested IRQ infrastructure pinctrl: sx150x: handle missing 'advanced' reg in sx1504 and sx1505 pinctrl: sx150x: rename 'reg_advance' to 'reg_advanced' pinctrl: sx150x: access the correct bits in the 4-bit regs of sx150[147] pinctrl: mt8173: set GPIO16 to usb iddig mode pinctrl: bcm2835: switch to GPIOLIB_IRQCHIP pinctrl: New driver for TI DA850/OMAP-L138/AM18XX pinconf devicetree: bindings: pinctrl: Add binding for ti,da850-pupd Documentation: pinctrl: palmas: Add ti,palmas-powerhold-override property definition pinctrl: intel: set default handler to be handle_bad_irq() pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507 pinctrl: sx150x: sort chips by part number pinctrl: sx150x: use correct registers for reg_sense (sx1502 and sx1508) pinctrl: imx: fix imx_pinctrl_desc initialization pinctrl: sx150x: support setting multiple pins at once pinctrl: sx150x: various spelling fixes and some white-space cleanup pinctrl: mediatek: use builtin_platform_driver pinctrl: stm32: use builtin_platform_driver pinctrl: sunxi: Testing the wrong variable pinctrl: nomadik: split up and comments MC0 pins ...
| * pinctrl: sx150x: use new nested IRQ infrastructureLinus Walleij2016-12-071-3/+7
| | | | | | | | | | | | | | | | | | Use the new gpiochip_irqchip_add_nested() and gpiochip_set_nested_irqchip() calls to properly created a nested irqchip and mark all child irqs properly with their parent IRQ. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sx150x: handle missing 'advanced' reg in sx1504 and sx1505Peter Rosin2016-12-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a problem where sx150x_regmap_reg_width() returns 8 for the data register (reg 0) for sx1504 where it should return 4, and return a correct 8 for sx1505 but for the wrong reason (both chips lack the 'advanced' register). This is not a real problem, since nothing depends on the function returning 4 or 8, and certainly not if it is returning 8 for the wrong reason. But fix this to avoid nasty surprises down the line. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sx150x: rename 'reg_advance' to 'reg_advanced'Peter Rosin2016-12-071-10/+10
| | | | | | | | | | | | | | | | This matches the datasheets and is less confusing since the register has nothing to with advancing anything. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sx150x: access the correct bits in the 4-bit regs of sx150[147]Peter Rosin2016-12-071-1/+2
| | | | | | | | | | | | | | | | | | The code assumes 8-bit or 16-bit width registers, but three of the chips (sx1501/sx1504/sx1507) are 4-bit. So, try to handle 4-bit chips as well, they leave the high part of each register unused. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mt8173: set GPIO16 to usb iddig modeChunfeng Yun2016-12-071-1/+1
| | | | | | | | | | | | | | | | | | | | the default mode of GPIO16 pin is gpio, when set EINT16 to IRQ_TYPE_LEVEL_HIGH, no interrupt is triggered, it can be fixed when set its default mode as usb iddig. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: bcm2835: switch to GPIOLIB_IRQCHIPLinus Walleij2016-12-072-76/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It should be possible to use the GPIOLIB_IRQCHIP helper library with the BCM2835 driver since it is a pretty straight forward cascaded irqchip. The only difference from other drivers is that the BCM2835 has several banks for a single gpiochip, and each bank has a separate IRQ line. Instead of creating one gpiochip per bank, a single gpiochip covers all banks GPIO lines. This makes it necessary to resolve the bank ID in the IRQ handler. The GPIOLIB_IRQCHIP allows several IRQs to be cascaded off the same gpiochip by calling gpiochip_set_chained_irqchip() repeatedly, but we have been a bit short on examples for how this should be handled in practice, so this is intended as an example of how this can be achieved. The old code did not model the chip as a chained interrupt handler, but this patch also rectifies that situation. Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Tested-by: Eric Anholt <eric@anholt.net> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: New driver for TI DA850/OMAP-L138/AM18XX pinconfDavid Lechner2016-12-073-0/+220
| | | | | | | | | | | | | | | | | | This adds a new driver for pinconf on TI DA850/OMAP-L138/AM18XX. These SoCs have a separate controller for controlling pullup/pulldown groups. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: intel: set default handler to be handle_bad_irq()Andy Shevchenko2016-12-072-2/+2
| | | | | | | | | | | | | | | | | | We switch the default handler to be handle_bad_irq() instead of handle_simple_irq() (which was not correct anyway). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507Peter Rosin2016-11-251-0/+98
| | | | | | | | | | | | | | Untested, register offsets carefully copied from datasheets. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sx150x: sort chips by part numberPeter Rosin2016-11-251-71/+71
| | | | | | | | | | Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sx150x: use correct registers for reg_sense (sx1502 and sx1508)Peter Rosin2016-11-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | All other registers on these chips are 8-bit, but reg_sense is 16-bits and therefore needs to be moved down one notch. This was apparently overlooked in the conversion to regmap, which only updated the register locations for the 16-bit chips. Fixes: 6489677f86c3 ("pinctrl-sx150x: Replace sx150x_*_cfg by means of regmap API") Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imx: fix imx_pinctrl_desc initializationGary Bisson2016-11-251-4/+4
| | | | | | | | | | | | | | | | | | Fixes: 6e408ed8be0e ("pinctrl: imx: fix initialization of imx_pinctrl_desc") Reviewed-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sx150x: support setting multiple pins at oncePeter Rosin2016-11-241-0/+17
| | | | | | | | | | | | | | | | | | | | | | If the chip does not have an oscio pin, all pins are configured in the same regmap register making it trivial to update all pins at once, so do that. If an oscio pin is present, there needs to be more locking in place to handle all cases correctly, so this is skipped. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sx150x: various spelling fixes and some white-space cleanupPeter Rosin2016-11-231-7/+6
| | | | | | | | | | | | Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: use builtin_platform_driverGeliang Tang2016-11-221-5/+1
| | | | | | | | | | | | | | | | Use builtin_platform_driver() helper to simplify the code. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: stm32: use builtin_platform_driverGeliang Tang2016-11-221-5/+1
| | | | | | | | | | | | | | Use builtin_platform_driver() helper to simplify the code. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: Testing the wrong variableDan Carpenter2016-11-221-2/+3
| | | | | | | | | | | | | | | | | | | | Smatch complains that we dereference "map" before testing it for NULL which is true. We should be testing "*map" instead. Also on the error path, we should free *map and set it to NULL. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: nomadik: split up and comments MC0 pinsLinus Walleij2016-11-181-6/+17
| | | | | | | | | | | | | | When debugging it helps to see exactly which pin goes where, so make it very detailed. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: single: Fix a couple error codesDan Carpenter2016-11-161-2/+6
| | | | | | | | | | | | | | | | We should return -ENOMEM instead of success if pcs_add_function() fails. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: fix theoretical uninitialized variable accessArnd Bergmann2016-11-161-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc warns about a way that it could use an uninitialized variable: drivers/pinctrl/sunxi/pinctrl-sunxi.c: In function 'sunxi_pinctrl_init': drivers/pinctrl/sunxi/pinctrl-sunxi.c:1191:8: error: 'best_div' may be used uninitialized in this function [-Werror=maybe-uninitialized] This cannot really happen except if 'freq' is UINT_MAX and 'clock' is zero, and both of these are forbidden. To shut up the warning anyway, this changes the logic to initialize the return code to the first divider value before looking at the others. Fixes: 7c926492d38a ("pinctrl: sunxi: Add support for interrupt debouncing") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge tag 'sh-pfc-for-v4.10-tag2' of ↵Linus Walleij2016-11-167-366/+816
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.10 (take two) - DU and EtherAVB pin groups for R-Car M3-W, - Bias handling cleanups and bug fixes, - Drive-strength for non-GPIO pins for R-Car H3, - EtherAVB MDIO & MII, and QSPI pin groups for R-Car H3.
| | * pinctrl: sh-pfc: r8a7795: Add group for QSPI0 and QSPI1 pinsNiklas Söderlund2016-11-161-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | Group the QSPI0 and QSPI1 pins into similar groups found in other sh-pfc drivers. The pins can not be muxed between functions other than QSPI, but their drive strength can be controlled. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pinsNiklas Söderlund2016-11-161-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Group the AVB pins into similar groups found in other sh-pfc drivers. The pins can not be muxed between functions other then AVB but their drive strength can be controlled. The group avb_mdc containing ADV_MDC and ADV_MDIO are on other SoCs called avb_mdio. In pfc-r8a7795 the avb_mdc group already existed and is in use in DT. Therefore add the ADV_MDIO pin to the existing group instead of renaming it. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795: Support none GPIO pins with configurable ↵Niklas Söderlund2016-11-161-15/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drive-strength There are pins on the r8a7795 which are not part of a GPIO bank nor can be muxed between different functions. They do however allow for the drive-strength to be configured. Add those pins to the list of pins and to the drive-strength configuration registers. The pins can now be referred to in DT by function names and their drive-strength modified. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: Support named pins with custom configurationNiklas Söderlund2016-11-161-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pins not associated with a GPIO port can still have other configuration parameters. Add a new macro SH_PFC_PIN_NAMED_CFG which allows for named pins to be declared with a set of configurations. The new macro is an modification of SH_PFC_PIN_NAMED to allow for optional configuration to be assigned. The flag SH_PFC_PIN_CFG_NO_GPIO is still enforced as this should only be used to define pins not associated with a GPIO port. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7778: Use lookup function for bias dataNiklas Söderlund2016-11-161-170/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the data structure and use the generic sh_pfc_pin_to_bias_info() function to get the register offset and bit information. Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795: Use lookup function for bias dataNiklas Söderlund2016-11-161-171/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a bug in the r8a7795 bias code where a WARN() is trigged anytime a pin from PUEN0/PUD0 is accessed. # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8 [..] Call trace: [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8 [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270 [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30 [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188 [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98 [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128 [<ffff0000081fe3bc>] seq_read+0x16c/0x420 [<ffff00000831a110>] full_proxy_read+0x58/0x88 [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8 [<ffff0000081d8874>] vfs_read+0x84/0x148 [<ffff0000081d9d64>] SyS_read+0x44/0xa0 [<ffff000008082f4c>] __sys_trace_return+0x0/0x4 This is due to the WARN() check if the reg field of the pullups struct is zero, and this should be 0 for pins controlled by the PUEN0/PUD0 registers since PU0 is defined as 0. Change the data structure and use the generic sh_pfc_pin_to_bias_info() function to get the register offset and bit information. Fixes: 560655247b627ac7 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support") Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795: Simplify get bias logicNiklas Söderlund2016-11-161-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The last else statement is missing braces, and the indentation level can be reduced. Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: Add helper to handle bias lookup tableNiklas Söderlund2016-11-153-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some SoC there are no simple mapping of pins to bias register bits and a lookup table is needed. This logic is already implemented in some SoC specific drivers that could benefit from a generic implementation. Add helpers to deal with the lookup which later can be used by the SoC specific drivers. The logic used to lookup are different from the one it aims to replace, this is intentional. This new method reduces the memory consumption at the cost of increased CPU usage and fix a bug where a WARN() would incorrectly be triggered if the register offset is 0. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLENiklas Söderlund2016-11-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output when examining /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins if the operation get_bias() is implemented but the pin is not handled by the get_bias() implementation. In that case the output will state that "input bias disabled" indicating that this pin has bias control support. Make support for PIN_CONFIG_BIAS_DISABLE depend on that the pin either supports SH_PFC_PIN_CFG_PULL_UP or SH_PFC_PIN_CFG_PULL_DOWN. This also solves the issue where SoC specific implementations print error messages if their particular implementation of {set,get}_bias() is called with a pin it does not know about. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7796: Add DU supportNiklas Söderlund2016-11-151-0/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only the DU parallel RGB output signals are included, HDMI and TCON pins will be added in separate groups. Based on a similar patch from Laurent Pinchart for the r8a7795 PFC driver. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7796: Add EtherAVB pins, groups and functionsTakeshi Kihara2016-11-151-0/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds AVB_LINK, AVB_MAGIC, AVB_PHY_INT, AVB_MDC, AVB_AVTP_PPS, AVB_AVTP_MATCH, AVB_AVTP_CAPTURE pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: rockchip: add support for rk1108Andy Yan2016-11-161-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This add pinctrl support for Rockchip RK1108 Soc. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Series-changes: 2 - add pull and drive-strength functionality Series-changes: 3 - two minor CodingStyle fixes adviced by Heiko Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: Add support for interrupt debouncingMaxime Ripard2016-11-152-0/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pin controller found in the Allwinner SoCs has support for interrupts debouncing. However, this is not done per-pin, preventing us from using the generic pinconf binding for that, but per irq bank, which, depending on the SoC, ranges from one to five. Introduce a device-wide property to deal with this using a microsecond resolution. We can re-use the per-pin input-debounce property for that, so let's do it! Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: Make sunxi_pconf_group_set use sunxi_pconf_reg helperChen-Yu Tsai2016-11-151-32/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sunxi_pconf_reg helper introduced in the last patch gives us the chance to rework sunxi_pconf_group_set to have it match the structure of sunxi_pconf_(group_)get and make it easier to understand. For each config to set, it: 1. checks if the parameter is supported. 2. checks if the argument is within limits. 3. converts argument to the register value. 4. writes to the register with spinlock held. As a result the function now blocks unsupported config parameters, instead of silently ignoring them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: Add support for fetching pinconf settings from hardwareChen-Yu Tsai2016-11-152-6/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sunxi pinctrl driver only caches whatever pinconf setting was last set on a given pingroup. This is not particularly helpful, nor is it correct. Fix this by actually reading the hardware registers and returning the correct results or error codes. Also filter out unsupported pinconf settings. Since this driver has a peculiar setup of 1 pin per group, we can support both pin and pingroup pinconf setting read back with the same code. The sunxi_pconf_reg helper and code structure is inspired by pinctrl-msm. With this done we can also claim to support generic pinconf, by setting .is_generic = true in pinconf_ops. Also remove the cached config value. The behavior of this was never correct, as it only cached 1 setting instead of all of them. Since we can now read back settings directly from the hardware, it is no longer required. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: Fix PIN_CONFIG_BIAS_PULL_{DOWN,UP} argumentChen-Yu Tsai2016-11-151-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to pinconf-generic.h, the argument for PIN_CONFIG_BIAS_PULL_{DOWN,UP} is non-zero if the bias is enabled with a pull up/down resistor, zero if it is directly connected to VDD or ground. Since Allwinner hardware uses a weak pull resistor internally, the argument should be 1. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: Free configs in pinctrl_map only if it is a config mapChen-Yu Tsai2016-11-151-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the recently refactored sunxi pinctrl library, we are only allocating one set of pin configs for each pinmux setting node. When the pinctrl_map structure is freed, the pin configs should also be freed. However the code assumed the first map would contain the configs, which actually never happens, as the mux function map gets added first. The proper way to do this is to look through all the maps and free the first one whose type is actually PIN_MAP_TYPE_CONFIGS_GROUP. Also slightly expand the comment explaining this. Fixes: f233dbca6227 ("pinctrl: sunxi: Rework the pin config building code") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: vt8500: make bool drivers explicitly non-modularPaul Gortmaker2016-11-157-81/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | None of the Kconfigs for any of these drivers are tristate, meaning that they currently are not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the drivers there is no doubt they are builtin-only. All drivers get the exact same change, so they are handled in batch. Changes are (1) use builtin_platform_driver, (2) use init.h header (3) delete module_exit related code, (4) delete MODULE_DEVICE_TABLE, (5) delete MODULE_LICENCE/MODULE_AUTHOR and associated tags and (6) drop ".remove" code and prevent sysfs unbind attempts to call ".remove". Once this is done, the shared remove function in wmt.[ch] is no longer used and hence it is removed as well. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE etc. tags since all that information is already contained at the top of each file in the comments. Cc: Tony Prisk <linux@prisktech.co.nz> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: samsung: Add GPF support for Exynos5433Chanwoo Choi2016-11-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add the support of GPF[1-5] pin of Exynos5433 SoC. The GPFx need to support the multiple memory map because the registers of GPFx are located in the different domain. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bankChanwoo Choi2016-11-156-78/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports the multiple IORESOURCE_MEM resources for one pin-bank. In the pre-existing Exynos series, the registers of the gpio bank are included in the one memory map. But, some gpio bank need to support the one more memory map (IORESOURCE_MEM) because the registers of gpio bank are separated into the different memory map. For example, The both ALIVE and IMEM domain have the different memory base address. The GFP[1-5] of exynos5433 are composed as following: - ALIVE domain : WEINT_* registers - IMEM domain : CON/DAT/PUD/DRV/CONPDN/PUDPDN register Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: linux-gpio@vger.kernel.org Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: bcm2835: Return pins to inputs when freedPhil Elwell2016-11-151-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When dynamically unloading overlays, it is important that freed pins are restored to being inputs to prevent functions from being enabled in multiple places at once. Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Phil Elwell <phil@raspberrypi.org> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: bcm2835: Fix ints for GPIOs 28-31 & 46-53Phil Elwell2016-11-151-12/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Contrary to the documentation, the BCM2835 GPIO controller actually has four interrupt lines - one each for the three IRQ groups and one common. Confusingly, the GPIO interrupt groups don't correspond directly with the GPIO control banks. Instead, GPIOs 0-27 generate IRQ GPIO0, 28-45 IRQ GPIO1 and 46-53 IRQ GPIO2. Awkwardly, the GPIOs for IRQ GPIO1 straddle two 32-entry GPIO banks, so split out a function to process the interrupts for a single GPIO bank. Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Phil Elwell <phil@raspberrypi.org> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: single: search for the bits property when parsing bitsAxel Haslam2016-11-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The pcs_parse_bits_in_pinctrl_entry function should search for the "pinctrl-single,bits" and not "pinctrl-single,pins" Signed-off-by: Axel Haslam <ahaslam@baylibre.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: single: check for any error when getting rowsAxel Haslam2016-11-111-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pinctrl_count_index_with_args returns -ENOENT not -EINVAL. The return check would pass, and we would try to kzalloc with a negative error size throwing a warning. Instead of checking for -EINVAL specifically, lets check for any error and avoid negative size allocations. Signed-off-by: Axel Haslam <ahaslam@baylibre.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: st: st_pctl_dt_parse_groups simplify expressionHeinrich Schuchardt2016-11-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | for_each_property_of_node(pins, pp) checks that pp is not NULL. So there is no need to check it inside the loop. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: st: st_pinconf_dbg_show wrong format stringHeinrich Schuchardt2016-11-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | function is defined as unsigned int. So we need %u to print it. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'sh-pfc-for-v4.10-tag1' of ↵Linus Walleij2016-11-081-10/+378
| |\ \ | | |/ | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.10 - I2C and DRIF pin groups for R-Car M3-W, - Bug fixes for SDHI2/3 on R-Car M3-W.
| | * pinctrl: sh-pfc: r8a7796: Fix GPSR definitions for SDHI2/3Geert Uytterhoeven2016-11-071-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix off-by-one (row and/or register) errors in links to Peripheral Function Select Register bitfields from GPIO/Peripheral Function Select Register 4 macros for SDHI2 and SDHI3 pins. Based on rev. 0.52E of the R-Car Gen3 User's Manual. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>
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