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* [PATCH] shpchp: Use dword accessors for PCI_ROM_ADDRESSAdam Kropelin2005-09-171-2/+1
| | | | | | | | | | | | | | PCI_ROM_ADDRESS is a 32 bit register and as such should be accessed using pci_bus_{read,write}_config_dword(). A recent audit of drivers/ turned up several cases of byte- and word-sized accesses. The harmful ones were fixed by Linus directly. This patches up one of the remaining harmless-but-still-wrong cases caught in the dragnet. Signed-off-by: Adam Kropelin <akropel1@rochester.rr.com> Cc: <kristen.c.accardi@intel.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] pciehp: Use dword accessors for PCI_ROM_ADDRESSAdam Kropelin2005-09-171-3/+1
| | | | | | | | | | | | | | PCI_ROM_ADDRESS is a 32 bit register and as such should be accessed using pci_bus_{read,write}_config_dword(). A recent audit of drivers/ turned up several cases of byte- and word-sized accesses. The harmful ones were fixed by Linus directly. This patches up one of the remaining harmless-but-still-wrong cases caught in the dragnet. Signed-off-by: Adam Kropelin <akropel1@rochester.rr.com> Cc: <kristen.c.accardi@intel.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] ibmphp: Use dword accessors for PCI_ROM_ADDRESSAdam Kropelin2005-09-171-1/+1
| | | | | | | | | | | | | PCI_ROM_ADDRESS is a 32 bit register and as such should be accessed using pci_bus_{read,write}_config_dword(). A recent audit of drivers/ turned up several cases of byte- and word-sized accesses. The harmful ones were fixed by Linus directly. This patches up one of the remaining harmless-but-still-wrong cases caught in the dragnet. Signed-off-by: Adam Kropelin <akropel1@rochester.rr.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] pci: only call pci_restore_bars at bootJohn W. Linville2005-09-141-4/+12
| | | | | | | | | | | | Certain (SGI?) ia64 boxes object to having their PCI BARs restored unless absolutely necessary. This patch restricts calling pci_restore_bars from pci_set_power_state unless the current state is PCI_UNKNOWN, the actual (i.e. physical) state of the device is PCI_D3hot, and the device indicates that it will lose its configuration when transitioning to PCI_D0. Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] Subject: PATCH: fix numa caused compile warningsAlan Cox2005-09-102-5/+11
| | | | | | | | | pcibus_to_cpumask expands into more than just an initialiser so gcc moans about code before variable declarations. Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6 Linus Torvalds2005-09-095-54/+64
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| * [PATCH] PCI: Small rearrangement of PCI probing codePaul Mackerras2005-09-092-18/+33
| | | | | | | | | | | | | | | | | | | | | | | | This patch makes some small rearrangements of the PCI probing code in order to make it possible for arch code to set up the PCI tree without needing to duplicate code from the PCI layer unnecessarily. PPC64 will use this to set up the PCI tree from the Open Firmware device tree, which we need to do on logically-partitioned pSeries systems. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * [PATCH] PCI: Unhide SMBus on Compaq Evo N620cRumen Ivanov Zarev2005-09-091-0/+6
| | | | | | | | | | | | | | | | Trivial patch against 2.6.13 to unhide SMBus on Compaq Evo N620c laptop using Intel 82855PM chipset. Signed-off-by: Rumen Zarev <rzarev@caltech.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * [PATCH] PCI: Fix PCI bus mastering enable problem in pciehpRajesh Shah2005-09-091-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Martin Franc reported that the pciehp driver was not enabling bus master capability on his hot-plugged card. pciehprm_enable_card() was updating the PCI command register only if _HPP indicated a value for SERR or PERR that was different from the current setting. I don't have hardware that reproduces this problem, but Martin reports that this patch fixes the problem for him. Signed-off-by: Rajesh Shah <rajesh.shah@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> From rzarev@its.caltech.edu Tue Sep 6 18:29:50 2005 Date: Tue, 6 Sep 2005 13:39:32 -0700 (PDT) From: Rumen Ivanov Zarev <rzarev@its.caltech.edu> Message-Id: <200509062039.j86KdWMr014934@inky.its.caltech.edu> To: gregkh@suse.de Subject: PCI: Unhide SMBus on Compaq Evo N620c Cc: linux-kernel@vger.kernel.org Trivial patch against 2.6.13 to unhide SMBus on Compaq Evo N620c laptop using Intel 82855PM chipset. Signed-off-by: Rumen Zarev <rzarev@caltech.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> --- drivers/pci/quirks.c | 6 ++++++ 1 file changed, 6 insertions(+) --- gregkh-2.6.orig/drivers/pci/quirks.c 2005-09-09 10:28:55.000000000 -0700 +++ gregkh-2.6/drivers/pci/quirks.c 2005-09-09 13:51:44.000000000 -0700 @@ -876,6 +876,12 @@ static void __init asus_hides_smbus_host case 0xC00C: /* Samsung P35 notebook */ asus_hides_smbus = 1; } + } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { + if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) + switch(dev->subsystem_device) { + case 0x0058: /* Compaq Evo N620c */ + asus_hides_smbus = 1; + } } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
| * [PATCH] PCI: move pci core to use add_hotplug_env_var()Greg Kroah-Hartman2005-09-091-32/+21
| | | | | | | | | | | | | | | | This fixes a bug in the environment variables for all PCI device hotplug calls. Thanks to Kay Sievers for pointing out the problem. Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | [PATCH] yenta: share code with PCI coreDominik Brodowski2005-09-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Share code between setup-bus.c and yenta_socket.c: use the write-out code of resources to the bridge also in yenta_socket.c, as it provides useful debug output. In addition, it fixes the bug that the CPU-centric resource view might need to be transferred to the PCI-centric view: setup-bus.c does that, while yenta-socket.c did not. Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | Merge master.kernel.org:/pub/scm/linux/kernel/git/paulus/ppc64-2.6 Linus Torvalds2005-09-092-11/+17
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| * [PATCH] Separate pci bits out of struct device_nodePaul Mackerras2005-09-092-11/+17
| | | | | | | | | | | | | | | | | | | | | | This patch pulls the PCI-related junk out of struct device_node and puts it in a separate structure, struct pci_dn. The device_node now just has a void * pointer in it, which points to a struct pci_dn for nodes that represent PCI devices. It could potentially be used in future for device-specific data for other sorts of devices, such as virtual I/O devices. Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [PATCH] PCI: PCI/libata INTx bug fixBrett M Russ2005-09-091-1/+1
|/ | | | | | | | | | | Previous INTx cleanup patch had a bug that was not caught. I found this last night during testing and can confirm that it is now 100% working. Signed-off-by: Brett Russ <russb@emc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Acked-by: Jeff Garzik <jgarzik@pobox.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] PCI/libata INTx cleanupBrett M Russ2005-09-082-8/+28
| | | | | | | | | Simple cleanup to eliminate X copies of the pci_enable_intx() function in libata. Moved ahci.c's pci_intx() to pci.c and use it throughout libata and msi.c. Signed-off-by: Brett Russ <russb@emc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI: Support PCM PM CAP version 3Daniel Ritz2005-09-082-8/+6
| | | | | | | | | | | | | - support PCI PM CAP version 3 (as defined in PCI PM Interface Spec v1.2) - pci/probe.c sets the PM state initially to 4 which is D3cold. add a PCI_UNKNOWN - minor cleanups Signed-off-by: Daniel Ritz <daniel.ritz@gmx.ch> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI: Add pci_walk_bus function to PCI core (nonrecursive)Paul Mackerras2005-09-081-0/+48
| | | | | | | | | | | | | | | | | | | | The PCI error recovery infrastructure needs to be able to contact all the drivers affected by a PCI error event, which may mean traversing all the devices under a given PCI-PCI bridge. This patch adds a function to the PCI core that traverses all the PCI devices on a PCI bus and under any PCI-PCI bridges on that bus (and so on), calling a given function for each device. This provides a way for the error recovery code to iterate through all devices that are affected by an error event. This version is not implemented as a recursive function. Instead, when we reach a PCI-PCI bridge, we set the pointers to start doing the devices on the bus under the bridge, and when we reach the end of a bus's devices, we use the bus->self pointer to go back up to the next higher bus and continue doing its devices. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI Hotplug: SGI hotplug driver fixesPrarit Bhargava2005-09-081-104/+91
| | | | | | | | | | These fixes were suggested by pcihpd-discuss, but were dropped in the initial checkin of the code. These fixes include cleaning up the hotplug driver sysfs filename, and some minor code cleanups. The driver also requires at least PROM 4.30, not 4.20. Signed-off-by: Prarit Bhargava <prarit@sgi.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI: Fix regression in pci_enable_device_barsAlan Stern2005-09-081-1/+1
| | | | | | | | | | This patch (as552) fixes yet another small problem recently added. If an attempt to put a PCI device back into D0 fails because the device doesn't support PCI PM, it shouldn't count as error. Without this patch the UHCI controllers on my Intel motherboard don't work. Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI: start paying attention to a lot of pci function return valuesGreg Kroah-Hartman2005-09-084-7/+17
| | | | Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] Make sparc64 use setup-res.cDavid S. Miller2005-09-083-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There were three changes necessary in order to allow sparc64 to use setup-res.c: 1) Sparc64 roots the PCI I/O and MEM address space using parent resources contained in the PCI controller structure. I'm actually surprised no other platforms do this, especially ones like Alpha and PPC{,64}. These resources get linked into the iomem/ioport tree when PCI controllers are probed. So the hierarchy looks like this: iomem --| PCI controller 1 MEM space --| device 1 device 2 etc. PCI controller 2 MEM space --| ... ioport --| PCI controller 1 IO space --| ... PCI controller 2 IO space --| ... You get the idea. The drivers/pci/setup-res.c code allocates using plain iomem_space and ioport_space as the root, so that wouldn't work with the above setup. So I added a pcibios_select_root() that is used to handle this. It uses the PCI controller struct's io_space and mem_space on sparc64, and io{port,mem}_resource on every other platform to keep current behavior. 2) quirk_io_region() is buggy. It takes in raw BUS view addresses and tries to use them as a PCI resource. pci_claim_resource() expects the resource to be fully formed when it gets called. The sparc64 implementation would do the translation but that's absolutely wrong, because if the same resource gets released then re-claimed we'll adjust things twice. So I fixed up quirk_io_region() to do the proper pcibios_bus_to_resource() conversion before passing it on to pci_claim_resource(). 3) I was mistakedly __init'ing the function methods the PCI controller drivers provide on sparc64 to implement some parts of these routines. This was, of course, easy to fix. So we end up with the following, and that nasty SPARC64 makefile ifdef in drivers/pci/Makefile is finally zapped. Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI: restore BAR values after D3hot->D0 for devices that need itJohn W. Linville2005-09-082-5/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some PCI devices (e.g. 3c905B, 3c556B) lose all configuration (including BARs) when transitioning from D3hot->D0. This leaves such a device in an inaccessible state. The patch below causes the BARs to be restored when enabling such a device, so that its driver will be able to access it. The patch also adds pci_restore_bars as a new global symbol, and adds a correpsonding EXPORT_SYMBOL_GPL for that. Some firmware (e.g. Thinkpad T21) leaves devices in D3hot after a (re)boot. Most drivers call pci_enable_device very early, so devices left in D3hot that lose configuration during the D3hot->D0 transition will be inaccessible to their drivers. Drivers could be modified to account for this, but it would be difficult to know which drivers need modification. This is especially true since often many devices are covered by the same driver. It likely would be necessary to replicate code across dozens of drivers. The patch below should trigger only when transitioning from D3hot->D0 (or at boot), and only for devices that have the "no soft reset" bit cleared in the PM control register. I believe it is safe to include this patch as part of the PCI infrastructure. The cleanest implementation of pci_restore_bars was to call pci_update_resource. Unfortunately, that does not currently exist for the sparc64 architecture. The patch below includes a null implemenation of pci_update_resource for sparc64. Some have expressed interest in making general use of the the pci_restore_bars function, so that has been exported to GPL licensed modules. Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI Hotplug: use bus_slot number for nameKristen Accardi2005-09-082-2/+2
| | | | | | | | | | For systems with multiple hotplug controllers, you need to use more than just the slot number to uniquely name the slot. Without a unique slot name, the pci_hp_register() will fail. This patch adds the bus number to the name. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI: remove CONFIG_PCI_NAMESAdrian Bunk2005-09-087-10495/+3
| | | | | | | This patch removes CONFIG_PCI_NAMES. Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI: Run PCI driver initialization on local nodeAndi Kleen2005-09-081-1/+30
| | | | | | | | | | | | | | | Run PCI driver initialization on local node Instead of adding messy kmalloc_node()s everywhere run the PCI driver probe on the node local to the device. This would not have helped for IDE, but should for other more clean drivers that do more initialization in probe(). It won't help for drivers that do most of the work on first open (like many network drivers) Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI Hotplug: rpaphp: Purify hotplugJohn Rose2005-09-085-193/+104
| | | | | | | | | | | | | | | | | | Currently rpaphp registers the following bus types as hotplug slots: 1) Actual PCI Hotplug slots 2) Embedded/Internal PCI slots 3) PCI Host Bridges The second and third bus types are not actually direct parents of removable adapters. As such, the rpaphp has special case code to fake results for attributes like power, adapter status, etc. This patch removes types 2 and 3 from the rpaphp module. This patch also changes the DLPAR module so that slots can be DLPAR-added/removed without having been designated as hotplug-capable. Signed-off-by: John Rose <johnrose@austin.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI Hotplug: rpaphp: Export slot enableJohn Rose2005-09-083-14/+35
| | | | | | | | | | | This patch exports rpaphp_config_pci_adapter() for use by the rpadlpar module. It also changes this function by removing any dependencies on struct slot. The patch also changes the RPA DLPAR-add path to enable newly-added slots in a separate step from that which registers them as hotplug slots. Signed-off-by: John Rose <johnrose@austin.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI Hotplug: rpaphp: Remove rpaphp_find_pciJohn Rose2005-09-083-61/+47
| | | | | | | | | The rpaphp module currently uses a fragile method to find a pci device by its device node. This function is unnecessary, so this patch scraps it. Signed-off-by: John Rose <johnrose@austin.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI Hotplug: rpaphp: Change slot pci referenceJohn Rose2005-09-083-117/+75
| | | | | | | | | | | | | | | | The slot structure in the rpaphp module currently references the PCI contents of the slot using the PCI device of the parent bridge. This is unnecessary, since the module is actually interested in the subordinate bus of the bridge. The dependency on a PCI bridge device also prohibits the module from registering hotplug slots that have a root bridge as a parent, since root bridges on PPC64 don't have PCI devices. This patch changes struct slot to reference the PCI subsystem using a pci_bus rather than a pci_dev. Signed-off-by: John Rose <johnrose@austin.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI Hotplug: rpaphp: Move VIO registrationJohn Rose2005-09-087-271/+88
| | | | | | | | | | | | | | | | Currently, rpaphp registers Virtual I/O slots as hotplug slots. The only purpose of this registration is to ensure that the VIO subsystem is notified of new VIO buses during DLPAR adds. Similarly, rpaphp notifies the VIO subsystem when a VIO bus is DLPAR-removed. The rpaphp module has special case code to fake results for attributes like power, adapter status, etc. The VIO register/unregister functions could just as easily be made from the DLPAR module. This patch moves the VIO registration calls to the DLPAR module, and removes the VIO fluff from rpaphp altogether. Signed-off-by: John Rose <johnrose@austin.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [PATCH] PCI Hotplug: rpaphp: Remove unused stuffJohn Rose2005-09-082-73/+31
| | | | | | | Subject line says it all :) Signed-off-by: John Rose <johnrose@austin.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* Merge linux-2.6 with linux-acpi-2.6Len Brown2005-09-084-22/+33
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| * [PATCH] x86/x86_64: deferred handling of writes to /proc/irqxx/smp_affinityAshok Raj2005-09-072-17/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When handling writes to /proc/irq, current code is re-programming rte entries directly. This is not recommended and could potentially cause chipset's to lockup, or cause missing interrupts. CONFIG_IRQ_BALANCE does this correctly, where it re-programs only when the interrupt is pending. The same needs to be done for /proc/irq handling as well. Otherwise user space irq balancers are really not doing the right thing. - Changed pending_irq_balance_cpumask to pending_irq_migrate_cpumask for lack of a generic name. - added move_irq out of IRQ_BALANCE, and added this same to X86_64 - Added new proc handler for write, so we can do deferred write at irq handling time. - Display of /proc/irq/XX/smp_affinity used to display CPU_MASKALL, instead it now shows only active cpu masks, or exactly what was set. - Provided a common move_irq implementation, instead of duplicating when using generic irq framework. Tested on i386/x86_64 and ia64 with CONFIG_PCI_MSI turned on and off. Tested UP builds as well. MSI testing: tbd: I have cards, need to look for a x-over cable, although I did test an earlier version of this patch. Will test in a couple days. Signed-off-by: Ashok Raj <ashok.raj@intel.com> Acked-by: Zwane Mwaikambo <zwane@holomorphy.com> Grudgingly-acked-by: Andi Kleen <ak@muc.de> Signed-off-by: Coywolf Qi Hunt <coywolf@lovecn.org> Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
| * [PATCH] swsusp: switch pm_message_t to structPavel Machek2005-09-051-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds type-checking to pm_message_t, so that people can't confuse it with int or u32. It also allows us to fix "disk yoyo" during suspend (disk spinning down/up/down). [We've tried that before; since that cpufreq problems were fixed and I've tried make allyes config and fixed resulting damage.] Signed-off-by: Pavel Machek <pavel@suse.cz> Signed-off-by: Alexander Nyberg <alexn@telia.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
| * [PATCH] via vt8237 apic bypass deassertion quirkKarsten Wiese2005-09-051-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | The VIA VT8237's IOAPIC sends 'APIC De-Assert Messages' by default, causing another CPU interrupt when the IRQ pin is de-asserted. This feature is switched off by the patch to get rid of doubled ioapic level interrupt rates. Signed-off-by: Karsten Wiese <annabellesgarden@yahoo.de> Tested-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | Merge linux-2.6 into linux-acpi-2.6 testLen Brown2005-09-032-8/+18
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| * [PATCH] Fix PCI ROM mappingBenjamin Herrenschmidt2005-09-011-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | This fixes a problem with pci_map_rom() which doesn't properly update the ROM BAR value with the address thas allocated for it by the PCI code. This problem, among other, breaks boot on Mac laptops. It'ss a new version based on Linus latest one with better error checking. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
| * [PATCH] x86: pci_assign_unassigned_resources() updateIvan Kokshaysky2005-08-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I had some time to think about PCI assign issues in 2.6.13-rc series. The major problem here is that we call pci_assign_unassigned_resources() way too early - at subsys_initcall level. Therefore we give no chances to ACPI and PnP routines (called at fs_initcall level) to reserve their respective resources properly, as the comments in drivers/pnp/system.c and drivers/acpi/motherboard.c suggest: /** * Reserve motherboard resources after PCI claim BARs, * but before PCI assign resources for uninitialized PCI devices */ So I moved the pci_assign_unassigned_resources() call to pcibios_assign_resources() (fs_initcall), which should hopefully fix a lot of problems and make PCIBIOS_MIN_IO tweaks unnecessary. Other changes: - remove resource assignment code from pcibios_assign_resources(), since it duplicates pci_assign_unassigned_resources() functionality and actually does nothing in 2.6.13; - modify ROM assignment code as per Ben's suggestion: try to use firmware settings by default (if PCI_ASSIGN_ROMS is not set); - set CARDBUS_IO_SIZE back to 4K as it's a wonderful stress test for various setups. Confirmed by Tero Roponen <teanropo@cc.jyu.fi> (who had problems with the 4kB CardBus IO size previously). Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | Auto-update from upstreamLen Brown2005-08-262-2/+4
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| * Ignore disabled ROM resources at setupLinus Torvalds2005-08-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Writing even a disabled value seems to mess up some matrox graphics cards. It may be a card-related issue, but we may also be writing reserved low bits in the result. This was a fall-out of switching x86 over to the generic PCI resource allocation code, and needs more debugging. In particular, the old x86 code defaulted to not doing any resource allocations at all for ROM resources. In the meantime, this has been reported to make X happier by Helge Hafting <helgehaf@aitel.hist.no>. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
| * Only pre-allocate 256 bytes of cardbio IO rangeLinus Torvalds2005-08-261-1/+1
| | | | | | | | | | | | | | | | It may seem small, but most cards need much less, if any, and this not only makes the code adhere to the comment, it seems to fix a boot-time lockup on a ThinkPad 380XD laptop reported by Tero Roponen <teanropo@cc.jyu.fi> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [ACPI] delete CONFIG_ACPI_BUSLen Brown2005-08-242-4/+4
|/ | | | | | it is a synonym for CONFIG_ACPI Signed-off-by: Len Brown <len.brown@intel.com>
* [PATCH] PCI Hotplug: new contact infoKristen Accardi2005-08-1620-20/+20
| | | | | | Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] PCI: fix quirk-6700-fix.patchAndrew Morton2005-08-161-0/+6
| | | | | | | | | drivers/built-in.o(.text+0x32c3): In function `quirk_pcie_pxh': /usr/src/25/drivers/pci/quirks.c:1312: undefined reference to `disable_msi_mode' Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] PCI: 6700/6702PXH quirkKristen Accardi2005-08-163-2/+26
| | | | | | | | | | | | | On the 6700/6702 PXH part, a MSI may get corrupted if an ACPI hotplug driver and SHPC driver in MSI mode are used together. This patch will prevent MSI from being enabled for the SHPC as part of an early pci quirk, as well as on any pci device which sets the no_msi bit. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Revert "[PATCH] PCI: restore BAR values..."Linus Torvalds2005-08-082-56/+5
| | | | | | | Revert commit fec59a711eef002d4ef9eb8de09dd0a26986eb77, which is breaking sparc64 that doesn't have a working pci_update_resource. We'll re-do this after 2.6.13 when we'll do it all properly.
* [PATCH] VIA VT8235 PCI quirkIvan Kokshaysky2005-08-081-0/+19
| | | | | | | | | | | | | Like many other southbridges from different manufacturers, VIA VT8235 chip has two non-standard BARs for power management and SMBus registers (see the datasheet at http://www.via.com.tw). This new quirk routine fixes boot problem with 2.6.13-rc2/rc6 kernels on Targa Visionary 811 Athlon64 laptop, as reported by Mikael Pettersson <mikpe@csd.uu.se>. Signed-off-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] Fix restore of 64-bit PCI BAR'sIvan Kokshaysky2005-08-071-1/+6
| | | | | | | | | | | | | | For 64-bit BAR[i] only pci_dev->resource[i] is valid, ->resource[i+1] slot is unused and contains zeroes in all fields. So when we update a PCI BAR, all we need is just to check that we're going to update a _valid_ resource. Also make sure to write high bits - use "x >> 16 >> 16" (rather than the simpler ">> 32") to avoid warnings on 32-bit architectures where we're not going to have any high bits. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] PCI: restore BAR values after D3hot->D0 for devices that need itJohn W. Linville2005-08-042-5/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some PCI devices (e.g. 3c905B, 3c556B) lose all configuration (including BARs) when transitioning from D3hot->D0. This leaves such a device in an inaccessible state. The patch below causes the BARs to be restored when enabling such a device, so that its driver will be able to access it. The patch also adds pci_restore_bars as a new global symbol, and adds a correpsonding EXPORT_SYMBOL_GPL for that. Some firmware (e.g. Thinkpad T21) leaves devices in D3hot after a (re)boot. Most drivers call pci_enable_device very early, so devices left in D3hot that lose configuration during the D3hot->D0 transition will be inaccessible to their drivers. Drivers could be modified to account for this, but it would be difficult to know which drivers need modification. This is especially true since often many devices are covered by the same driver. It likely would be necessary to replicate code across dozens of drivers. The patch below should trigger only when transitioning from D3hot->D0 (or at boot), and only for devices that have the "no soft reset" bit cleared in the PM control register. I believe it is safe to include this patch as part of the PCI infrastructure. The cleanest implementation of pci_restore_bars was to call pci_update_resource. Unfortunately, that does not currently exist for the sparc64 architecture. The patch below includes a null implemenation of pci_update_resource for sparc64. Some have expressed interest in making general use of the the pci_restore_bars function, so that has been exported to GPL licensed modules. Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* pci: make bus resource start address override minimum IO addressLinus Torvalds2005-08-021-1/+3
| | | | | | | | | | | | | | The reason we have PCIBIOS_MIN_IO and PCIBIOS_MIN_CARDBUS_IO is because we want to protect badly documented motherboard PCI resources and thus don't want to allocate new resources in low IO/MEM space. However, if we have already discovered a PCI bridge with a specified resource base, that should override that decision. This change will allow us to move the "careful" region upwards without resulting in problems allocating resources in low mappings. This was brought on by us having allocated a bus resource at 0x1000, conflicting with a undocumented VAIO Sony PI resources.
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