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path: root/drivers/pci/host/pcie-designware.c
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* PCI: Fix whitespace, capitalization, and spelling errorsBjorn Helgaas2013-11-141-1/+1
| | | | | | | | | Fix whitespace, capitalization, and spelling errors. No functional change. I know "busses" is not an error, but "buses" was more common, so I used it consistently. Signed-off-by: Marta Rybczynska <rybczynska@gmail.com> (pci_reset_bridge_secondary_bus()) Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* PCI: designware: Add irq_create_mapping()Pratyush Anand2013-10-091-12/+13
| | | | | | | | | | Without irq_create_mapping(), the correct IRQ number cannot be provided. In this case, it makes problems such as NULL dereference. Thus, irq_create_mapping() should be added for MSI. Suggested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: designware: Make dw_pcie_rd_own_conf(), etc., staticBjorn Helgaas2013-10-091-8/+8
| | | | | | | | | | | | | | The following variables and functions are used only in pcie-designware.c, so make them static: global_io_offset dw_pcie_rd_own_conf() dw_pcie_wr_own_conf() dw_pcie_setup() dw_pcie_scan_bus() dw_pcie_map_irq() Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com>
* PCI: exynos: Add support for MSIJingoo Han2013-09-251-0/+240
| | | | | | | | | | | This patch adds support for Message Signaled Interrupt in the Exynos PCIe driver using Synopsys designware PCIe core IP. Signed-off-by: Siva Reddy Kallam <siva.kallam@samsung.com> Signed-off-by: Srikanth T Shivanand <ts.srikanth@samsung.com> Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
* PCI: designware: Drop "addr" arg from dw_pcie_readl_rc()/dw_pcie_writel_rc()Seungwon Jeon2013-08-291-80/+55
| | | | | | | | | | | | | The "dbi_addr" argument to dw_pcie_readl_rc() and dw_pcie_writel_rc() is redundant and misleading because we always have the "struct pcie_port" and we always want to use the address from there. This patch removes the argument and changes the callers to match. No functional change. [bhelgaas: changelog] Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com>
* PCI: exynos: Split into Synopsys part and Exynos partJingoo Han2013-08-121-739/+272
| | | | | | | | | | | | | | Exynos PCIe IP consists of Synopsys specific part and Exynos specific part. Only core block is a Synopsys Designware part; other parts are Exynos specific. Also, the Synopsys Designware part can be shared with other platforms; thus, it can be split two parts such as Synopsys Designware part and Exynos specific part. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
* pci: Add PCIe driver for Samsung ExynosJingoo Han2013-06-261-0/+1057
Exynos5440 has a PCIe controller which can be used as Root Complex. This driver supports a PCIe controller as Root Complex mode. Signed-off-by: Surendranath Gurivireddy Balla <suren.reddy@samsung.com> Signed-off-by: Siva Reddy Kallam <siva.kallam@samsung.com> Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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