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* mtd: spi-nor: Rework the disabling of block write protectionTudor Ambarus2019-11-111-90/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spi_nor_unlock() unlocks blocks of memory or the entire flash memory array, if requested. clear_sr_bp() unlocks the entire flash memory array at boot time. This calls for some unification, clear_sr_bp() is just an optimization for the case when the unlock request covers the entire flash size. Get rid of clear_sr_bp() and introduce spi_nor_unlock_all(), which is just a call to spi_nor_unlock() for the entire flash memory array. This fixes a bug that was present in spi_nor_spansion_clear_sr_bp(). When the QE bit was zero, we used the Write Status (01h) command with one data byte, which might cleared the Status Register 2. We now always use the Write Status (01h) command with two data bytes when SNOR_F_HAS_16BIT_SR is set, to avoid clearing the Status Register 2. The SNOR_F_NO_READ_CR case is treated as well. When the flash doesn't support the CR Read command, we make an assumption about the value of the QE bit. In spi_nor_init(), call spi_nor_quad_enable() first, then spi_nor_unlock_all(), so that at the spi_nor_unlock_all() time we can be sure the QE bit has value one, because of the previous call to spi_nor_quad_enable(). Get rid of the MFR handling and implement specific manufacturer default_init() fixup hooks. Note that this changes a bit the logic for the SNOR_MFR_ATMEL, SNOR_MFR_INTEL and SNOR_MFR_SST cases. Before this patch, the Atmel, Intel and SST chips did not set the locking ops, but unlocked the entire flash at boot time, while now they are setting the locking ops to stm_locking_ops. This should work, since the disable of the block protection at the boot time used the same Status Register bits to unlock the flash, as in the stm_locking_ops case. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()Tudor Ambarus2019-11-111-5/+115
| | | | | | | | | | | | | | | | | | | | | | | Make sure that when doing a lock() or an unlock() operation we don't clear the QE bit from Status Register 2. JESD216 revB or later offers information about the *default* Status Register commands to use (see BFPT DWORDS[15], bits 22:20). In this standard, Status Register 1 refers to the first data byte transferred on a Read Status (05h) or Write Status (01h) command. Status register 2 refers to the byte read using instruction 35h. Status register 2 is the second byte transferred in a Write Status (01h) command. Industry naming and definitions of these Status Registers may differ. The definitions are described in JESD216B, BFPT DWORDS[15], bits 22:20. There are cases in which writing only one byte to the Status Register 1 has the side-effect of clearing Status Register 2 and implicitly the Quad Enable bit. This side-effect is hit just by the BFPT_DWORD15_QER_SR2_BIT1_BUGGY and BFPT_DWORD15_QER_SR2_BIT1 cases. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Print debug message when the read back test failsTudor Ambarus2019-11-071-1/+6
| | | | | | | Demystify where the EIO error occurs. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Check all the bits written, not just the BP onesTudor Ambarus2019-11-071-5/+4
| | | | | | | | | Check that all the bits written in the write_sr_and_check() method match the status_new received value. Failing to write the other bits is dangerous too, extend the check. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Fix errno on Quad Enable methodsTudor Ambarus2019-11-071-3/+3
| | | | | | | | | When the Read-Modify-Write-Read-Back Quad Enable methods failed on the Read-Back, they returned -EINVAL. Since this is an I/O error, return -EIO. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Drop spansion_quad_enable()Tudor Ambarus2019-11-071-53/+5
| | | | | | | | | | | | | | | | | | | | | Drop the default spansion_quad_enable() method and replace it with spansion_read_cr_quad_enable(). The function was buggy, it didn't care about the previous values of the Status and Configuration Registers. spansion_read_cr_quad_enable() is a Read-Modify-Write-Check function that keeps track of what were the previous values of the Status and Configuration Registers. In terms of instruction types sent to the flash, the only difference between the spansion_quad_enable() and spansion_read_cr_quad_enable() is that the later calls spi_nor_read_sr(). We can safely assume that all flashes support spi_nor_read_sr(), because all flashes call it in spi_nor_sr_ready(). The transition from spansion_quad_enable() to spansion_read_cr_quad_enable() will not affect anybody, drop the buggy code. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Describe all the Reg OpsTudor Ambarus2019-11-071-11/+127
| | | | | | | Document all the Register Operations. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Merge spi_nor_write_sr() and spi_nor_write_sr_cr()Tudor Ambarus2019-11-071-51/+23
| | | | | | | | | | | | | | Merge static int spi_nor_write_sr(struct spi_nor *nor, u8 val) static int spi_nor_write_sr_cr(struct spi_nor *nor, const u8 *sr_cr) into static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) The Status Register can be written with one or two bytes. Merge the two functions to avoid code duplication. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Move the WE and wait calls inside Write SR methodsTudor Ambarus2019-11-071-64/+44
| | | | | | | | | | | Avoid duplicating code by moving the calls to spi_nor_write_enable() and spi_nor_wait_till_ready() inside the Write Status Register methods. Move spi_nor_write_sr() to avoid forward declaration of spi_nor_wait_till_ready(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr()Tudor Ambarus2019-11-071-6/+2
| | | | | | | | | spi_nor_clear_sr() and spi_nor_clear_fsr() are called just in case of errors. The callers didn't check their return value, make them of type void. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Rename label as it is no longer genericTudor Ambarus2019-11-071-11/+11
| | | | | | | | Rename 'sst_write_err' label to 'out' as it is no longer generic for all the errors in the sst_write() method, and may introduce confusion. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Check for errors after each Register OperationTudor Ambarus2019-11-071-21/+60
| | | | | | | Check for the return vales of each Register Operation. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Print debug info inside Reg Ops methodsTudor Ambarus2019-11-071-42/+127
| | | | | | | Spare the callers of printing debug messages by themselves. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: Use dev_dbg insted of dev_err for low level infoTudor Ambarus2019-11-071-21/+21
| | | | | | | | | | | | | | | | | What most users care about is "my dev is not working properly". All low level information should be discovered when activating the debug traces. Keep error messages just for the following cases: - when the SR/FSR report program or erase fails, or attempts of modifying a protected sector, - when the JEDEC ID is not recognized, - when the resume() call fails, - when the spi_nor_check() fails. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* mtd: spi-nor: fix silent truncation in spi_nor_read_raw()Sergei Shtylyov2019-11-021-1/+1
| | | | | | | | | | | spi_nor_read_raw() assigns the result of 'ssize_t spi_nor_read_data()' to the 'int ret' variable, while 'ssize_t' is a 64-bit type and *int* is a 32-bit type on the 64-bit machines. This silent truncation isn't really valid, so fix up the variable's type. Fixes: f384b352cbf0 ("mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* mtd: spi-nor: fix silent truncation in spi_nor_read()Sergei Shtylyov2019-11-021-1/+1
| | | | | | | | | | | spi_nor_read() assigns the result of 'ssize_t spi_nor_read_data()' to the 'int ret' variable, while 'ssize_t' is a 64-bit type and *int* is a 32-bit type on the 64-bit machines. This silent truncation isn't really valid, so fix up the variable's type. Fixes: 59451e1233bd ("mtd: spi-nor: change return value of read/write") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* mtd: spi-nor: intel-spi: Add support for Intel Comet Lake-H SPI serial flashMika Westerberg2019-11-021-0/+1
| | | | | | | | Intel Comet Lake-H PCH has the same SPI serial flash controller as Comet Lake-LP. Add Comet Lake-H PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* mtd: spi-nor: Print device info in case of errorTudor Ambarus2019-11-021-2/+2
| | | | | | | Print identifying information about struct device. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Constify data to write to the Status RegisterTudor Ambarus2019-11-011-2/+2
| | | | | | | Constify the data to write to the Status Register. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Fix retlen handling in sst_write()Tudor Ambarus2019-11-011-4/+5
| | | | | | | | | In case the write of the first byte failed, retlen was incorrectly incremented to *retlen += actual; on the exit path. retlen should be incremented when actual data was written to the flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Drop redundant error reports in Reg Ops callersTudor Ambarus2019-11-011-40/+10
| | | | | | | | Drop the error messages from the callers, since the callees already print an error message in case of failure. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Pointer parameter for CR in spi_nor_read_cr()Tudor Ambarus2019-11-011-25/+30
| | | | | | | | | | | | Let the callers pass the pointer to the DMA-able buffer where the value of the Configuration Register will be written. This way we avoid the casts between int and u8, which can be confusing. Callers stop compare the return value of spi_nor_read_cr() with negative, spi_nor_read_cr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Pointer parameter for FSR in spi_nor_read_fsr()Tudor Ambarus2019-11-011-18/+20
| | | | | | | | | | | | Let the callers pass the pointer to the DMA-able buffer where the value of the Flag Status Register will be written. This way we avoid the casts between int and u8, which can be confusing. Caller stops compare the return value of spi_nor_read_fsr() with negative, spi_nor_read_fsr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Pointer parameter for SR in spi_nor_read_sr()Tudor Ambarus2019-11-011-53/+64
| | | | | | | | | | | | Let the callers pass the pointer to the DMA-able buffer where the value of the Status Register will be written. This way we avoid the casts between int and u8, which can be confusing. Callers stop compare the return value of spi_nor_read_sr() with negative, spi_nor_read_sr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Don't overwrite errno from Reg OpsTudor Ambarus2019-11-011-7/+6
| | | | | | | | Do not overwrite the error numbers received the Register Operations methods. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Drop explicit cast to int to already int valueTudor Ambarus2019-11-011-9/+6
| | | | | | | ret is already of type int. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Stop compare with negative in Reg Ops methodsTudor Ambarus2019-11-011-10/+13
| | | | | | | | | | | | | | spi_mem_exec_op() nor->controller_ops->write_reg() nor->controller_ops->read_reg() spi_nor_wait_till_ready() Return 0 on success, -errno otherwise. Stop compare with negative and compare with zero in all the register operations methods. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Group all Reg Ops to avoid forward declarationsTudor Ambarus2019-11-011-213/+213
| | | | | | | | Group all register methods up in the file, to avoid forward declarations. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Drop duplicated new lineTudor Ambarus2019-11-011-1/+0
| | | | | | | Two new lines, one after another, drop one. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Prepend spi_nor_ to all Reg Ops methodsTudor Ambarus2019-11-011-54/+56
| | | | | | | All the core functions should begin with "spi_nor_". Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definitionTudor Ambarus2019-10-231-8/+7
| | | | | | | | | | | n_tx was never used, drop it. Replace 'const u8 *txbuf' with 'u8 opcode', to comply with the SPI NOR int (*read_reg)() method. The 'const' qualifier has no meaning for parameters passed by value, drop it. Going furher, the opcode was passed to cqspi_calc_rdreg() and never used, drop it. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: Introduce 'struct spi_nor_controller_ops'Tudor Ambarus2019-10-237-96/+136
| | | | | | | | | | | | | | Move all SPI NOR controller driver specific ops in a dedicated structure. 'struct spi_nor' becomes lighter. Use size_t for lengths in 'int (*write_reg)()' and 'int (*read_reg)()'. Rename wite/read_buf to buf, the name of the functions are suggestive enough. Constify buf in int (*write_reg). Comply with these changes in the SPI NOR controller drivers. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignmentTudor Ambarus2019-10-231-1/+0
| | | | | | | The pointer to 'struct spi_nor' is kzalloc'ed above in the code. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
* mtd: spi-nor: add support for en25qh16DENG Qingfang2019-10-231-0/+2
| | | | | | | | | | Tested on HiWiFi C526A Datasheet is available at: http://www.xinyahong.com/upLoad/product/month_1411/201411201256018276.pdf Signed-off-by: DENG Qingfang <dqfext@gmail.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* mtd: spi-nor: intel-spi: add support for Intel Cannon Lake SPI flashJethro Beekman2019-10-232-0/+16
| | | | | | | | | | | Now that SPI flash controllers without a software sequencer are supported, it's trivial to add support for CNL and its PCI ID. Values from https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/300-series-chipset-pch-datasheet-vol-2.pdf Signed-off-by: Jethro Beekman <jethro@fortanix.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* mtd: spi-nor: intel-spi: support chips without software sequencerJethro Beekman2019-10-231-7/+16
| | | | | | | | | | | | Some flash controllers don't have a software sequencer. Avoid configuring the register addresses for it, and double check everywhere that its not accidentally trying to be used. Every use of `sregs` is now guarded by a check of `sregs` or `swseq_reg`. The check might be done in the calling function. Signed-off-by: Jethro Beekman <jethro@fortanix.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* mtd: rawnand: au1550nd: Fix au_read_buf16() prototypePaul Burton2019-10-071-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7e534323c416 ("mtd: rawnand: Pass a nand_chip object to chip->read_xxx() hooks") modified the prototype of the struct nand_chip read_buf function pointer. In the au1550nd driver we have 2 implementations of read_buf. The previously mentioned commit modified the au_read_buf() implementation to match the function pointer, but not au_read_buf16(). This results in a compiler warning for MIPS db1xxx_defconfig builds: drivers/mtd/nand/raw/au1550nd.c:443:57: warning: pointer type mismatch in conditional expression Fix this by updating the prototype of au_read_buf16() to take a struct nand_chip pointer as its first argument, as is expected after commit 7e534323c416 ("mtd: rawnand: Pass a nand_chip object to chip->read_xxx() hooks"). Note that this shouldn't have caused any functional issues at runtime, since the offset of the struct mtd_info within struct nand_chip is 0 making mtd_to_nand() effectively a type-cast. Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes: 7e534323c416 ("mtd: rawnand: Pass a nand_chip object to chip->read_xxx() hooks") Cc: stable@vger.kernel.org # v4.20+ Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
* mtd: spi-nor: Fix direction of the write_sr() transferTudor Ambarus2019-10-041-1/+1
| | | | | | | | | | | write_sr() sends data to the SPI memory, fix the direction. Fixes: b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c") Reported-by: John Garry <john.garry@huawei.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: John Garry <john.garry@huawei.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
* Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds2019-09-223-544/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Paul Burton: "Main MIPS changes: - boot_mem_map is removed, providing a nice cleanup made possible by the recent removal of bootmem. - Some fixes to atomics, in general providing compiler barriers for smp_mb__{before,after}_atomic plus fixes specific to Loongson CPUs or MIPS32 systems using cmpxchg64(). - Conversion to the new generic VDSO infrastructure courtesy of Vincenzo Frascino. - Removal of undefined behavior in set_io_port_base(), fixing the behavior of some MIPS kernel configurations when built with recent clang versions. - Initial MIPS32 huge page support, functional on at least Ingenic SoCs. - pte_special() is now supported for some configurations, allowing among other things generic fast GUP to be used. - Miscellaneous fixes & cleanups. And platform specific changes: - Major improvements to Ingenic SoC support from Paul Cercueil, mostly enabled by the inclusion of the new TCU (timer-counter unit) drivers he's spent a very patient year or so working on. Plus some fixes for X1000 SoCs from Zhou Yanjie. - Netgear R6200 v1 systems are now supported by the bcm47xx platform. - DT updates for BMIPS, Lantiq & Microsemi Ocelot systems" * tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (89 commits) MIPS: Detect bad _PFN_SHIFT values MIPS: Disable pte_special() for MIPS32 with RiXi MIPS: ralink: deactivate PCI support for SOC_MT7621 mips: compat: vdso: Use legacy syscalls as fallback MIPS: Drop Loongson _CACHE_* definitions MIPS: tlbex: Remove cpu_has_local_ebase MIPS: tlbex: Simplify r3k check MIPS: Select R3k-style TLB in Kconfig MIPS: PCI: refactor ioc3 special handling mips: remove ioremap_cachable mips/atomic: Fix smp_mb__{before,after}_atomic() mips/atomic: Fix loongson_llsc_mb() wreckage mips/atomic: Fix cmpxchg64 barriers MIPS: Octeon: remove duplicated include from dma-octeon.c firmware: bcm47xx_nvram: Allow COMPILE_TEST firmware: bcm47xx_nvram: Correct size_t printf format MIPS: Treat Loongson Extensions as ASEs MIPS: Remove dev_err() usage after platform_get_irq() MIPS: dts: mscc: describe the PTP ready interrupt MIPS: dts: mscc: describe the PTP register range ...
| * mtd: rawnand: Drop obsolete JZ4740 NAND driverPaul Cercueil2019-07-303-544/+0
| | | | | | | | | | | | | | | | | | It has been replaced with the newer Ingenic NAND driver. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: Artur Rojek <contact@artur-rojek.eu> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com>
* | Merge tag 'upstream-5.4-rc1' of ↵Linus Torvalds2019-09-213-11/+44
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs Pull UBI, UBIFS and JFFS2 updates from Richard Weinberger: "UBI: - Be less stupid when placing a fastmap anchor - Try harder to get an empty PEB in case of contention - Make ubiblock to warn if image is not a multiple of 512 UBIFS: - Various fixes in error paths JFFS2: - Various fixes in error paths" * tag 'upstream-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs: jffs2: Fix memory leak in jffs2_scan_eraseblock() error path jffs2: Remove jffs2_gc_fetch_page and jffs2_gc_release_page jffs2: Fix possible null-pointer dereferences in jffs2_add_frag_to_fragtree() ubi: block: Warn if volume size is not multiple of 512 ubifs: Fix memory leak bug in alloc_ubifs_info() error path ubifs: Fix memory leak in __ubifs_node_verify_hmac error path ubifs: Fix memory leak in read_znode() error path ubi: ubi_wl_get_peb: Increase the number of attempts while getting PEB ubi: Don't do anchor move within fastmap area ubifs: Remove redundant assignment to pointer fname
| * | ubi: block: Warn if volume size is not multiple of 512Richard Weinberger2019-09-151-8/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If volume size is not a multiple of 512, ubi block cuts off the last bytes of an volume since the block layer works on 512 byte sectors. This can happen especially on NOR flash with minimal io size of 1. To avoid unpleasant surprises, print a warning. Signed-off-by: Richard Weinberger <richard@nod.at>
| * | ubi: ubi_wl_get_peb: Increase the number of attempts while getting PEBZhihao Cheng2019-09-151-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Running stress test io_paral (A pressure ubi test in mtd-utils) on an UBI device with fewer PEBs (fastmap enabled) may cause ENOSPC errors and make UBI device read-only, but there are still free PEBs on the UBI device. This problem can be easily reproduced by performing the following steps on a 2-core machine: $ modprobe nandsim first_id_byte=0x20 second_id_byte=0x33 parts=80 $ modprobe ubi mtd="0,0" fm_autoconvert $ ./io_paral /dev/ubi0 We may see the following verbose: (output) [io_paral] update_volume():108: failed to write 380 bytes at offset 95920 of volume 2 [io_paral] update_volume():109: update: 97088 bytes [io_paral] write_thread():227: function pwrite() failed with error 28 (No space left on device) [io_paral] write_thread():229: cannot write 15872 bytes to offs 31744, wrote -1 (dmesg) ubi0 error: ubi_wl_get_peb [ubi]: Unable to get a free PEB from user WL pool ubi0 warning: ubi_eba_write_leb [ubi]: switch to read-only mode CPU: 0 PID: 2027 Comm: io_paral Not tainted 5.3.0-rc2-00001-g5986cd0 #9 ubi0 warning: try_write_vid_and_data [ubi]: failed to write VID header to LEB 2:5, PEB 18 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.12.0 -0-ga698c8995f-prebuilt.qemu.org 04/01/2014 Call Trace: dump_stack+0x85/0xba ubi_eba_write_leb+0xa1e/0xa40 [ubi] vol_cdev_write+0x307/0x520 [ubi] vfs_write+0xfa/0x280 ksys_pwrite64+0xc5/0xe0 __x64_sys_pwrite64+0x22/0x30 do_syscall_64+0xbf/0x440 In function ubi_wl_get_peb, the operation of filling the pool (ubi_update_fastmap) with free PEBs and fetching a free PEB from the pool is not atomic. After thread A filling the pool with free PEB, free PEB may be taken away by thread B. When thread A checks the expression again, the condition is still unsatisfactory. At this time, there may still be free PEBs on UBI that can be filled into the pool. This patch increases the number of attempts to obtain PEB. An extreme case (No free PEBs left after creating test volumes) has been tested on different type of machines for 100 times. The biggest number of attempts are shown below: x86_64 arm64 2-core 4 4 4-core 8 4 8-core 4 4 Signed-off-by: Zhihao Cheng <chengzhihao1@huawei.com> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | ubi: Don't do anchor move within fastmap areaRichard Weinberger2019-09-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make sure that Fastmap can use a PEB within the first 64 PEBs, UBI moves blocks away from that area. It uses regular wear-leveling for that job. An anchor move can be triggered if no PEB is free in this area or because of anticipation. In the latter case it can happen that UBI decides to move a block but finds a free PEB within the same area. This case is in vain an increases only erase counters. Catch this case and cancel wear-leveling if this happens. Signed-off-by: Richard Weinberger <richard@nod.at>
* | | Merge tag 'mtd/for-5.4' of ↵Linus Torvalds2019-09-2143-1414/+2273
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Richard Weinberger: "MTD core changes: - add debugfs nodes for querying the flash name and id - mtd parser reorganization SPI NOR core changes: - always use bounce buffer for register read/writes - move m25p80 code in spi-nor.c - rework hwcaps selection for the spi-mem case - rework the core in order to move the manufacturer specific code out of it: - regroup flash parameters in 'struct spi_nor_flash_parameter' - add default_init() and post_sfdp() hooks to tweak the flash parameters - introduce the ->set_4byte(), ->convert_addr() and ->setup() methods, to deal with manufacturer specific code - rework the SPI NOR lock/unlock logic - fix an error code in spi_nor_read_raw() - fix a memory leak bug - enable the debugfs for the partname and partid - add support for few flashes SPI NOR controller drivers changes: - intel-spi: - Whitelist 4B read commands - Add support for Intel Tiger Lake SPI serial flash - aspeed-smc: Add of_node_put() - hisi-sfc: add of_node_put() - cadence-quadspi: Fix QSPI RCU Schedule Stall NAND core: - Fixing typos - Adding missing of_node_put() in various drivers Raw NAND controller drivers: - Macronix: new controller driver - Omap2: fix the number of bitflips returned - Brcmnand: fix a pointer not iterating over all the page chunks - W90x900: driver removed - Onenand: fix a memory leak - Sharpsl: missing include guard - STM32: avoid warnings when building with W=1 - Ingenic: fix a coccinelle warning - r852: call a helper to simplify the code CFI core: - Kill useless initializer in mtd_do_chip_probe() - Fix a rare write failure seen on some cfi_cmdset_0002 compliant Parallel NORs - Bunch of cleanups for cfi_cmdset_0002 driver's write functions by Tokunori Ikegami" * tag 'mtd/for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (77 commits) mtd: pmc551: Remove set but not used variable 'soff_lo' mtd: cfi_cmdset_0002: Fix do_erase_chip() to get chip as erasing mode mtd: sm_ftl: Fix memory leak in sm_init_zone() error path mtd: parsers: Move CMDLINE parser mtd: parsers: Move OF parser mtd: parsers: Move BCM63xx parser mtd: parsers: Move BCM47xx parser mtd: parsers: Move TI AR7 parser mtd: pismo: Simplify getting the adapter of a client mtd: phram: Module parameters add writable permissions mtd: pxa2xx: Use ioremap_cache insted of ioremap_cached mtd: spi-nor: Rename "n25q512a" to "mt25qu512a (n25q512a)" mtd: spi-nor: Add support for mt35xu02g mtd: rawnand: omap2: Fix number of bitflips reporting with ELM mtd: rawnand: brcmnand: Fix ecc chunk calculation for erased page bitfips mtd: spi-nor: remove superfluous pass of nor->info->sector_size mtd: spi-nor: enable the debugfs for the partname and partid mtd: mtdcore: add debugfs nodes for querying the flash name and id mtd: spi-nor: hisi-sfc: Add of_node_put() before break mtd: spi-nor: aspeed-smc: Add of_node_put() ...
| * | | mtd: pmc551: Remove set but not used variable 'soff_lo'zhengbin2019-09-151-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes gcc '-Wunused-but-set-variable' warning: drivers/mtd/devices/pmc551.c: In function pmc551_erase: drivers/mtd/devices/pmc551.c:142:15: warning: variable soff_lo set but not used [-Wunused-but-set-variable] drivers/mtd/devices/pmc551.c: In function pmc551_read: drivers/mtd/devices/pmc551.c:232:15: warning: variable soff_lo set but not used [-Wunused-but-set-variable] drivers/mtd/devices/pmc551.c: In function pmc551_write: drivers/mtd/devices/pmc551.c:289:15: warning: variable soff_lo set but not used [-Wunused-but-set-variable] It is not used since commit cdf0a7d16980 ("[MTD] pmc551 whitespace cleanup") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: zhengbin <zhengbin13@huawei.com> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | | mtd: cfi_cmdset_0002: Fix do_erase_chip() to get chip as erasing modeTokunori Ikegami2019-09-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The chip state is set to erasing by the function after getting chip. So it should be to get chip as erasing mode at first. But previously it was to get chip as writing mode then fix as erasing. Signed-off-by: Tokunori Ikegami <ikegami.t@gmail.com> Cc: linux-mtd@lists.infradead.org Signed-off-by: Richard Weinberger <richard@nod.at>
| * | | mtd: sm_ftl: Fix memory leak in sm_init_zone() error pathWenwen Wang2019-09-151-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In sm_init_zone(), 'zone->lba_to_phys_table' is allocated through kmalloc_array() and 'zone->free_sectors' is allocated in kfifo_alloc() respectively. However, they are not deallocated in the following execution if sm_read_sector() fails, leading to memory leaks. To fix this issue, free them before returning -EIO. Signed-off-by: Wenwen Wang <wenwen@cs.uga.edu> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | | mtd: parsers: Move CMDLINE parserLinus Walleij2019-09-155-38/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This moves the CMDLINE partition parser down into the parser subdirectory. No functional change. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | | mtd: parsers: Move OF parserLinus Walleij2019-09-155-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This moves the OF/device tree partition parser down into the parser subdirectory. No functional change. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Richard Weinberger <richard@nod.at>
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