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path: root/drivers/mtd/spi-nor/Kconfig
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* spi-nor: intel-spi: Remove EXPERT dependencyBin Meng2017-10-251-2/+2
| | | | | | | | | | | | | The idea to have the intel-spi driver dependent on EXPERT was exactly because we did not want ordinary users playing with the device and inadvertently overwrite their BIOSes (if it is not protected). This seems to be superfluous hence remove it. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
* mtd: spi-nor: Allow Cadence QSPI support for ARM64Thor Thayer2017-10-101-1/+1
| | | | | | | | | Allow ARM64 support for the Cadence QSPI interface by adding ARM64 as a dependency. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
* mtd: spi-nor: intel-spi: Add support for Intel Denverton SPI serial flash ↵Mika Westerberg2017-08-011-0/+16
| | | | | | | | | | controller Intel Denverton exposes the SPI serial flash controller as a PCI device instead of being part of the LPC chip as previous generations did. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
* mtd: spi-nor: stm32-quadspi: allow building with COMPILE_TESTBrian Norris2017-05-151-1/+1
| | | | | | Cc: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
* mtd: spi-nor: add driver for STM32 quad spi flash controllerLudovic Barre2017-05-011-0/+7
| | | | | | | | | | | | | | | | The quadspi is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the following modes: -indirect mode: all the operations are performed using the quadspi registers -read memory-mapped mode: the external Flash memory is mapped to the microcontroller address space and is seen by the system as if it was an internal memory Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* Merge tag 'ib-mfd-mtd-v4.11' of ↵Cyrille Pitchen2017-02-101-0/+20
|\ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd From Lee Jones: """ Immutable branch between MFD and MTD due for the v4.11 merge window """
| * spi-nor: Add support for Intel SPI serial flash controllerMika Westerberg2017-01-031-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the SPI serial flash host controller found on many Intel CPUs including Baytrail and Braswell. The SPI serial flash controller is used to access BIOS and other platform specific information. By default the driver exposes a single read-only MTD device but with a module parameter "writeable=1" the MTD device can be made read-write which makes it possible to upgrade BIOS directly from Linux. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* | mtd: aspeed: add memory controllers for the Aspeed AST2400 SoCCédric Le Goater2017-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver adds mtd support for the Aspeed AST2400 SoC static memory controllers: * New Static Memory Controller (referred as FMC) . BMC firmware . AST2500 compatible register set . 5 chip select pins (CE0 ∼ CE4) . supports NOR flash, NAND flash and SPI flash memory. * SPI Flash Controller (SPI) . host Firmware . slightly different register set, between AST2500 and the legacy controller . supports SPI flash memory . 1 chip select pin (CE0) The legacy static memory controller (referred as SMC) is not supported, as well as types other than SPI. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* | mtd: spi-nor: add memory controllers for the Aspeed AST2500 SoCCédric Le Goater2017-02-101-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver adds mtd support for the Aspeed AST2500 SoC static memory controllers : * Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . supports SPI type flash memory (CE0-CE1) . CE2 can be of NOR type flash but this is not supported by the driver * SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . supports SPI type flash memory Each controller has a memory range on which it maps its flash module slaves. Each slave is assigned a memory window for its mapping that can be changed at bootime with the Segment Address Register. Each SPI flash slave can then be accessed in two modes: Command and User. When in User mode, accesses to the memory segment of the slaves are translated in SPI transfers. When in Command mode, the HW generates the SPI commands automatically and the memory segment is accessed as if doing a MMIO. Currently, only the User mode is supported. Command mode needs a little more work to check that the memory window on the AHB bus fits the module size. Based on previous work from Milton D. Miller II <miltonm@us.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* | mtd: spi-nor: cqspi: Fix build on arches missing readsl/writeslMarek Vasut2017-01-041-1/+1
|/ | | | | | | | | | | | | | | | | The x86-64 and some other architectures are missing readsl/writesl functions, so this driver won't build on them. Use a more portable ioread32_rep()/iowrite32_rep() instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alan Tull <atull@opensource.altera.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Graham Moore <grmoore@opensource.altera.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Yves Vandervennet <yvanderv@opensource.altera.com> Suggested-by: Stefan Roese <sr@denx.de> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* mtd: spi-nor: don't build Cadence QuadSPI on non-ARMBrian Norris2016-07-191-1/+1
| | | | | | | | | | This controller driver is used only on ARM but is mostly written portably so it can build on other arch'es. Unfortunately, at least x86 doesn't provibe readsl()/writesl() accessors. We could possibly fix this issue in the future by using io{read,write}32_rep() instead, but let's just drop the architectures we aren't using for now. Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: Add driver for Cadence Quad SPI Flash ControllerGraham Moore2016-07-181-0/+11
| | | | | | | | | | | | | | | | | | Add support for the Cadence QSPI controller. This controller is present in the Altera SoCFPGA SoCs and this driver has been tested on the Cyclone V SoC. Signed-off-by: Graham Moore <grmoore@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alan Tull <atull@opensource.altera.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Graham Moore <grmoore@opensource.altera.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Yves Vandervennet <yvanderv@opensource.altera.com> Cc: devicetree@vger.kernel.org Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: atmel-quadspi: add driver for Atmel QSPI controllerCyrille Pitchen2016-07-151-0/+9
| | | | | | | | | | This driver add support to the new Atmel QSPI controller embedded into sama5d2x SoCs. It expects a NOR memory to be connected to the QSPI controller. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: add hisilicon spi-nor flash controller driverJiancheng Xue2016-07-131-0/+7
| | | | | | | | | | | | Add hisilicon spi-nor flash controller driver Signed-off-by: Binquan Peng <pengbinquan@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: fsl-quadspi: add support for layerscapeYao Yuan2016-03-071-1/+1
| | | | | | | | | LS1043a and LS2080A in the Layerscape family also support Freescale Quad SPI, make Quad SPI selectable for these hardwares. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: fsl-quadspi: add support for ls1021aYao Yuan2016-03-071-1/+1
| | | | | | | | | | | LS1021a also support Freescale Quad SPI controller. Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI selectable for LS1021A SOC hardwares. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Acked-by: Han xu <han.xu@freescale.com> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: Fix dependencies for !HAS_IOMEM archsRichard Weinberger2016-01-261-0/+1
| | | | | | | | | Not every arch has io memory. So, unbreak the build by fixing the dependencies. Signed-off-by: Richard Weinberger <richard@nod.at> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: mtk-nor: new Mediatek serial flash controller driverBayi Cheng2015-11-201-0/+7
| | | | | | | Add spi nor flash driver for mediatek controller Signed-off-by: Bayi Cheng <bayi.cheng@mediatek.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: fsl-quadspi: allow building for other ARCHes with COMPILE_TESTBrian Norris2015-10-191-1/+2
| | | | | | | | This driver doesn't actually need ARCH_MXC to compile. Relax the constraints. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Han xu <han.xu@freescale.com>
* mtd: spi-nor: Improve Kconfig help text for SPI_FSL_QUADSPIFabio Estevam2015-08-141-1/+2
| | | | | | | | | The current "We only connect the NOR to this controller now." text is not very clear, so explain it better by saying that generic SPI is not supported by SPI_FSL_QUADSPI and only SPI NOR is. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: add driver for NXP SPI Flash Interface (SPIFI)Joachim Eastwood2015-08-141-0/+11
| | | | | | | | | | | | | | | Add SPI-NOR driver for the SPI Flash Interface (SPIFI) controller that is found on newer NXP MCU devices. The controller supports serial SPI Flash devices with 1-, 2- and 4-bit width in either SPI mode 0 or 3. The controller can operate in either command or memory mode. In memory mode the Flash is exposed as normal memory and can be directly accessed by the CPU. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: add Kconfig option to disable 4K sectorsRafał Miłecki2014-09-281-0/+14
| | | | | | | | | | | | | | | | | | | | | | Current situation with 4K sectors is quite messy. First of all, some MTD "users" don't work with such small size. An example may be UBIFS which requires 15 KiB erase blocks as a minimum. In theory spi-nor should provide multiple erase regions and MTD "users" should use the one they need. Unforunately that is not implemented. In the result our flashes database in spi-nor is hackish. For some flashes we pretend they don't support 4K sectors just because some distribution uses UBIFS on it. This ofc leads to conflicts, like Samsung using w25q128 with 4K sectors vs. OpenWrt requiring it to pretend it's 64 KiB blocks only. My idea (plan?) for fixing this situation: 1) Use real hw info (this requires a way for disabling 4K for now) 2) Provide detailed info about erase regions 3) Make UBIFS work with devices that support 4K sectors Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: allow to be built as moduleBrian Norris2014-04-141-2/+2
| | | | | | | | There's no reason this can't be a module. Also, give SPI-NOR its own submenu. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de>
* mtd: spi-nor: shorten Kconfig namingBrian Norris2014-04-141-3/+8
| | | | | | Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com>
* mtd: spi-nor: Add Freescale QuadSPI driverHuang Shijie2014-04-141-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (0) What is the QuadSPI controller? The QuadSPI(Quad Serial Peripheral Interface) acts as an interface to one single or two external serial flash devices, each with up to 4 bidirectional data lines. (1) The QuadSPI controller is driven by the LUT(Look-up Table) registers. The LUT registers are a look-up-table for sequences of instructions. A valid sequence consists of four LUT registers. (2) The definition of the LUT register shows below: --------------------------------------------------- | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | --------------------------------------------------- There are several types of INSTRx, such as: CMD : the SPI NOR command. ADDR : the address for the SPI NOR command. DUMMY : the dummy cycles needed by the SPI NOR command. .... There are several types of PADx, such as: PAD1 : use a singe I/O line. PAD2 : use two I/O lines. PAD4 : use quad I/O lines. .... (3) Test this driver with the JFFS2 and UBIFS: For jffs2: ------------- #flash_eraseall /dev/mtd0 #mount -t jffs2 /dev/mtdblock0 tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 For ubifs: ------------- #flash_eraseall /dev/mtd0 #ubiattach /dev/ubi_ctrl -m 0 #ubimkvol /dev/ubi0 -N test -m #mount -t ubifs ubi0:test tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: add the framework for SPI NORHuang Shijie2014-04-141-0/+6
This patch cloned most of the m25p80.c. In theory, it adds a new spi-nor layer. Before this patch, the layer is like: MTD ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip After this patch, the layer is like: MTD ------------------------ spi-nor ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip With the spi-nor controller driver(Freescale Quadspi), it looks like: MTD ------------------------ spi-nor ------------------------ fsl-quadspi ------------------------ SPI NOR chip New APIs: spi_nor_scan: used to scan a spi-nor flash. Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> [Brian: rebased to include additional m25p_ids[] entry] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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