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NVRAM is always placed at the end of device and it does not have to
start at the beginning of a block, so check few possible offsets.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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This reverts commit be3781b71ac03723b552dc156931620634ef1b22.
Some CFE bootloaders have NVRAM at offset 0x1000. With that patch we
were detecting such a bootloaders as a standard NVRAM partition.
Changing anything in this pseudo-NVRAM resulted in corrupted bootloader
and bricked device!
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Pull MTD update from David Woodhouse:
"Fairly unexciting MTD merge for 3.9:
- misc clean-ups in the MTD command-line partitioning parser
(cmdlinepart)
- add flash locking support for STmicro chips serial flash chips, as
well as for CFI command set 2 chips.
- new driver for the ELM error correction HW module found in various
TI chips, enable the OMAP NAND driver to use the ELM HW error
correction
- added number of new serial flash IDs
- various fixes and improvements in the gpmi NAND driver
- bcm47xx NAND driver improvements
- make the mtdpart module actually removable"
* tag 'for-linus-20130301' of git://git.infradead.org/linux-mtd: (45 commits)
mtd: map: BUG() in non handled cases
mtd: bcm47xxnflash: use pr_fmt for module prefix in messages
mtd: davinci_nand: Use managed resources
mtd: mtd_torturetest can cause stack overflows
mtd: physmap_of: Convert device allocation to managed devm_kzalloc()
mtd: at91: atmel_nand: for PMECC, add code to check the ONFI parameter ECC requirement.
mtd: atmel_nand: make pmecc-cap, pmecc-sector-size in dts is optional.
mtd: atmel_nand: avoid to report an error when lookup table offset is 0.
mtd: bcm47xxsflash: adjust names of bus-specific functions
mtd: bcm47xxpart: improve probing of nvram partition
mtd: bcm47xxpart: add support for other erase sizes
mtd: bcm47xxnflash: register this as normal driver
mtd: bcm47xxnflash: fix message
mtd: bcm47xxsflash: register this as normal driver
mtd: bcm47xxsflash: write number of written bytes
mtd: gpmi: add sanity check for the ECC
mtd: gpmi: set the Golois Field bit for mx6q's BCH
mtd: devices: elm: Removes <xx> literals in elm DT node
mtd: gpmi: fix a dereferencing freed memory error
mtd: fix the wrong timeo for panic_nand_wait()
...
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The nvram in the nvram partition does not start at the beginning of the
partition on every device. Sometimes they are stating in the middle of
a partition or the first 0x1000 bytes are free.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
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To make the partitions writable they should aligned to erase sizes of
the flash. If the erase size is small use 0x10000.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
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It's required for accessing trx header (usually re-calculating a
checksum) and for writing a new firmware.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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The nvram functions are exported and used by some normal drivers. To
prevent name clashes with ofter parts of the kernel code add a bcm47xx_
prefix in front of the function names and the header file name.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/4744/
Signed-off-by: John Crispin <blogic@openwrt.org>
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This driver provides parser detecting partitions on BCM47XX flash
memories. It has many differences in comparison to BCM63XX, like:
1) Different CFE with no more trivial MAGICs
2) More partitions types (board_data, ML, POT)
3) Supporting more than 1 flash on a device
which resulted in decision of writing new parser.
It uses generic mtd interface and was successfully tested with Netgear
WNDR4500 router which has 2 flash memories: serial one and NAND one.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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