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path: root/drivers/iommu/tegra-gart.c
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* iommu/tegra-gart: Staticize tegra_gart_pm_opsSachin Kamat2013-11-011-1/+1
| | | | | | | | 'tegra_gart_pm_ops' is local to this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
* iommu/tegra: gart: cleanup devm_* functions usageWei Yongjun2013-09-241-17/+2
| | | | | | | | | | The devm_[kzalloc|ioremap] functions allocates data that are released when a driver detaches. Thus, there is no reason to explicitly call devm_[kfree|iounmap] in probe or remove functions. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
* iommu/tegra: Print phys_addr_t using %paThierry Reding2013-09-241-3/+3
| | | | | | | | | | | When enabling LPAE on ARM, phys_addr_t becomes 64 bits wide and printing a variable of that type using a simple %x format specifier causes the compiler to complain. Change the format specifier to %pa, which is used specifically for variables of type phys_addr_t. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Joerg Roedel <joro@8bytes.org>
*-. Merge branches 'iommu/fixes', 'x86/vt-d', 'x86/amd', 'ppc/pamu', 'core' and ↵Joerg Roedel2013-05-021-2/+3
|\ \ | | | | | | | | | 'arm/tegra' into next
| | * iommu/tegra: Fix printk formats for dma_addr_tVarun Sethi2013-05-021-1/+2
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | Fix printk formats for dma_addr_t: drivers/iommu/tegra-smmu.c: In function 'smmu_iommu_iova_to_phys': >> drivers/iommu/tegra-smmu.c:774:2: warning: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'dma_addr_t' [-Wformat] -- drivers/iommu/tegra-gart.c: In function 'gart_iommu_iova_to_phys': >> drivers/iommu/tegra-gart.c:298:3: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'dma_addr_t' [-Wformat] Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
| * iommu/fsl: Make iova dma_addr_t in the iommu_iova_to_phys API.Varun Sethi2013-04-021-1/+1
|/ | | | | | | | This is required in case of PAMU, as it can support a window size of up to 64G (even on 32bit). Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
* iommu/tegra: assume CONFIG_OF in gart driverStephen Warren2013-02-191-3/+1
| | | | | | | | Tegra only supports, and always enables, device tree. Remove all ifdefs for DT support from the driver. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
* Drivers: iommu: remove __dev* attributes.Greg Kroah-Hartman2013-01-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Joerg Roedel <joro@8bytes.org> Cc: Ohad Ben-Cohen <ohad@wizery.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Omar Ramirez Luna <omar.luna@linaro.org> Cc: Mauro Carvalho Chehab <mchehab@redhat.com> Cc: Hiroshi Doyu <hdoyu@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Bharat Nihalani <bnihalani@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* iommu/tegra: gart: Move bus_set_iommu after probe for multi archHiroshi Doyu2012-11-281-1/+1
| | | | | | | | For a single image to support multiple SoCs(GART/SMMU). Reported-by: Arto Merilainen <amerilainen@nvidia.com> Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
* iommu/tegra: Implement DOMAIN_ATTR_GEOMETRY attributeHiroshi DOYU2012-07-111-0/+5
| | | | | | | Implement the attribute for the Tegra IOMMU drivers. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
* iommu/tegra: gart: Fix register offset correctlyHiroshi DOYU2012-05-111-3/+4
| | | | | | | | | | DT passes the exact GART register ranges without any overlapping with MC register ranges. GART register offset needs to be adjusted by one passed by DT correctly. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
* iommu: tegra/gart: Add device tree supportThierry Reding2012-04-161-0/+11
| | | | | | | | | This commit adds device tree support for the GART hardware available on NVIDIA Tegra 20 SoCs. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
* iommu: tegra/gart: use correct gart_deviceVandana Salve2012-04-161-1/+1
| | | | | | | | | | | Pass the correct gart device pointer. Reviewed-by: Vandana Salve <vsalve@nvidia.com> Tested-by: Vandana Salve <vsalve@nvidia.com> Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
* iommu/tegra-gart: fix spin_unlock in map failure pathLucas Stach2012-03-131-1/+1
| | | | | | | | This must have been messed up while merging, the intention was clearly to unlock there. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
* ARM: IOMMU: Tegra20: Add iommu_ops for GART driverHiroshi DOYU2012-01-261-0/+451
Tegra 20 IOMMU H/W, GART (Graphics Address Relocation Table). This patch implements struct iommu_ops for GART for the upper IOMMU API. This H/W module supports only single virtual address space(domain), and manages a single level 1-to-1 mapping H/W translation page table. [With small fixes by Joerg Roedel] Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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