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* drm/i915 Update Gen8 golden context batch bufferArmin Reese2014-11-041-157/+635
| | | | | | | | | The file drivers/gpu/drm/i915/intel_renderstate_gen8.c is updated to the version created by IGT null_state_gen Signed-off-by: Armin Reese <armin.c.reese@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Abort command parsing for chained batchesBrad Volkin2014-11-042-12/+30
| | | | | | | | | | | | | | | | | | | | libva uses chained batch buffers in a way that the command parser can't generally handle. Fortunately, libva doesn't need to write registers from batch buffers in the way that mesa does, so this patch causes the driver to fall back to non-secure dispatch if the parser detects a chained batch buffer. Note: The 2nd hunk to munge the error code of the parser looks a bit superflous. At least until we have the batch copy code ready and can run the cmd parser in granting mode. But it isn't since we still need to let existing libva buffers pass (though not with elevated privs ofc!). Testcase: igt/gem_exec_parse/chained-batch Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com> [danvet: Add note - this confused me in review and Brad clarified things (after a few mails ...).] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Update plane parameters for cursor plane (v2)Sonika Jindal2014-11-041-0/+12
| | | | | | | | | | | | | | | This allows the cursor plane to be updated the same way as primary and sprites, and same set_property handler is used for all of these planes. v2 (by Matt Roper): Rework to apply to latest di-nightly codebase. The switch to split check/commit plane programming changed the code flow enough that the original patch could no longer be applied. Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Tested-by (IVB): Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Move flags describing VMA mappings into the VMATvrtko Ursulin2014-11-049-35/+36
| | | | | | | | | | | | If these flags are on the object level it will be more difficult to allow for multiple VMAs per object. v2: Simplification and cleanup after code review comments (Chris Wilson). Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* Merge tag 'drm-intel-next-2014-10-24' of ↵Dave Airlie2014-11-0423-936/+1140
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm-intel into drm-next - suspend/resume/freeze/thaw unification from Imre - wa list improvements from Mika&Arun - display pll precomputation from Ander Conselvan, this removed the last ->mode_set callbacks, a big step towards implementing atomic modesets - more kerneldoc for the interrupt code - 180 rotation for cursors (Ville&Sonika) - ULT/ULX feature check macros cleaned up thanks to Damien - piles and piles of fixes all over, bug team seems to work! * tag 'drm-intel-next-2014-10-24' of git://anongit.freedesktop.org/drm-intel: (61 commits) drm/i915: Update DRIVER_DATE to 20141024 drm/i915: add comments on what stage a given PM handler is called drm/i915: unify switcheroo and legacy suspend/resume handlers drm/i915: add poweroff_late handler drm/i915: sanitize suspend/resume helper function names drm/i915: unify S3 and S4 suspend/resume handlers drm/i915: disable/re-enable PCI device around S4 freeze/thaw drm/i915: enable output polling during S4 thaw drm/i915: check for GT faults in all resume handlers and driver load time drm/i915: remove unused restore_gtt_mappings optimization during suspend drm/i915: fix S4 suspend while switcheroo state is off drm/i915: vlv: fix switcheroo/legacy suspend/resume drm/i915: propagate error from legacy resume handler drm/i915: unify legacy S3 suspend and S4 freeze handlers drm/i915: factor out i915_drm_suspend_late drm/i915: Emit even number of dwords when emitting LRIs drm/i915: Add rotation support for cursor plane (v5) drm/i915: Correctly reject invalid flags for wait_ioctl drm/i915: use macros to assign mmio access functions drm/i915: only run hsw_power_well_post_enable when really needed ...
| * drm/i915: Update DRIVER_DATE to 20141024Daniel Vetter2014-10-241-1/+1
| | | | | | | | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: add comments on what stage a given PM handler is calledImre Deak2014-10-241-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will hopefully make it easier to navigate the code without the need to consult the full PM documentation. v2: - add a comment that the freeze handler is also called after rebooting - add a comment that the thaw handler is also called to recover from errors (Ville) - add the PM event names (PMSG_THAW etc.) for reference (Ville) - add comments that s0ix can be handled both via system and runtime suspend (Ville) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: unify switcheroo and legacy suspend/resume handlersImre Deak2014-10-243-12/+7
| | | | | | | | | | | | | | | | | | | | | | By now we handle switcheroo and legacy suspend/resume the same way, so no need to keep separate functions for them. No functional change. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: add poweroff_late handlerImre Deak2014-10-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | The suspend_late handler saves some registers and powers off the device, so it doesn't have a big overhead. Calling it at S4 poweroff_late time makes the power off handling identical to the S3 suspend and S4 freeze handling, so do this for consistency. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: sanitize suspend/resume helper function namesImre Deak2014-10-241-12/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | By now the S4 freeze/thaw and S3 suspend/resume events are handled the same way, so we can rename the freeze/thaw internal helpers to suspend/resume accordingly to make clearer what the helpers do. Also rename i915_resume_early to i915_drm_resume_early aligning it with the rest of the helper names. No functional change. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: unify S3 and S4 suspend/resume handlersImre Deak2014-10-241-87/+17
| | | | | | | | | | | | | | | | | | | | | | | | The S3 and S4 events are now handled the same way internally, there is no need to keep separate wrapper functions around them. Simply reuse the suspend/resume versions everywhere. No functional change. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: disable/re-enable PCI device around S4 freeze/thawImre Deak2014-10-241-3/+2
| | | | | | | | | | | | | | | | | | | | | | We already disable everything during S4 freeze, except the PCI device itself. There is no reason why we couldn't disable that too and doing so allows us to unify these handlers in the next patch with the corresponding S3 suspend/resume handlers. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: enable output polling during S4 thawImre Deak2014-10-241-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To avoid processing hotplug events we disable connector polling for the duration of S3 suspend. We also disable it for S4 freeze, and keep it disabled after S4 thaw. This won't prevent though hotplug processing, since we re-enable interrupts anyway. There is also no need to prevent it at that time, since we reinitialize everything during thaw, so the device is in a consistent state. So to simplify things enable polling during thaw, which will allow us to handle S4 thaw the same way as S3 resume in an upcoming patch. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: check for GT faults in all resume handlers and driver load timeImre Deak2014-10-242-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Checking for GT faults is not specific in any way to S4 thaw, so do it also during S3 resume, S4 restore and driver load time. This allows us to unify the Sx handlers in an upcoming patch. v2: - move the check to intel_uncore_early_sanitize(), so we check at driver load time too (Chris) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: remove unused restore_gtt_mappings optimization during suspendImre Deak2014-10-241-11/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The logic to skip restoring GTT mappings was added to speed up suspend/resume, but not on old GENs where not restoring them caused problems. The check for old GENs is based on the existence of OpRegion, but this doesn't work since opregion is initialized only after the check. So we end up always restoring the mappings. On my BYT - which has OpRegion - skipping restoring the mappings during suspend doesn't work, I get a GPU hang after resume. Also the logic of when to allow the optimization during S4 is reversed: we should allow it during S4 thaw but not during S4 restore, but atm we have it the other way around in the code. Since correctness wins over optimal code and since the optimization wasn't used anyway I decided not to try to fix it at this point, but just remove it. This allows us to unify the S3 and S4 handlers in the following patches. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: fix S4 suspend while switcheroo state is offImre Deak2014-10-241-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the device is suspended already through the switcheroo interface we shouldn't suspend it again or resume it after suspend. We have the corresponding check for S3 suspend already, add it for all the other S3 and S4 handlers. Also move the check from i915_resume_early() to i915_resume_legacy(), so that it's done in the high level handler for all PM events. v2: - fix the resume path too, we don't need to special case there DRM_SWITCH_POWER_OFF with the device being enabled (in which case we'd have to disable the device), since that never happens (Ville) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: vlv: fix switcheroo/legacy suspend/resumeImre Deak2014-10-241-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During switcheroo/legacy suspend we don't call the suspend_late handler but when resuming afterwards we call resume_early. This happened to work so far, since suspend_late only disabled the PCI device. This changed in commit 016970beb05da6285c2f3ed2bee1c676cb75972e Author: Sagar Kamble <sagar.a.kamble@intel.com> Date: Wed Aug 13 23:07:06 2014 +0530 drm/i915: Sharing platform specific sequence between runtime and system susp after which we also saved/restored the VLV Gunit HW state in suspend_late/resume_early. So now since we don't save the state during suspend a following resume will restore a corrupted state. Fix this by calling the suspend_late handler during both switcheroo and legacy suspend. CC: Sagar Kamble <sagar.a.kamble@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Sagar Kamble <sagar.a.kamble@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: propagate error from legacy resume handlerImre Deak2014-10-241-3/+6
| | | | | | | | | | | | Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: unify legacy S3 suspend and S4 freeze handlersImre Deak2014-10-241-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i915_suspend() is called from the DRM legacy S3 suspend/S4 freeze paths and the switcheroo suspend path. For switcheroo we only ever need to perform a full suspend (PM_EVENT_SUSPEND) and for the DRM legacy path we can handle the S4 freeze (PM_EVENT_FREEZE) the same way as S3 suspend. The only difference atm between suspend and freeze is that during freeze we don't disable the PCI device, but there is no reason why we can't do so. So unify the two cases to reduce complexity. Note that for the DRM legacy case the thaw event is not handled, so we disable the display before creating the hibernation image and it won't get re-enabled until reboot. We could fix this leaving the display enabled for the image creation/writing (if we care enough about UMS), but this can be done as a follow-up. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: factor out i915_drm_suspend_lateImre Deak2014-10-241-12/+20
| | | | | | | | | | | | | | | | | | | | | | This is needed by an upcoming patch fixing the switcheroo/legacy suspend paths. No functional change. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Emit even number of dwords when emitting LRIsArun Siluvery2014-10-241-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The number of DWords should be even when doing ring emits as command sequences require QWord alignment. There was some discussion about the maximum length of the MI_LRI command. Quoting Mika "I did some test with bdw: "The maximum is 128 writes, resulting the 8 bit length field of the command being 0xff, thus following the spec. The 128'th write went through. "Perhaps the max command length is then less in older gens? "Perhaps WARN_ON(x > 128) in MI_LOAD_REGISTER_IMM would be in place but one needs minor tweak to command parser a bit also then. #define I915_MAX_WA_REGS 16 keeps us safe for now atleast." Ville commented that on pre-gen6 the length field seems to be restricted to 0x3f though. So for all cases we should be ok. v2: user LRI variant that can write multiple regs in one go (Damien). We can simply insert one NOP at the end instead of one per register write. Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> [danvet: Add a summary of the MI_LRI length discussion.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Add rotation support for cursor plane (v5)Ville Syrjälä2014-10-242-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cursor plane also supports 180 degree rotation. Add a new "cursor-rotation" property on the crtc which controls this. Unlike sprites, the cursor has a fixed size, so if you have a small cursor image with the rest of the bo filled by transparent pixels, simply flipping the rotation property will cause the visible part of the cursor to shift. This is something to keep in mind when using cursor rotation. v2: Fix gen4/vlv by offsetting the base address appropriately v3: Removing cursor-rotation property and using rotation property on cursor plane. v4: Changing the author name back to Ville. v5 (by Matt Roper): Slight tweaking to apply against latest di-nightly codebase. Cc: Sagar Kamble <sagar.a.kamble@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Tested-by (IVB): Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Correctly reject invalid flags for wait_ioctlDaniel Vetter2014-10-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Not having checks for this isn't good. I've checked igt and libdrm and they all already clear flags properly. So we're lucky and should be able to sneak this ABI clarification in. Testcase: igt/gem_wait/invalid-flags Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85280 Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: use macros to assign mmio access functionsYu Zhang2014-10-241-48/+30
| | | | | | | | | | | | | | | | | | | | | | This is beautification prep work since vgt will add even more special cases. With these macros it's much easier to see what's going on really. Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com> [danvet: #undef the temporary macros after the function again. And write a commit message.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: only run hsw_power_well_post_enable when really neededPaulo Zanoni2014-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Only run it after we actually enable the power well. When we're booting the machine there are cases where we run hsw_power_well_post_enable without really needing, and even though this is not causing any real bugs, it is unneeded and causes confusion to people debugging interrupts. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915/chv: Use 16 and 32 for low and high drain latency precision.Rodrigo Vivi2014-10-242-21/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current chv spec teels we can only use either 16 or 32 bits as precision. Although in the past VLV went from 16/32 to 32/64 and spec might not be updated, these precision values brings stability and fixes some issues Wayne was facing. Cc: Wayne Boyer <wayne.boyer@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Tested-by: Wayne Boyer <wayne.boyer@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Sprinkle const as requested by Ville.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Fold in intel_mst_port_dp_detectDaniel Vetter2014-10-241-9/+1
| | | | | | | | | | | | | | | | | | The indirection here seems to serve no purpose. Probably leftovers from earlier revisions. Spotted while trying to review some mst patches. Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
| * drm/i915: add runtime PM get/put call in i915_execlistsMichel Thierry2014-10-241-0/+3
| | | | | | | | | | | | | | | | | | Otherwise we will get WARNs when we read context status registers and the machine is suspended. Testcase: igt/pm_rpm/debugfs-read Signed-off-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Fix chv PCS DW11 register definesVille Syrjälä2014-10-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I managed to fumble the per spline PCS DW11 register defines in: commit 570e2a747bc06cd8620662c5125ec2dc964c511b Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Mon Aug 18 14:42:46 2014 +0300 drm/i915: Clear TX FIFO reset master override bits on chv Fortunately the bit in DW0 that was cleared due to this didn't have any effect as long as the bit we meant to clear was already zero. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> [danvet: Fix commit ref as pointed out by Jani.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Don't claim that we're resetting PCH ADPA registerVille Syrjälä2014-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | intel_crt_reset() resets the ADPA register on all gen5+ platforms. However the debug message claims it's touching the PCH ADPA register which is clearly not what it does on VLV. Drop the PCH part from the debug message. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: disable IPS while getting the pipe CRCs.Paulo Zanoni2014-10-241-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some yet-undiscovered reason, when IPS gets enabled, the pipe CRC changes. Since hsw_enable_ips() doesn't really guarantees to enable IPS (it depends on package C-states), we can't really predict if IPS is enabled or disabled while running our CRC tests, so let's just completely disable IPS while pipe CRCs are being used. If we find a way to make IPS not change the pipe CRC result, we may want to fix IPS and then revert this patch. While this doesn't happen, let's merge this patch, so every IGT test relying on the CRCs can work on pipe A. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72864 Testcase: igt/kms_cursor_crc (and others) Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: call drm_vblank_cleanup() earlier at unloadPaulo Zanoni2014-10-241-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In its current place, it just segfaults while trying to access the CRTC structures: [ 9132.421681] Call Trace: [ 9132.421707] [<ffffffffa01130d8>] i915_get_crtc_scanoutpos+0x1e8/0x220 [i915] [ 9132.421727] [<ffffffffa001da34>] drm_calc_vbltimestamp_from_scanoutpos+0x94/0x330 [drm] [ 9132.421744] [<ffffffffa001d240>] ?vblank_disable_and_save+0x40/0x1e0 [drm] [ 9132.421769] [<ffffffffa0114328>] i915_get_vblank_timestamp+0x68/0xb0 [i915] [ 9132.421786] [<ffffffffa001d094>] drm_get_last_vbltimestamp+0x44/0x80 [drm] [ 9132.421801] [<ffffffffa001d3a6>] vblank_disable_and_save+0x1a6/0x1e0 [drm] [ 9132.421817] [<ffffffffa001eac1>] drm_vblank_cleanup+0x61/0xa0 [drm] [ 9132.421849] [<ffffffffa0177a5e>] i915_driver_unload+0xde/0x290 [i915] [ 9132.421867] [<ffffffffa0020264>] drm_dev_unregister+0x24/0xb0 [drm] [ 9132.421884] [<ffffffffa002090e>] drm_put_dev+0x1e/0x70 [drm] [ 9132.421901] [<ffffffffa00e01e0>] i915_pci_remove+0x10/0x20 [i915] [ 9132.421910] [<ffffffff81347556>] pci_device_remove+0x36/0xb0 [ 9132.421920] [<ffffffff8140084a>] __device_release_driver+0x7a/0xf0 [ 9132.421928] [<ffffffff81400fc8>] driver_detach+0xb8/0xc0 [ 9132.421936] [<ffffffff8140054a>] bus_remove_driver+0x4a/0xb0 [ 9132.421944] [<ffffffff81401717>] driver_unregister+0x27/0x50 [ 9132.421953] [<ffffffff81346f65>] pci_unregister_driver+0x25/0x70 [ 9132.421971] [<ffffffffa00229c8>] drm_pci_exit+0x78/0xa0 [drm] [ 9132.422000] [<ffffffffa017a6d2>] i915_exit+0x20/0x94e [i915] [ 9132.422009] [<ffffffff810fb9dc>] SyS_delete_module+0x13c/0x1f0 [ 9132.422019] [<ffffffff8131c5fb>] ? trace_hardirqs_on_thunk+0x3a/0x3f [ 9132.422028] [<ffffffff816f7792>] system_call_fastpath+0x16/0x1b This means it has to be before intel_modeset_cleanup, which cleans the CRTC structures. But if we move it to before intel_fbdev_fini(), we get WARNs because intel_fbdev_fini() still tries to use the vblanks, so the only acceptable point for drm_vblank_cleanup() seems to be this place. Related commit: commit cbb47d179fb345c579cd8cd884693903fceed26a Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Mon Sep 23 17:33:20 2013 -0300 drm/i915: Add some missing steps to i915_driver_load error path Testsuite: igt/drv_module_reload Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77511 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83484 Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: spt does not have pch backlight override bitJani Nikula2014-10-241-2/+3
| | | | | | | | | | | | | | | | | | | | | | SPT is always in the PCH override mode, and the bit MBZ. Only set override on LPT. v2: check for PCH version (Ville) Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: preserve swizzle settings if necessary v4Jesse Barnes2014-10-243-15/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some machines (like MBAs) might use a tiled framebuffer but not enable display swizzling at boot time. We want to preserve that configuration if possible to prevent a boot time mode set. On IVB+ it shouldn't affect performance anyway since the memory controller does internal swizzling anyway. For most other configs we'll be able to enable swizzling at boot time, since the initial framebuffer won't be tiled, thus we won't see any corruption when we enable it. v2: preserve swizzling if BIOS had it set (Daniel) v3: preserve swizzling only if we inherited a tiled framebuffer (Daniel) check display swizzle setting in detect_bit_6_swizzle (Daniel) use gen6 as cutoff point (Daniel) v4: fixup swizzle preserve again, had wrong init order (Daniel) Reported-by: Kristian Høgsberg <hoegsberg@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: vlv: fix gunit HW state corruption during S4 suspendImre Deak2014-10-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During S4 freeze we don't call intel_suspend_complete(), which would save the gunit HW state, but during S4 thaw/restore events we call intel_resume_prepare() which restores it, thus ending up in a corrupted HW state. Fix this by calling intel_suspend_complete() from the corresponding freeze_late event handler. The issue was introduced in commit 016970beb05da6285c2f3ed2bee1c676cb75972e Author: Sagar Kamble <sagar.a.kamble@intel.com> Date: Wed Aug 13 23:07:06 2014 +0530 CC: Sagar Kamble <sagar.a.kamble@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Check workaround status on dfs read timeMika Kuoppala2014-10-241-7/+7
| | | | | | | | | | | | | | | | | | | | As the workaround list has the value as initialization time constant, we can do the simple checking on the go without negleting igt. Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Build workaround list in ring initializationMika Kuoppala2014-10-243-102/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we build the workaround list in ring initialization and decouple it from the actual writing of values, we gain the ability to decide where and how we want to apply the values. The advantage of this will become more clear when we need to initialize workarounds on older gens where it is not possible to write all the registers through ring LRIs. v2: rebase on newest bdw workarounds Cc: Arun Siluvery <arun.siluvery@linux.intel.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com> [danvet: Resolve tiny conflict in comments and ocd alignments a bit.] [danvet2: Remove bogus force_wake_get call spotted by Paulo and QA.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: remove redundant #ifdef CONFIG_COMPATJani Nikula2014-10-241-2/+0
| | | | | | | | | | | | | | The whole file is only built with CONFIG_COMPAT=y. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: remove dead code from legacy suspend handlerImre Deak2014-10-241-3/+3
| | | | | | | | | | | | | | | | | | | | The legacy DRM suspend logic (effective in UMS) doesn't handle any S4 thaw events so we don't need to care about it either. Only S3 suspend and S4 freeze events are handled. Leave an assert behind to be sure. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Make intel_pipe_has_type() and some callers take intel_crtcAnder Conselvan de Oliveira2014-10-241-52/+54
| | | | | | | | | | | | | | For consistency, since that's the rule followed for internal functions. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Make *_crtc_mode_set() take an intel_crtc insted of drm_crtcAnder Conselvan de Oliveira2014-10-242-51/+46
| | | | | | | | | | | | | | For consistency, since that's the rule followed for internal functions. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Make *_find_best_dpll() take an intel_crtc insted of drm_crtcAnder Conselvan de Oliveira2014-10-242-19/+20
| | | | | | | | | | | | | | For consistency, since that's the rule followed for internal functions. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Replace some loop through encoders with intel_pipe_has_type()Ander Conselvan de Oliveira2014-10-241-19/+2
| | | | | | | | | | | | | | | | | | In the ironlake mode set code, there was two instances of a loop through encoders to find out if one of them has INTEL_OUTPUT_LVDS type. Simplify the code by deleting some lines and use intel_pipe_has_type() instead. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Document that mmap forwarding is discouragedDaniel Vetter2014-10-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Too many new drm driver writers seem to look at i915 for inspiration. But we have two ways to do mmap, so discourage readers from the old, ugly version. In a new driver we'd just expose two mmap offsets per object, one for the gtt map and the other for the cpu map. v2: Make it clear that i915 does cpu mmaps this way for past cluelessness^W^W historical reasons. Asked for by Jani. Cc: "Cheng, Yao" <yao.cheng@intel.com> Cc: David Herrmann <dh.herrmann@gmail.com> Reviewed-by: David Herrmann <dh.herrmann@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915/bdw: Remove BDW preproduction W/As until C stepping.Rodrigo Vivi2014-10-242-13/+2
| | | | | | | | | | | | | | | | | | | | | | Let's clean this a bit v2: Rebase after other Mika's patch that removed some BDW production workarounds. v3: Removed stepping info. Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Convert a couple more INTEL_INFO-esque macros to be pointer agnosticChris Wilson2014-10-241-2/+2
| | | | | | | | | | | | | | | | | | | | Just a couple more macros that assume that they were being passed a struct drm_device when they want a struct drm_i915_private. Use our magic macro to ease transitioning over to using drm_i915_privates Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915/skl: Add 180 degree HW rotation supportSonika Jindal2014-10-243-0/+8
| | | | | | | | | | | | | | | | Add support for 180 degree rotation for primary and sprite planes Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Suppress no action noise from oom shrinkerChris Wilson2014-10-241-2/+3
| | | | | | | | | | | | | | | | | | | | | | If we are not able to free anything (the shrinker leaves nothing on the global object lists), do not log anything. This is useful when other subsystems are being stress-tested for their oom behaviour and i915.ko is shouting into the logs about doing nothing. Reported-by: Dave Jones <davej@redhat.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Report the current number of bytes freed during oomChris Wilson2014-10-241-4/+4
| | | | | | | | | | | | | | | | | | | | The shrinker reports the number of pages freed, but we try to log the number of bytes - which leads to some nonsense values being reportedly freed during oom. Reported-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Add missing '\n' to cdclk debug messageVille Syrjälä2014-10-241-1/+1
| | | | | | | | | | Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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