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* drm/amdgpu: fix PRT teardown on VM fini v3Christian König2017-03-292-26/+82
| | | | | | | | | | v2: new approach fixing this by registering a fence callback for all users of the VM on teardown v3: agd: rebase Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add OOM fallback on PRT teardown (v2)Christian König2017-03-291-6/+22
| | | | | | | | | | Don't assume kmalloc will always succeed. v2: agd: rebase Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: minor PRT turnoff fix (v2)Christian König2017-03-291-7/+5
| | | | | | | | | | | When two VMs stop using PRT support at the same time we might not disable it in the right order otherwise. v2: agd: rebase Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: change pte definitions to 64 bitAlex Xie2017-03-291-1/+1
| | | | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: fix PTE definesChristian König2017-03-291-7/+7
| | | | | | | | | Those should be 64bit, even on a 32bit system. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/amdgpu: Update read_sensor calls to have size parameter (v3)Tom St Denis2017-03-298-27/+64
| | | | | | | | | | | | | | | | This update allows sensors to return more than 1 value and indicates to the caller how many bytes are written. The debugfs interface has been updated to handle reading all of the values. Simply seek to the enum value (multiplied by 4) and then read as many bytes as the sensor provides. (v2): Don't set size to 4 before reading GPU_POWER (v3): agd: rebase Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: implement PRT for GFX8 v2Christian König2017-03-291-0/+57
| | | | | | | | | | | | Enable/disable the handling globally for now and print a warning when we enable it for the first time. v2: set correct register Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: implement PRT for GFX7 v2Christian König2017-03-291-0/+57
| | | | | | | | | | | | Enable/disable the handling globally for now and print a warning when we enable it for the first time. v2: set correct register Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: implement PRT for GFX6 v2Christian König2017-03-293-0/+60
| | | | | | | | | | | | Enable/disable the handling globally for now and print a warning when we enable it for the first time. v2: write to the correct register, adjust bits to that hw generation v3: fix compilation, add the missing register bit definitions Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: IOCTL interface for PRT support v4Junwei Zhang2017-03-294-27/+62
| | | | | | | | | | | | | | | | | | Till GFX8 we can only enable PRT support globally, but with the next hardware generation we can do this on a per page basis. Keep the interface consistent by adding PRT mappings and enable support globally on current hardware when the first mapping is made. v2: disable PRT support delayed and on all error paths v3: PRT and other permissions are mutal exclusive, PRT mappings don't need a BO. v4: update PRT mappings durign CS as well, make va_flags 64bit Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add basic PRT support (v2)Christian König2017-03-293-11/+98
| | | | | | | | | | | | | | Future hardware generations can handle PRT flags on a per page basis, but current hardware can only turn it on globally. Add the basic handling for both, a global callback to enable/disable triggered by setting a per mapping flag. v2: agd: rebase fixes Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add support for BO_VAs without BO v2Christian König2017-03-291-6/+14
| | | | | | | | | | For PRT support we need mappings which aren't backed by any memory. v2: fix parameter checking Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:use hw_init for sriov_gpu_resetMonk Liu2017-03-291-6/+6
| | | | | | | | | no suspend invoked so after VF FLR by host, we just call hw_init to reinitialize IPs. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: implement gpu power display for smu7_hwmgrEric Huang2017-03-291-0/+33
| | | | | | Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add power consumption display support in debugfsEric Huang2017-03-292-0/+19
| | | | | | | | | | | | The additional output are: vddc power in Watt; vddci power in Watt; max gpu power in Watt; average gpu power in Watt. Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: change parameter type pointer from int32_t to void in ↵Eric Huang2017-03-296-36/+36
| | | | | | | | | | read sensor As well as fix print format for uint32_t type. Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/amdgpu: add power profile support for CIEric Huang2017-03-292-0/+259
| | | | | | | Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add power profile support for PolarisEric Huang2017-03-293-0/+67
| | | | | | | Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add power profile support for FijiEric Huang2017-03-293-1/+68
| | | | | | | Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add power profile support for tongaEric Huang2017-03-293-0/+66
| | | | | | | Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add power profile support for SMU7Eric Huang2017-03-293-0/+86
| | | | | | | Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: reapply power profile when force dpm level to autoEric Huang2017-03-291-3/+19
| | | | | | | Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/amdgpu: add power profile sysfs entryEric Huang2017-03-296-1/+382
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the sysfs entries pp_gfx_power_profile and pp_compute_power_profile which give user a way to set power profile through parameters minimum sclk, minimum mclk, activity threshold, up hysteresis and down hysteresis only when the entry power_dpm_force_performance_level is in default value "auto". It is read and write. Example: echo 500 800 20 0 5 > /sys/class/drm/card0/device/pp_*_power_profile cat /sys/class/drm/card0/device/pp_*_power_profile 500 800 20 0 5 Note: first parameter is sclk in MHz, second is mclk in MHz, third is activity threshold in percentage, fourth is up hysteresis in ms and fifth is down hysteresis in ms. echo set > /sys/class/drm/card0/device/pp_*_power_profile To set power profile state if it exists. echo reset > /sys/class/drm/card0/device/pp_*_power_profile To restore default state and clear previous setting. Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:cleanup no needed bracesMonk Liu2017-03-291-6/+3
| | | | | | Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:don't return error for debugfs failedMonk Liu2017-03-291-1/+0
| | | | | | Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:add lock_reset for SRIOVMonk Liu2017-03-293-0/+4
| | | | | | | | | | | | | | | | | | this lock is used for sriov_gpu_reset, only get this mutex can run into sriov_gpu_reset. we have couple source triggers gpu_reset for SRIOV: 1) submit timedout and trigger reset voluntarily 2) invalid instruction detected by ENGINE and trigger reset voluntarily 2) hypervisor found world switch hang and trigger flr and notify guest to do reset. all need take care and we need a mutex to protect the consistency of reset routine. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:change kiq lock nameMonk Liu2017-03-292-6/+6
| | | | | | Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:implement SRIOV gpu_reset (v2)Monk Liu2017-03-292-1/+156
| | | | | | | | | | | | | | implement SRIOV gpu_reset for future use. it wil be called from: 1) job timeout 2) privl access or instruction error interrupt 3) hypervisor detect VF hang v2: agd: rebase on upstream Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:divide KCQ mqd init to sw and hwMonk Liu2017-03-291-65/+42
| | | | | | | | | | | | sw part only invoked once during sw_init. hw part invoked during first drv load and resume later. that way we cannot alloc mqd in hw/resume, we only keep mqd allocted in sw_init routine. and hw_init routine only kmap and set it. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:minor cleanupMonk Liu2017-03-291-4/+1
| | | | | Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:no need use sriov vf checksMonk Liu2017-03-291-9/+4
| | | | | | | | | | We ultimately want to re-use this for bare metal, so no need to have vf checks in the KIQ code itself since kiq itself is currently only used in VF cases. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:bo_free_kernel will set ptr to NULL if freedMonk Liu2017-03-291-1/+0
| | | | | | Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:imple mqd soft ini/finiMonk Liu2017-03-291-0/+52
| | | | | | | | | | | | | | | this is for SRIOV fix: mqd soft init/fini will be invoked by sw_init to allocate BO for compute MQD resource, instead of original scheme that hw_init allocates MQD. because if hw_init allocates MQD, then resume will allocate MQD, and that lead to memory leak after driver recovered from hang. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/damdgpu:add new mqd member in ringMonk Liu2017-03-292-0/+4
| | | | | | | | | | introduce a new mqd member in ring is for later usage. we need keep a clean version of MQD for the purpose of recovering compute rings from hang. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:cg & pg shouldn't active on VF deviceMonk Liu2017-03-294-0/+27
| | | | | | | | | | CG & PG function changes engine clock/gating, which is not appropriate for VF device, because one vf doesn't know the whole picture of engine's overall workload. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: clean framebuffer with GPUPixel Ding2017-03-291-3/+2
| | | | | | | | | | CPU is not efficient to clean framebuffer especially under virtualization, then loading driver takes long time which causes timeout of mailbox handshake. Signed-off-by: Pixel Ding <Pixel.Ding@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:fix amdgpu_sa_bo_new error(v2)Monk Liu2017-03-291-2/+2
| | | | | | | | | | | | | | | | ib_pool init should prior to fbdev_init, otherwise there will be error from amdgpu_sa_bo_new (amdgpu_sa.c:323) fbdev_init will call ttm_validate which further call amdgpu_sa_bo_new. v2: move fbdev_init behind ib test. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/virt: skip VM fault handler for VFPixel Ding2017-03-291-0/+7
| | | | | | | | | | | VF uses KIQ to access registers. When VM fault occurs, the driver can't get back the fence of KIQ submission and runs into CPU soft lockup. Signed-off-by: Pixel Ding <Pixel.Ding@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/virt: increase mailbox timeout to 5000msPixel Ding2017-03-291-1/+1
| | | | | | | | | | | When multiple VFs try to enter exclusive mode at the same time, the looping mechansim doesn't help to ensure each can get it because it only loops active VFs, then the last one has to wait for a long interval. Signed-off-by: Pixel Ding <Pixel.Ding@amd.com> Reviewed-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:fix powerplay logicMonk Liu2017-03-292-2/+2
| | | | | | | | | 1,like pp_hw_init, we shouldn't report error if PP disabled 2,disable pp_en if sriov Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:fix typoMonk Liu2017-03-291-2/+2
| | | | | | Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/i915/gvt: fix error return check for copy_gma_to_hva()Zhenyu Wang2017-03-291-4/+4
| | | | | | | | | | | | | | | | | From commit 73dec95e6ba3 ("drm/i915: Emit to ringbuffer directly"), copy_gma_to_hva() now returns copied data length instead of 0, so need to change error return check for that. Note: Looks this is caused by backmerge conflict resolving, so 4.11-rc4 is not impacted as commit 73dec95e6ba3 ("drm/i915: Emit to ringbuffer directly") is not in 4.11. But need to fix this before I can apply 4.12 stuff against drm-intel-next correctly. Fixes: e5c1ff14757a ("Backmerge tag 'v4.11-rc4' into drm-next") Cc: Dave Airlie <airlied@redhat.com> Cc: Tina Zhang <tina.zhang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* Backmerge tag 'v4.11-rc4' into drm-nextDave Airlie2017-03-2834-260/+423
|\ | | | | | | | | | | Linux 4.11-rc4 The i915 GVT team need the rc4 code to base some more code on.
| * Merge branch 'drm-fixes-4.11' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2017-03-244-8/+17
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-fixes A few small fixes for 4.11 * 'drm-fixes-4.11' of git://people.freedesktop.org/~agd5f/linux: drm/amd/amdgpu: add POLARIS12 PCI ID drm/amdgpu: fix the clearing wb size drm/amdgpu: reinstate oland workaround for sclk drm/radeon: reinstate oland workaround for sclk
| | * drm/amd/amdgpu: add POLARIS12 PCI IDEvan Quan2017-03-171-0/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| | * drm/amdgpu: fix the clearing wb sizeHuang Rui2017-03-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The clearing wb size should be the one that it is assigned. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: reinstate oland workaround for sclkAlex Deucher2017-03-161-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Higher sclks seem to be unstable on some boards. bug: https://bugs.freedesktop.org/show_bug.cgi?id=100222 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| | * drm/radeon: reinstate oland workaround for sclkAlex Deucher2017-03-161-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Higher sclks seem to be unstable on some boards. bug: https://bugs.freedesktop.org/show_bug.cgi?id=100222 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| * | Merge tag 'drm-misc-fixes-2017-03-23' of ↵Dave Airlie2017-03-241-3/+3
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/git/drm-misc into drm-fixes One fbdev regression fix from Michel * tag 'drm-misc-fixes-2017-03-23' of git://anongit.freedesktop.org/git/drm-misc: drm/fb-helper: Allow var->x/yres(_virtual) < fb->width/height again
| | * | drm/fb-helper: Allow var->x/yres(_virtual) < fb->width/height againMichel Dänzer2017-03-231-3/+3
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise this can also prevent modesets e.g. for switching VTs, when multiple monitors with different native resolutions are connected. The depths must match though, so keep the != test for that. Also update the DRM_DEBUG output to be slightly more accurate, this doesn't only affect requests from userspace. Bugzilla: https://bugs.freedesktop.org/99841 Fixes: 865afb11949e ("drm/fb-helper: reject any changes to the fbdev") Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Daniel Stone <daniels@collabora.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20170323085326.20185-1-michel@daenzer.net
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