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path: root/drivers/gpu/drm/nouveau/nv50_calc.c
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* drm/nouveau/clock: pull in the implementation from all over the placeBen Skeggs2012-10-031-97/+0
| | | | | | | Still missing the main bits we use to change performance levels, I'll get to it after all the hard yakka has been finished. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nva3/clk: better pll calculation when no fractional fb div availableBen Skeggs2011-05-161-31/+37
| | | | | | | | | | | | The core/mem/shader clocks don't support the fractional feedback divider, causing our calculated clocks to be off by quite a lot in some cases. To solve this we will switch to a search-based algorithm when fN is NULL. For my NVA8 at PL3, this actually generates identical cooefficients to the binary driver. Hopefully that's a good sign, and that does not break VPLL calculation for someone.. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nva3: fix overflow in fixed point math used for pll calculationBen Skeggs2010-11-181-6/+10
| | | | | | And a slight tweak which gets us closer to VBIOS-calculated numbers. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: support fractional feedback divider on newer chipsBen Skeggs2010-05-191-0/+87
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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