summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_runtime_pm.c
Commit message (Expand)AuthorAgeFilesLines
* Merge tag 'drm-intel-next-2015-11-20-merged' of git://anongit.freedesktop.org...Dave Airlie2015-12-011-229/+277
|\
| * Merge tag 'v4.4-rc2' into drm-intel-next-queuedDaniel Vetter2015-11-231-0/+18
| |\
| * | drm/i915/gen9: Add boot parameter for disabling DC6Patrik Jakobsson2015-11-171-3/+11
| * | drm/i915/gen9: Turn DC handling into a power wellPatrik Jakobsson2015-11-171-29/+83
| * | drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5()Patrik Jakobsson2015-11-171-3/+0
| * | drm/i915: Remove distinction between DDI 2 vs 4 lanesPatrik Jakobsson2015-11-171-46/+25
| * | drm/i915: Remove DDI power domain exclusion SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINSVille Syrjälä2015-11-171-5/+1
| * | drm/i915: Introduce a gmbus power domainVille Syrjälä2015-11-171-30/+4
| * | drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6Patrik Jakobsson2015-11-171-18/+17
| * | drm/i915: fix handling of the disable_power_well module optionImre Deak2015-11-171-1/+15
| * | drm/i915/skl: remove redundant DDI/IRQ reinitialization during PW1 enablingImre Deak2015-11-171-5/+0
| * | drm/i915/skl: disable DC states before display core init/uninitImre Deak2015-11-171-0/+4
| * | drm/i915/gen9: simplify DC toggling codeImre Deak2015-11-171-36/+27
| * | drm/i915/skl: don't toggle PW1 and MISC power wells on-demandImre Deak2015-11-171-27/+9
| * | drm/i915/skl: init/uninit display core as part of the HW power domain stateImre Deak2015-11-171-2/+54
| * | drm/i915: rename intel_power_domains_resume to *_sync_hwImre Deak2015-11-171-2/+2
| * | drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequencesDamien Lespiau2015-11-171-0/+28
| * | drm/i915: fix lookup_power_well for power wells without any domainImre Deak2015-11-171-2/+4
| * | drm/i915: fix the power well ID for always on wellsImre Deak2015-11-171-0/+2
| * | drm/i915/skl: Removed assert for csr-fw-loading check during disabling dc6Animesh Manna2015-11-121-1/+0
| * | drm/i915/gen9: Remove csr.state, csr_lock and related code.Daniel Vetter2015-11-121-15/+2
| * | drm/i915/gen9: move assert_csr_loaded into intel_rpm.cDaniel Vetter2015-11-121-0/+8
| * | drm/i915: Kill intel_runtime_pm_disable()Ville Syrjälä2015-11-111-17/+0
| * | drm/i915/kbl: Introduce Kabylake platform defition.Rodrigo Vivi2015-10-281-1/+1
| * | drm/i915/skl: Making DC6 entry is the last call in suspend flow.Animesh Manna2015-10-191-12/+7
* | | drm/i915: fix potential dangling else problems in for_each_ macrosJani Nikula2015-11-251-2/+2
| |/ |/|
* | Merge tag 'drm-intel-next-fixes-2015-11-06' of git://anongit.freedesktop.org/...Dave Airlie2015-11-071-0/+18
|\ \
| * | drm/i915/skl: disable display side power well support for nowImre Deak2015-11-061-0/+18
| |/
* | Merge tag 'drm-intel-next-2015-10-10' of git://anongit.freedesktop.org/drm-in...Dave Airlie2015-10-201-7/+54
|\ \ | |/
| * drm/i915: Skip CHV PHY asserts until PHY has been fully resetVille Syrjälä2015-10-061-1/+45
| * drm/i915: fixup runtime PM handling v2Jesse Barnes2015-09-301-3/+0
| * drm/i915/skl: Block disable call for pw1 if dmc firmware is present.Animesh Manna2015-09-301-3/+9
* | Merge commit '06d1ee32a4d25356a710b49d5e95dbdd68bdf505' of git://git.kernel.o...Dave Airlie2015-10-161-1/+2
|\ \ | |/ |/|
| * drm/i915/skl: Don't call intel_prepare_ddi when encoder list isn't yet initia...Rodrigo Vivi2015-09-281-1/+2
* | drm/i915: make CSR firmware messages less verboseJesse Barnes2015-09-141-18/+18
* | Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter2015-09-021-0/+2
|\ \ | |/
| * drm/i915/skl: Adding DDI_E power well domainXiong Zhang2015-08-311-0/+2
* | drm/i915: Add CHV PHY LDO power sanity checksVille Syrjälä2015-09-011-17/+109
* | drm/i915: Add some CHV DPIO lane power state assertsVille Syrjälä2015-09-011-0/+54
* | drm/i915: Force CL2 off in CHV x1 PHYVille Syrjälä2015-08-261-0/+9
* | drm/i915: Enable DPIO SUS clock gating on CHVVille Syrjälä2015-08-261-1/+2
* | drm/i915: Trick CL2 into life on CHV when using pipe B with port BVille Syrjälä2015-08-261-0/+29
* | drm/i915: Implement PHY lane power gating for CHVVille Syrjälä2015-08-261-9/+114
* | drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enableVille Syrjälä2015-08-261-21/+24
* | drm/i915: Add locking around chv_phy_control_init()Ville Syrjälä2015-08-261-0/+2
|/
* drm/i915: Extract a intel_power_well_disable() functionDamien Lespiau2015-08-051-5/+10
* drm/i915: Extract a intel_power_well_enable() functionDamien Lespiau2015-08-051-5/+10
* drm/i915: Refactor VLV display power well init/deinitVille Syrjälä2015-07-131-29/+23
* drm/i915: Simplify CHV pipe A power well codeVille Syrjälä2015-07-131-27/+20
* drm/i915: Apply OCD to VLV/CHV DPLL definesVille Syrjälä2015-07-131-4/+4
OpenPOWER on IntegriCloud