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path: root/drivers/gpu/drm/i915/intel_ringbuffer.c
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* drm/i915: move flushing list processing to i915_retire_commandsDaniel Vetter2010-09-081-0/+4
| | | | | | | | | | | | | | | ... instead of threading flush_domains through the execbuf code to i915_add_request. With this change 2 small cleanups are possible (likewise the majority of the patch): - The flush_domains parameter of i915_add_request is always 0. Drop it and the corresponding logic. - Ditto for the seqno param of i915_gem_process_flushing_list. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Enable MI_FLUSH on SandybridgeZhenyu Wang2010-09-071-2/+6
| | | | | | | | | MI_FLUSH is being deprecated, but still available on Sandybridge. Make sure it's enabled as userspace still uses MI_FLUSH. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915 invalidate indirect state pointers at end of ring execZou Nan hai2010-08-091-0/+9
| | | | | | | | This is required by the spec, and without this some 3D programs will hang after resume from RC6 we enable that. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915/ringbuffer: Set ring->gem_buffer = NULL on init unwindChris Wilson2010-08-091-14/+17
| | | | | | | | | The cleanup path for early abort failed to nullify the gem_buffer. The likely consequence of this is zero, since a failure here should mean aborting the module load. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Use a common seqno for all rings.Chris Wilson2010-08-091-20/+26
| | | | | | | | This will be used by the eviction logic to maintain fairness between the rings. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Inline ringbuffer_emit()Chris Wilson2010-08-091-8/+0
| | | | | | | | As the function has been reduced to a store plus increment, the body is now smaller than the call so inline it. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Move ringbuffer accounting to begin/advance.Chris Wilson2010-08-091-2/+3
| | | | | | | | | | | | | As we check that the ringbuffer will not wrap upon emission, we do not need to check that incrementing the tail wrapped every time. However, we do upon advancing just in case the tail is now pointing at the very end of the ring. Likewise we can account for the space used during emission in begin() and avoid decrementing it for every emit. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Unroll wrapping of the ringbuffer.Chris Wilson2010-08-091-2/+4
| | | | | | | The tail is quadword aligned, so we can add two MI_NOOP as a time. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Account for space on the ring buffer consumed whilst wrapping.Chris Wilson2010-07-011-0/+1
| | | | | | | | If we fill the tail of the physical ring buffer with NOOP when wrapping, we need to account for the reduction in available space. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix incorrect intel_ring_begin size in BSD ringbuffer.Zou Nan hai2010-06-141-4/+5
| | | | | | | | | The ring_begin API was taking a number of bytes, while all of our other begin/end macros take number of dwords. Change the API over to dwords to prevent future bugs. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix PIPE_CONTROL command on SandybridgeZhenyu Wang2010-05-281-2/+14
| | | | | | | | | | | | | | | Sandybridge(Gen6) has new format for PIPE_CONTROL command, the flush and post-op control are in dword 1 now. This changes command length field for difference between Ironlake and Sandybridge. I tried to test this with noop request and issue PIPE_CONTROL command for each sequence and track notify interrupts, which seems work fine. Hopefully we don't need workaround like on Ironlake for Sandybridge. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: implement BSD ring buffer V2Zou Nan hai2010-05-261-0/+153
| | | | | | | | | | | The BSD (bit stream decoder) ring is used for accessing the BSD engine which decodes video bitstream for H.264 and VC1 on G45+. It is asynchronous with the render ring and has access to separate parts of the GPU from it, though the render cache is coherent between the two. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: introduce intel_ring_buffer structure (V2)Zou Nan hai2010-05-261-233/+349
| | | | | | | | | | | Introduces a more complete intel_ring_buffer structure with callbacks for setup and management of a particular ringbuffer, and converts the render ring buffer consumers to use it. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com> [anholt: Fixed up whitespace fail and rebased against prep patches] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Rename dev_priv->ring to dev_priv->render_ring.Eric Anholt2010-05-261-14/+14
| | | | | | With the advent of the BSD ring, be clear about which ring this is. The docs are pretty consistent with calling this the Render engine at this point.
* drm/i915: Move ringbuffer-related code to intel_ringbuffer.c.Eric Anholt2010-05-261-0/+568
This is preparation for supporting multiple ringbuffers on Ironlake. The non-copy-and-paste changes are: - de-staticing functions - I915_GEM_GPU_DOMAINS moving to i915_drv.h to be used by both files. - i915_gem_add_request had only half its implementation copy-and-pasted out of the middle of it.
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