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path: root/drivers/gpu/drm/i915/intel_ddi.c
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* drm/i915: fix intel_ddi_get_cdclk_freq for ULT machinesPaulo Zanoni2012-11-211-0/+2
* drm/i915: Enable DP audio for HaswellTakashi Iwai2012-11-211-0/+9
* drm/i915: fix Haswell FDI link disable pathPaulo Zanoni2012-11-111-0/+26
* drm/i915: fix Haswell FDI link training codePaulo Zanoni2012-11-111-49/+70
* drm/i915: set the correct number of FDI lanes on HaswellPaulo Zanoni2012-11-111-2/+3
* drm/i915: create the DDI encoderPaulo Zanoni2012-11-111-37/+106
* drm/i915: add intel_ddi_connector_get_hw_statePaulo Zanoni2012-11-111-0/+40
* drm/i915: add port field to intel_digital_portPaulo Zanoni2012-11-111-13/+10
* drm/i915: enable DDI eDPPaulo Zanoni2012-10-261-1/+1
* drm/i915: turn the eDP DDI panel on/offPaulo Zanoni2012-10-261-2/+16
* drm/i915: set/unset the DDI eDP backlightPaulo Zanoni2012-10-261-2/+13
* drm/i915: set the correct eDP aux channel clock divider on DDIPaulo Zanoni2012-10-261-1/+1
* drm/i915: select the correct pipe when using TRANSCODER_EDPPaulo Zanoni2012-10-261-0/+17
* drm/i915: convert PIPE_MSA_MISC to transcoderPaulo Zanoni2012-10-261-9/+9
* drm/i915: convert DDI_FUNC_CTL to transcoderPaulo Zanoni2012-10-261-37/+64
* drm/i915: convert PIPE_CLK_SEL to transcoderPaulo Zanoni2012-10-261-2/+8
* drm/i915: implement Haswell DP link train sequencePaulo Zanoni2012-10-181-2/+51
* drm/i915: add DP support to intel_ddi_disable_portPaulo Zanoni2012-10-181-1/+10
* drm/i915: add DP support to intel_ddi_mode_setPaulo Zanoni2012-10-181-17/+44
* drm/i915: add DP support to intel_enable_ddiPaulo Zanoni2012-10-181-9/+12
* drm/i915: add DP support to intel_ddi_get_hw_statePaulo Zanoni2012-10-181-4/+4
* drm/i915: add DP support to intel_ddi_get_encoder_portPaulo Zanoni2012-10-181-3/+9
* drm/i915: add DP support to intel_ddi_pll_mode_setPaulo Zanoni2012-10-171-1/+24
* drm/i915: add intel_ddi_set_pipe_settingsPaulo Zanoni2012-10-171-0/+34
* drm/i915: add DP support to intel_ddi_enable_pipe_funcPaulo Zanoni2012-10-171-4/+30
* drm/i915: Fix the SCC/SSC typo in the SPLL bits definitionDamien Lespiau2012-10-111-1/+1
* drm/i915: disable DDI_BUF_CTL at the correct timePaulo Zanoni2012-10-111-10/+23
* drm/i915: don't rely on previous values set on DDI_BUF_CTLPaulo Zanoni2012-10-101-5/+1
* drm/i915: completely rewrite the Haswell PLL handling codePaulo Zanoni2012-10-101-53/+210
* drm/i915: enable and disable PIPE_CLK_SEL at the right timePaulo Zanoni2012-10-101-4/+33
* drm/i915: enable and disable DDI_FUNC_CTL at the right timePaulo Zanoni2012-10-101-19/+64
* drm/i915: rewrite the LCPLL codePaulo Zanoni2012-10-101-6/+31
* drm/i915/hdmi: implement get_hw_stateDaniel Vetter2012-09-061-0/+29
* drm/i915/hdmi: convert to encoder->disable/enableDaniel Vetter2012-09-061-11/+19
* drm/i915: write eld info for HDMI audioWang Xingchao2012-08-171-1/+5
* drm/i915: try harder to find WR PLL clock settingsPaulo Zanoni2012-08-101-22/+17
* drm/i915: completely reset the value of DDI_FUNC_CTLPaulo Zanoni2012-08-091-6/+1
* drm/i915: correctly set the DDI_FUNC_CTL bpc fieldPaulo Zanoni2012-08-091-6/+20
* drm/i915: set the DDI sync polarity bitsPaulo Zanoni2012-08-091-0/+6
* drm/i915: fix pipe DDI mode selectPaulo Zanoni2012-08-091-1/+6
* drm/i915: add port parameter to intel_hdmi_initDaniel Vetter2012-07-251-1/+1
* drm/i915: program FDI_RX TP and FDI delaysEugeni Dodonov2012-07-051-0/+9
* drm/i915: add set_infoframes to struct intel_hdmiPaulo Zanoni2012-05-301-2/+1
* drm/i915: prepare HDMI link for HaswellEugeni Dodonov2012-05-191-0/+116
* drm/i915: add WR PLL programming tableEugeni Dodonov2012-05-191-0/+388
* drm/i915: detect digital outputs on HaswellEugeni Dodonov2012-05-191-0/+29
* drm/i915: support DDI training in FDI modeEugeni Dodonov2012-05-191-0/+115
* drm/i915: initialize DDI buffer translationsEugeni Dodonov2012-05-191-0/+107
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