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path: root/drivers/gpu/drm/i915/i915_reg.h
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* drm/i915: make the panel fitter work on pipes B and C on IVBPaulo Zanoni2012-11-211-0/+2
* drm/i915: don't intel_crt_init if DDI A has 4 lanesPaulo Zanoni2012-11-211-0/+1
* drm/i915: make DP work on LPT-LP machinesPaulo Zanoni2012-11-211-0/+1
* drm/i915: Move the remaining gtt codeBen Widawsky2012-11-111-17/+0
* drm/i915: flush system agent TLBs on SNBBen Widawsky2012-11-111-0/+2
* drm/i915: Calculate correct stolen size for GEN7+Ben Widawsky2012-11-111-0/+2
* drm/i915: Stop using AGP layer for GEN6+Ben Widawsky2012-11-111-0/+6
* drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3Jesse Barnes2012-11-111-2/+6
* drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLVJesse Barnes2012-11-111-0/+5
* drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLVJesse Barnes2012-11-111-0/+2
* drm/i915: implement WaDisableDopClockGatingisable on VLV and IVBJesse Barnes2012-11-111-0/+4
* drm/i915: implement WaDisableL3CacheAging on VLVJesse Barnes2012-11-111-0/+1
* drm/i915: fix Haswell FDI link training codePaulo Zanoni2012-11-111-6/+11
* drm/i915: implement WADP0ClockGatingDisableDaniel Vetter2012-11-111-0/+4
* drm/i915: CPT+ pch transcoder workaroundDaniel Vetter2012-11-111-2/+3
* drm/i915: Add SURFLIVE register definitionsVille Syrjälä2012-11-111-0/+7
* drm/i915: Fix display pixel format handlingVille Syrjälä2012-11-111-5/+12
* drm/i915: implement WaDisableRenderCachePipelinedFlushDaniel Vetter2012-11-111-0/+1
* drm/i915: Fix sprite offset on HSWDamien Lespiau2012-11-111-0/+3
* drm/i915: Fix primary plane offset on HSWDamien Lespiau2012-11-111-0/+3
* drm/i915: check fdi B/C lane sharing constraintDaniel Vetter2012-11-111-2/+3
* drm/i915: convert pipe timing definitions to transcoderPaulo Zanoni2012-10-261-7/+7
* drm/i915: convert CPU M/N timings to transcoderPaulo Zanoni2012-10-261-8/+8
* drm/i915: convert PIPE_MSA_MISC to transcoderPaulo Zanoni2012-10-261-9/+10
* drm/i915: convert PIPECONF to use transcoder instead of pipePaulo Zanoni2012-10-261-1/+1
* drm/i915: convert DDI_FUNC_CTL to transcoderPaulo Zanoni2012-10-261-27/+32
* drm/i915: convert PIPE_CLK_SEL to transcoderPaulo Zanoni2012-10-261-7/+7
* drm/i915: add TRANSCODER_EDPPaulo Zanoni2012-10-261-0/+1
* drm/i915: make edp panel power sequence setup more robustDaniel Vetter2012-10-231-0/+5
* Merge tag 'v3.7-rc2' into drm-intel-next-queuedDaniel Vetter2012-10-221-1/+8
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| * drm/i915: Set guardband clipping workaround bit in the right register.Kenneth Graunke2012-10-121-1/+1
| * drm/i915: Fix GT_MODE default valueBen Widawsky2012-10-041-0/+3
| * drm/i915: make sure we write all the DIP data bytesPaulo Zanoni2012-09-261-0/+4
* | drm/i915: Consolidate ILK_DSPCLK_GATE and PCH_DSPCLK_GATEDamien Lespiau2012-10-191-15/+7
* | drm/i915: add basic Haswell DP link train bitsPaulo Zanoni2012-10-171-0/+4
* | drm/i915: add intel_ddi_set_pipe_settingsPaulo Zanoni2012-10-171-0/+10
* | drm/i915: Document the multi-threaded FORCEWAKE bitsChris Wilson2012-10-171-0/+2
* | drm/i915: Allow DRM_ROOT_ONLY|DRM_MASTER to submit privileged batchbuffersChris Wilson2012-10-171-2/+5
* | drm/i915: Workaround to bump rc6 voltage to 450Ben Widawsky2012-10-161-0/+4
* | drm/i915: Fix the SCC/SSC typo in the SPLL bits definitionDamien Lespiau2012-10-111-3/+3
* | drm/i915: completely rewrite the Haswell PLL handling codePaulo Zanoni2012-10-101-0/+1
* | drm/i915: add haswell_set_pipeconfPaulo Zanoni2012-10-101-0/+1
* | drm/i915: enable and disable DDI_FUNC_CTL at the right timePaulo Zanoni2012-10-101-0/+1
* | drm/i915: rewrite the LCPLL codePaulo Zanoni2012-10-101-0/+6
* | drm/i915: implement WaDisableEarlyCull for VLV and IVBJesse Barnes2012-10-041-0/+1
* | drm/i915: implement WaForceL3Serialization on VLV and IVBJesse Barnes2012-10-041-0/+3
* | drm/i915: Fixup HDMI output on ValleyviewVijay Purushothaman2012-09-281-1/+1
* | drm/i915: Enable DisplayPort in ValleyviewVijay Purushothaman2012-09-281-6/+2
* | drm/i915: Add Valleyview lane control definitionsVijay Purushothaman2012-09-281-0/+8
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* Merge the modeset-rework, basic conversion into drm-intel-nextDaniel Vetter2012-09-061-0/+2
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