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path: root/drivers/gpu/drm/i915/i915_reg.h
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* drm/i915: Evict CS TLBs between batchesChris Wilson2014-09-081-4/+8
* drm/i915: Fix drain latency precision multipler for VLVZhenyu Wang2014-08-071-25/+25
* Merge tag 'v3.16' into drm-nextDave Airlie2014-08-051-0/+3
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| * drm/i915: Don't clobber the GTT when it's within stolen memoryVille Syrjälä2014-07-091-0/+3
* | Merge remote-tracking branch 'airlied/drm-next' into drm-intel-nextDaniel Vetter2014-07-291-2/+9
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| * | drm/i915: add some registers need for displayport MST support.Dave Airlie2014-07-211-2/+9
* | | drm/i915/chv: calculate rc6 residency correctlyMika Kuoppala2014-07-121-1/+1
* | | drm/i915: populate mem_freq/cz_clock for chvDeepak S2014-07-111-0/+6
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* | drm/i915: Switch to common shared dpll framework for WRPLLsDaniel Vetter2014-07-101-0/+1
* | drm/i915: State readout support for WRPLLsDaniel Vetter2014-07-101-0/+1
* | drm/i915: State readout and cross-checking for ddi_pll_selDaniel Vetter2014-07-101-0/+1
* | drm/i915: Clean up WRPLL/SPLL #definesDaniel Vetter2014-07-101-3/+4
* | drm/i915: fix D_COMP usage on BDWPaulo Zanoni2014-07-101-1/+4
* | drm/i915/vlv: WA for Turbo and RC6 to work together.Deepak S2014-07-081-0/+11
* | drm/i915/bdw: implement semaphore waitBen Widawsky2014-07-071-0/+3
* | drm/i915/bdw: implement semaphore signalBen Widawsky2014-07-071-1/+4
* | drm/i915: Give names to the CCK_DISPLAY_CLOCK_CONTROL bitsVille Syrjälä2014-07-071-0/+5
* | drm/i915: Add some L3 registers to the parser whitelistBrad Volkin2014-06-181-0/+2
* | drm/i915: update BDW DDI buffer translationsPaulo Zanoni2014-06-161-11/+0
* | drm/i915: BDW PSR: Add single frame update support.Rodrigo Vivi2014-06-131-0/+1
* | drm/i915: Fix VLV CRC reading.Rodrigo Vivi2014-06-131-1/+1
* | drm/i915: Add #defines for short/long pulse on gmch platformsDaniel Vetter2014-06-111-0/+6
* | drm/i915: Use transcoder as index to MIPI regsShashank Sharma2014-06-111-47/+93
* | drm/i915: Change Mipi register definitionsShashank Sharma2014-06-111-90/+93
* | drm/i915/chv: Handle video DIP registers on CHVVille Syrjälä2014-06-111-5/+12
* | drm/i915: Don't use pipe_offset stuff for DPLL registersVille Syrjälä2014-06-111-16/+10
* | drm/i915/chv: Force clock buffer enablesVille Syrjälä2014-06-111-0/+18
* | drm/i915/chv: Try to program the PHY used clock channel overridesVille Syrjälä2014-06-111-0/+7
* | drm/i915/chv: Enable RPS (Turbo) for CherryviewDeepak S2014-06-111-0/+11
* | drm/i915/chv: Enable Render Standby (RC6) for CherryviewDeepak S2014-06-111-0/+2
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* drm/i915: Enable interrupt-based AGPBUSY# enable on 85xVille Syrjälä2014-06-051-0/+4
* drm/i915: Flip the sense of AGPBUSY_DIS bitVille Syrjälä2014-06-051-1/+1
* drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elkVille Syrjälä2014-05-221-0/+4
* drm/i915: Add a brief description of the VLV display PHY internalsVille Syrjälä2014-05-221-4/+81
* drm/i915: Fix mmio vs. CS flip race on ILK+Ville Syrjälä2014-05-211-0/+1
* drm/i915: Drop /** */ comments from i915_reg.hVille Syrjälä2014-05-201-123/+123
* drm/i915/chv: Add a bunch of pre production workaroundsVille Syrjälä2014-05-201-0/+3
* drm/i915/chv: Use RMW to toggle swing calc initVille Syrjälä2014-05-201-0/+7
* drm/i915/chv: Don't do group access reads from TX lanes eitherVille Syrjälä2014-05-201-0/+11
* drm/i915/chv: Don't use PCS group access readsVille Syrjälä2014-05-201-0/+14
* drm/i915/chv: Set soft reset override bit for data lane resetsVille Syrjälä2014-05-201-0/+1
* drm/i915/chv: Register port D encoders and connectorsVille Syrjälä2014-05-201-0/+1
* drm/i915/chv: Fix PORT_TO_PIPE for CHVVille Syrjälä2014-05-201-0/+2
* drm/i915/chv: Add cursor pipe offsetsVille Syrjälä2014-05-201-12/+18
* drm/i915/chv: Fix gmbus for port DVille Syrjälä2014-05-201-0/+1
* drm/i915/chv: Add CHV display supportRafael Barbalho2014-05-201-3/+8
* drm/i915: Fix ILK GPU reset domain bitsVille Syrjälä2014-05-201-1/+7
* drm/i915: Add MIPI mmio reg baseShashank Sharma2014-05-191-0/+1
* drm/i915: rename IOSF sideband opcodes according to the specImre Deak2014-05-191-5/+0
* drm/i915: Enable PM Interrupts target via Display Interface.Deepak S2014-05-151-0/+1
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