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path: root/drivers/gpu/drm/amd
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* drm/amd/powerplay: add allowed feature mask for navi10Kevin Wang2019-06-211-2/+5
| | | | | | | | | | | add smu feature mask: 1.FEATURE_DPM_PREFETCHER_BIT 2.FEATURE_DPM_PREFETCHER_BIT 3.FEATURE_ATHUB_PG Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: optimization feature mask function for asicKevin Wang2019-06-214-17/+57
| | | | | | | | | | 1.change function return value type: from "unallowed" to "allowed" 2.replace feature mask number with feature macro, the code will clear. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: remove duplicate code from smu hw initKevin Wang2019-06-211-4/+0
| | | | | | | | remove duplicate code (un-used) in smu Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: implement smc firmware v2.1 for smu11Kevin Wang2019-06-214-30/+84
| | | | | | | | | | 1.add smc_firmware_header_v2_1 hfirmware support, support more pptable in smc firmware. 2.optimization current pptable load framework. 3.rename read_pptable_from_vbios with setup_pptable. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add smu11 smu_if_version check for navi10Kevin Wang2019-06-211-0/+1
| | | | | | | | add smu11 fw version check for navi10 Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: move the function of is_dpm_running to asic fileKevin Wang2019-06-213-24/+24
| | | | | | | | | the function os is_dpm_running is aisc related function, so move them to asic file. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: move the function of read_sensor to asic fileKevin Wang2019-06-213-8/+31
| | | | | | | | | The read_sensor functions has asic related parts code, so move them to asic file to implement. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: move the function of uvd&vce dpm to asic fileKevin Wang2019-06-213-28/+28
| | | | | | Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: move the function of get[set]_power_profile to asic fileKevin Wang2019-06-213-198/+199
| | | | | | | | | The callback of get[set]_power_profile is asic related function, so move theme into vega20_ppt file. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: move the funciton of conv_profile_to_workload to asic fileKevin Wang2019-06-213-35/+37
| | | | | | | | | the function of conv_profile_to_workload is asic related function, so move them into vega20_ppt file Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: enable power featuresKenneth Feng2019-06-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | the below smu related power features can be enabled now. 1.Prefetcher 2.GFX DPM 3.SOCCLK DPM 4.MP0CLK DPM 5.LCLK DPM 6.GFX ULV 7.CG 8.PPT 9.TDC 10.GFX EDC 11.VR0HOT 12.Fan Control 13.Thermal Control 14.LED Display 15.MMHub PG 16.ATHub PG Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: skip od feature on navi10 for the momentHuang Rui2019-06-211-0/+7
| | | | | | | | OD feature isn't enabled on navi10 so skip it for the moment. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: modify the feature mask to enable gfx/soc dpmHuang Rui2019-06-211-2/+2
| | | | | | | | So far, the gfx/soc dpm is enabled with feature mask set. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: introduce the function to load the soft pptable for ↵Huang Rui2019-06-212-6/+37
| | | | | | | | | | | | | navi10 (v2) Driver is able to load soft pptable from smc bin file with this function. We stored the soft pptable in the bottom of smc.bin that the version is v2. v2: remove is_fw_v2_0 flag. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: smu needs to be initialized after rlc in direct modeHuang Rui2019-06-211-9/+5
| | | | | | | | | | | For gfx 10, rlc firmware loading relies on smu firmware is loaded firstly, so in direct type, it has to load smc ucode here before rlc. And meanwhile, the smu initialization has to move after rlc, otherwise, smu message will get failure during the handshake with rlc and smu. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: fix the issue of checking on message mappingHuang Rui2019-06-211-2/+7
| | | | | | | | | The navi10_message_map[index] scope should be in PPSMC_Message_Count not in SMU_MSG_MAX_COUNT. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: bump smc firmware header version to v2 (v2)Huang Rui2019-06-212-0/+16
| | | | | | | | | | This patch bumps smc firmware header version to v2 for storing soft pptable. v2: fix the typo, and add prints for v2 header Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update smu11 driver if header for navi10 (v2)Huang Rui2019-06-211-1/+10
| | | | | | | | | | | This patch updates smu11 driver if header for navi10 to match 42.09.00 smu firmware. v2: clean up comments Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: enable backdoor smu fw loading (v2)Kenneth Feng2019-06-212-0/+34
| | | | | | | | | | enable backdoor smu fw loading on navi10 v2: squash in define fix (Alex) Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: move bootup value before read pptable from vbiosHuang Rui2019-06-211-3/+3
| | | | | | | | | In navi10, we need read the pp_table_id from bootup value, then decide whether use load the soft pptable. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add navi10 smc ucode init and navi10 ppt functions settingHuang Rui2019-06-211-0/+7
| | | | | | | | This patch adds navi10 smc ucode init and ppt functions setting. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: set smu v11 funcs for navi10Huang Rui2019-06-211-0/+1
| | | | | | | | Naiv10 also uses smu v11 functions. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: introduce the navi10 pptable implementationHuang Rui2019-06-213-1/+332
| | | | | | | | | | This patch introduces the navi10 pptable implementation, so far it is already has firmware loading, pptable side loading, writing back to smc, and feature mask enabling. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: fix the mp/smuio header for navi10Huang Rui2019-06-211-4/+4
| | | | | | | | SMU11 should use mp11 and smuio11 headers. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update smu 11 driver if header for navi10Huang Rui2019-06-212-1/+1040
| | | | | | | | | | This patch updates smu 11 driver if header for navi10. UVD/VCE won't be used for navi10. Here, reverve them for vega20. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update smu v11 ppsmc headerHuang Rui2019-06-211-18/+20
| | | | | | | | This patch updates smu v11 ppsmc header for navi10. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add to set navi ip blocksHuang Rui2019-06-211-0/+8
| | | | | | | | | Set the IPs for navi10 in early_init like other asics. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add Navi10 pci idsAlex Deucher2019-06-211-0/+6
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdkfd: Add navi10 support to amdkfd. (v3)Philip Cox2019-06-2118-12/+2442
| | | | | | | | | | | | | | | KFD (kernel fusion driver) is the kernel driver for the compute backend for usermode compute stack. v2: squash in updates (Alex) v3: squash in rebase fixes (Alex) Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Philip Cox <Philip.Cox@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: update golden setting programming logicHawking Zhang2019-06-212-2/+5
| | | | | | | | | Since from soc15, make sure only AndMasked bit get changed when applied or_mask Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add navi10 kfd support for amdgpu (v3)Hawking Zhang2019-06-214-4/+992
| | | | | | | | | | | | | | KFD (Kernel Fusion Driver) is the compute backend driver for AMD GPUs. v2: squash in updates (Alex) v3: fix warnings (Alex) Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Philip Cox <Philip.Cox@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add navi10 common ip block (v3)Hawking Zhang2019-06-214-1/+877
| | | | | | | | | | | | | | | This adds the core SOC code for navi asics. v1: add place holder and initial basic function (Ray) v2: add new introduced functions to avoid reference NULL pointer (Hawking) v3L squash in updates (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10Hawking Zhang2019-06-212-9/+8
| | | | | | | | Move to the header file. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add gfx v10 implementation (v10)Hawking Zhang2019-06-214-3/+5204
| | | | | | | | | | | | | | | | | | | | | GFX is the graphics and compute block on the GPU. v1: add initial gfx v10 implementation (Ray) v2: convert to new get_vm_pde function in emit_vm_flush (Hawking) v3: switch to new emit ib interfaces (Hawking) v4: squash in updates (Alex) v5: remove unused variables (Alex) v6: v6: some golden regs moved to vbios (Alex) v7: squash in some cleanups (Alex) v8: squash in golden settings update (Alex) v9: squash in whitespace fixes (Ernst Sjöstrand, Alex) v10: squash in GDS backup size fix and GDS/GWS/OA removal rebase fixes (Hawking) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/mes10.1: add ip block mes10.1 (v2)Jack Xiao2019-06-214-1/+138
| | | | | | | | | | | MES takes over the scheduling capability of GFX and SDMA, add MES as a standalone ip. v2: squash in updates (Alex) Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/mes: enable mes on navi10 and later asicJack Xiao2019-06-211-0/+3
| | | | | | | | | When amdgpu_mes is enabled and asic family is navi10 and later asic, enable mes per device. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/mes: add definitions of ip callback functionJack Xiao2019-06-211-0/+54
| | | | | | | | Abstract mes ip independent function layer. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/mes: add mes header file and definitionJack Xiao2019-06-212-0/+36
| | | | | | | | Add dummy header file and definitions of mes. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/mes: add amdgpu_mes driver parameterJack Xiao2019-06-212-0/+6
| | | | | | | | | | | | | amdgpu_mes, which is a driver scope parameter, is used to whether enable mes or not. MES (Micro Engine Scheduler) is the new on chip hw scheduling microcontroller. It can be used to handle queue scheduling and preemption and priorities. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add initial VCN2.0 support (v2)Leo Liu2019-06-214-1/+1897
| | | | | | | | | | | | | VCN (Video Core Next) is the video encode/decode block. Porting over the same functions from VCN1.0 v2: squash in updates (Alex) Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add JPEG2.0 decode ring ib testLeo Liu2019-06-211-2/+2
| | | | | | | | Add internal register offset for registers involving in ib tests Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add JPEG2.0 decode ring testLeo Liu2019-06-213-5/+6
| | | | | | | | Use register from JPEG tile, the UVD tile reg won't work for JPEG Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add VCN2.0 decode ib testLeo Liu2019-06-213-5/+17
| | | | | | | | Add internal register offset for registers involving in ib tests Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add VCN2.0 decode ring testLeo Liu2019-06-213-5/+11
| | | | | | | | Add internal register offset for registers involving in ring tests Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add Navi10 VCN firmware supportLeo Liu2019-06-211-0/+5
| | | | | | | | Add Navi10 to VCN family Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add initial support for sdma v5.0 (v6)Hawking Zhang2019-06-213-1/+1732
| | | | | | | | | | | | | | | | | | SDMA (System DMA) is a general purpose DMA engine usable by UMDs for transfers or the kernel for paging or GPUVM updates. v1: support basic funcitonalites includes rb, ib, vm, copy buffer and trap irq v2: convert to use new get_vm_pde in emit_vm_flush v3: retire amdgpu_ttm_set_active_vram_size from sdma v5 v4: retire the redundant hdp_invalidate implementation v5: squash in updates v6: some golden regs moved to vbios Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: set the default value of pa_sc_tile_steering_overrideHawking Zhang2019-06-211-0/+4
| | | | | | | | So userspace can access it. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: disable concurrent flushes for Navi10 v2Christian König2019-06-211-2/+5
| | | | | | | | | | | Navi10 have a bug in the SDMA which can theoretically cause memory corruption with concurrent VMID flushes v2: explicitely check Navi10 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/discovery: refactor ip list traversalXiaojie Yuan2019-06-211-29/+42
| | | | | | | | | | | | for each ip, check whether it is needed by amdgpu driver, if yes, record its base addresses v2: change some DRM_INFO to DRM_DEBUG v3: remove unused variable (Alex) Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/discovery: add module param for ip discovery enablementXiaojie Yuan2019-06-213-0/+16
| | | | | | | | to control enablement. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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