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* | drm/amd/display: update bw_calcs to take pipe sync into account (v3)Alex Deucher2019-08-231-2/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | Properly set all_displays_in_sync so that when the data is propagated to powerplay, it's set properly and we can enable mclk switching when all monitors are in sync. v2: fix logic, clean up v3: check for blending chains, simplify logic Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix calc_pll_max_vco_constructDmytro Laktyushkin2019-08-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | This was broken by a previous change switching to cached fw_info. Fixed by inverting a valid bool check. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111432 Fixes: 9adc8050bf3c ("drm/amd/display: make firmware info only load once during dc_bios create") Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix a potential null pointer dereferenceColin Ian King2019-08-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently the pointer init_data is dereferenced on the assignment of fw_info before init_data is sanity checked to see if it is null. Fix te potential null pointer dereference on init_data by only performing dereference after it is null checked. Addresses-Coverity: ("Dereference before null check") Fixes: 9adc8050bf3c ("drm/amd/display: make firmware info only load once during dc_bios create") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | Revert "drm/amd/display: Fix underscan not using proper scaling"David Francis2019-08-221-11/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 80e80ec817f161560b4159608fb41bd289abede3. This commit fixed an issue with underscan commits not updating all needed timing values, but through various refactors it is no longer necessary. It causes corruption on odm combine by overwriting the halved h_active in the stream timing Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | Revert "drm/amd/display: add global master update lock for DCN2"David Francis2019-08-224-71/+1
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6c5be4ac630805d3a3b20157a0c6421ef815fe78. This commit was accidentally promoted twice Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | Revert "drm/amd/display: navi10 bring up skip dsc encoder config"David Francis2019-08-221-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit ec8763486dd3d2fb585c2e6747520406e7dcef98. Re-enable enc2_dp_set_dsc_config. This function caused warnings due to missing register definitions. With the registers added, this now works Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | Revert "drm/amd/display: skip dsc config for navi10 bring up"David Francis2019-08-221-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 9e14d4f17e23ce46d346a6a22a295b4a65b9d918. optc dsc config was causing warnings due to missing register definitions. With the registers restored, the function can be re-enabled The reverted commit also disabled sanity checks and dsc power gating. The sanity check warnings are not associated with dsc, and power gating on dsc still has an issue on non-dsc monitors where the dsc hardware block is never init and so cannot respond to power gating requests. Therefore, those are left as is Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: remove duplicated include from dc_link.cYueHaibing2019-08-211-4/+0
| | | | | | | | | | | | | | | | Remove duplicated include. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Fix 32-bit divide error in wait_for_alt_modeNathan Chancellor2019-08-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building arm32 allyesconfig: ld.lld: error: undefined symbol: __aeabi_uldivmod >>> referenced by dc_link.c >>> gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a >>> referenced by dc_link.c >>> gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a time_taken_in_ns is of type unsigned long long so we need to use div_u64 to avoid this error. Fixes: b5b1f4554904 ("drm/amd/display: Enable type C hotplug") Reported-by: Randy Dunlap <rdunlap@infradead.org> Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Load NV12 SOC BB from firmwareLeo Li2019-08-151-60/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Previous SOC bounding box firmware loading logic was for NV10, when we still had it in firmware. Now that it's brought into driver code, and NV12 BB is in firmware, this logic needs to be repurposed for NV12. [How] Set SOC_BOUNDING_BOX_VALID to false, and add the dcn_2_0_nv12_soc BB struct. In init_soc_bounding_box, load firmware to nv12 BB instead. In addition, conditionally update and patch the BB, depending on ASIC REV. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Enable MPO with pre-blend color processing (RGB)Michael Strauss2019-08-153-2/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] DCN10 performs color processing before MPC combination, causes color shift in RGB colorspaces when positive brightness offset is applied However, YCbCr is still unfixed and remains disabled [How] Add layerIndex to dc_plane_state and dc_plane_info structs Re-enable MPO when brightness is adjusted and colorspace is not YCbCr Set rear plane's brightness offset to 0 when front plane visible Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: audio cannot switch to internal when display turns offyanyan kang2019-08-151-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] disable_az_endpoint has been skipped because dc->debug.az_endpoint_mute_only = true. [how] set dc->debug.az_endpoint_mute_only false when PPLIB’s PME notification function pointer is not NULL at the dcn10_resource construct function,because right now SMU/PPLIB and DAL all have the AZ D3 force PME notification implemented. AZ D3 should work. Signed-off-by: yanyan kang <Yanyan.Kang@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: check hpd before retry verify link capWenjing Liu2019-08-153-21/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] During detection link training if a display is disconnected, the current code will retry 3 times of link training on disconnected link before giving up. [how] Before each retry check for HPD status, only retry verify link cap when HPD is still high. Also put a 10ms delay between each retry to improve the chance of success. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: enable dcn_mem_pwr as golden setting updatesCharlene Liu2019-08-151-2/+1
| | | | | | | | | | | | | | | | | | Enable dcn_mem_pwr as golden setting updates Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: 3.2.46Anthony Koo2019-08-151-1/+1
| | | | | | | | | | | | Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix dcn20 global sync dml param extractionDmytro Laktyushkin2019-08-152-99/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the paremeters are extracted as if dml is calculating using pipes as we pass them in. in reality, dml internally merges pipes into planes if pipe split is detected. This change adds reverse logic to dcn20_calculate_dlg_params so that the global sync parameters can be correctly extracted for all the pipes when pipe split is enabled. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: 3.2.45Anthony Koo2019-08-151-1/+1
| | | | | | | | | | | | Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add and refine DSC logs in enable sequenceNikola Cornij2019-08-152-13/+35
| | | | | | | | | | | | | | | | | | | | | | [why] Some logs messages were not precise and some new log messages were needed after "get packed PPS" function was introduced Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add Logging for Gamma Related information (2/2)Wyatt Wood2019-08-152-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] A recent bug showed that logging would be useful in debugging various gamma issues. [How] Add logging in dc. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Remove redundant definition of dwb_source enumsJulian Parkin2019-08-151-12/+0
| | | | | | | | | | | | | | | | | | | | There are repeated (but guarded) definitions of dwb_src enums. There are also unused entires. Clean them up. Signed-off-by: Julian Parkin <julian.parkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add enum for H-timing divider modeQingqing Zhuo2019-08-152-4/+10
| | | | | | | | | | | | | | | | | | | | Add h_timing_div_mode enum to better reflect possible register values. Replace previously programmed values with enum Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Register VUPDATE_NO_LOCK interrupts for DCN2Nicholas Kazlauskas2019-08-151-10/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] These are needed to send back DRM vblank events in the case where VRR is on. Without the interrupt enabled we're deferring the events into the vblank queue and userspace is left waiting forever to get back the events they need. Found using igt@kms_vrr - the test fails immediately due to vblank timeout. [How] Register them the same way we're handling it for DCN1. This fixes igt@kms_vrr for DCN2. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: wake up ogam mem pwr before programming ocscCharlene Liu2019-08-156-7/+49
| | | | | | | | | | | | | | | | | | | | | | | | [Description] OGAM_MEM_PWR could stay in light up when driver woke up to update gamma. either disable MEM_LOW power feature or set to OGAM_bypass could make artificial color distortion goes away. Easy reproduce after LOW_MEM Power feature enables and resume from S3. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Julian Parkin <jparkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Correct DSC PPS logNikola Cornij2019-08-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] A misleading message "Programming PPS" appears before both programming and "query PPS" functions [how] Move the message from "log PPS" function to "program PPS" function Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Check if set_blank_data_double_buffer exists before callVitaly Prosyak2019-08-151-1/+2
| | | | | | | | | | | | | | | | | | | | Not all ASIC types have this function implemented - check before calling. Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Julian Parkin <jparkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Fix type of ODMCombineType fieldIlya Bakoulin2019-08-151-1/+1
| | | | | | | | | | | | | | | | | | | | The type was changed previously to better reflect possible register values. Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Remove 4:2:2 DSC supportNikola Cornij2019-08-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | [why] If DSC is available, a higher picture quality is achieved by using DSC with 4:4:4 format. Using 4:2:2 instead does not offer any benefit and would only introduce loss of quality. Removing it reduces maintenance and testing effort. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: reprogram VM config when system resumeLewis Huang2019-08-151-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] The vm config will be clear to 0 when system enter S4. It will cause hubbub didn't know how to fetch data when system resume. The flip always pending because earliest_inuse_address and request_address are different. [How] Reprogram VM config when system resume Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Enable type C hotplugEric Yang2019-08-153-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | [Why and How] We want to change where timing is done for alt mode. Some of the commented out #ifs are needed for DCN20 so we enable them for that case. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: HUBP/HUBBUB register programming fixesIlya Bakoulin2019-08-155-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] - Need to change interface function signature / add an enum to reflect the available register field values [How] - Add a new enum and modify existing functions to use it instead of bool Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: update optc odm interface for more than 2 oppsDmytro Laktyushkin2019-08-156-26/+31
| | | | | | | | | | | | | | | | | | | | Current optc odm interface only accepts 2 opps, we need to expand this to allow 4 to 1 odm combine. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Update DML parametersIlya Bakoulin2019-08-154-6/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Need to add DML struct members that were omitted in previous DML implemenations. [How] - Add missing enum values - Add missing struct members - Set new input values in the fetch functions Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Remove duplicate interface for programming FBJulian Parkin2019-08-156-160/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] There are currently two interfaces for exactly the same thing: hupb_update_dchub in hupb and update_dchub in hubbub. The hubbub version is currently unused past dcn10, largely because the call from the dcn10 hardware sequencer does not call through the interface, so the hupb interface was used instead. This is confusing because of the duplicate code, the unused functions, and the fact that more that one block currently owns this set of registers. [How] Remove the hubp interface entirely, as well as the register declarations that are not longer needed because of this. Change the call site to always call the hubbub version through the interface. Fix the update_dchub function in dcn20_hubbub.c to program the correct registers for dcn20. Signed-off-by: Julian Parkin <julian.parkin@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix pipe selection logic in validateJun Lei2019-08-151-2/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] Resource mapping done in dcn20_validate_bandwidth has a flaw: When a full update is performed, the HWSS will only update the MPCC tree for the stream that is updated as opposed to all streams. This means that when mapping pipes in validation, care must be taken to not change any existing mapping, otherwise it leads to partial hw programming [how] it's not strictly necessary to track which stream/mpcc tree is being updated, but rather it's sufficient to compare current and new state and just keep pipes that were previously already mapped unchanged. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: 3.2.44Aric Cyr2019-08-151-1/+1
| | | | | | | | | | | | Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Set DSC before DIG front-end is connected to its back-endNikola Cornij2019-08-157-84/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] At the time DIG FE is connected to its BE, the clocks in OTG are enabled and PHY will also be set up. When DSC has to be used to fit the stream into the available bandwidth, without DSC being set DIG could get exposed to the higer bandwidth it (or link) could handle. This causes the HW to "reject" video enable setup (the register shows that video enable was attempted, but the status bit shows it as disabled). [how] - Separate DSC setup into DSC register config and DSC PPS SDP setup - Move most of the DSC setup (register config) to before dcn10_link_encoder_connect_dig_be_to_fe() is called - Set up DSC PPS SDP after DIG FE is connected to its BE. This is because setting DSC PPS SDP before that has no effect. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Change DSC policy from slices per column to minimum slice ↵Nikola Cornij2019-08-151-39/+32
| | | | | | | | | | | | | | | | | | | | | | height [why] Minimum slice height is recommended by VESA DSC Spreadsheet user guide Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: clean up DML for DCN2xJun Lei2019-08-152-17/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] Previous "less risky" implemenation of 3 tiered fallback is no longer necessary since DMLv2 has gone through proper validation. v2 can now be used as the default and 1 level of fallback can be removed [how] remove previous workaround implemenation Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: enabling seamless boot sequence for dcn2Martin Leung2019-08-1517-36/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Seamless boot (building SW state inheriting BIOS-initialized timing) was enabled on DCN2, including fixes [How] Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/ Pixel clock. This is part 2 of 2 for seamless boot NV10 Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix dcn-specific clk_mgr init_clocksMartin Leung2019-08-152-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] underflow seen on certain monitor setups caused by making dcnxx_init_hw generic [How] by moving dcn20_init_hw into dcn10, we added a dcn-specific clk_mgr init (dc->clk_mgr->funcs->init_clocks()). Thus, put old clk_mgr memset in an else statement so both memsets don't get set Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Make init_hw and init_pipes generic for seamless bootMartin Leung2019-08-159-313/+312
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] For seamless boot the init_hw sequence must be split into actual hardware vs pipes, in order to defer pipe initialization to set mode and skip of pipe-destructive sequences [How] made dcn10_init_hw and dcn10_init_pipes generic for future dcns to inherit deleted dcn20 specific versions. This is part 1 of a 2 partimplementation of seamless boot Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: 3.2.43Aric Cyr2019-08-151-1/+1
| | | | | | | | | | | | Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: wait for pending complete when enabling a planeJun Lei2019-08-151-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] When planes are enabled, they must be enabled using VSYNC update (not immediate). However, before the VUPDATE occurs, DM may call with an "immediate" flip which is address only. This operation would normally be okay, but if the locking for immediate flip happens to occur before the VUPDATE associated with the initial plane enablement, it will cause HW to hang. [how] HWSS should enforce plane enable in HW to be synchronous with the call that enables the plane. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: refactor gpio to allocate hw_container in constructorSu Sung Chung2019-08-1517-137/+236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] if dynamic allocation fails during gpio_open, it will cause crash due to page fault. [how] handle allocation when gpio object gets created and prevent from calling gpio_open if allocation failed Signed-off-by: Su Sung Chung <Su.Chung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add work-around option to skip DCN20 clock updatesJaehyun Chung2019-08-152-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | [Why] Auto Overclock Memory fails for some systems that don't support p-state. [How] Implement the workaround, and it's corresponding enable flag. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fixup DPP programming sequenceJun Lei2019-08-159-47/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] DC does not correct account for the fact that DPP DTO is double buffered while DPP ref is not. This means that when DPP ref clock is lowered when it's "safe to lower", the DPP blocks that need an increased divider will temporarily have actual DPP clock drop below minimum while DTO double buffering takes effect. This results in temporary underflow. [how] To fix this, DPP clock cannot be programmed atomically, but rather be broken up into the DTO and the ref. Each has a separate "safe to lower" logic. When doing "prepare" the ref and dividers may only increase. When doing "optimize", both may decrease. It is guaranteed that we won't exceed max DPP clock because we do not use dividers larger than 1. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: make firmware info only load once during dc_bios createDmytro Laktyushkin2019-08-1512-79/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently every time DC wants to access firmware info we make a call into VBIOS. This makes no sense as there is nothing that can change runtime inside fw info and can cause issues when calling unstable bios during bringup. This change eliminate this behavior by only calling bios once for fw info and keeping it stored as part of dc_bios. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Synchronous DisplayPort Link TrainingDavid Galiffi2019-08-157-125/+282
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] We require a method to perform synchronous link training. [HOW] Sync LT is broken into 3 basic steps. "Begin" starts the state machine, and resets "preferred" link settings. "Attempt" will attempt to train the link with a given set of training parameters. "End" stops the state machine, and will optionally disable the link phy. Between "Begin" and "End" DPCD:600h must not be set to "2" (D3:Powered Down). Between "Begin" and "End", there may be multiple "Attempts" with different training parameters. Signed-off-by: David Galiffi <david.galiffi@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Improve sharing of HUBBUB register listsJulian Parkin2019-08-151-3/+6
| | | | | | | | | | | | | | | | | | | | | | Add DCN20 common register list that contains registers shared between DCN20 generations. Signed-off-by: Julian Parkin <julian.parkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add 22, 24, and 26 degammaVitaly Prosyak2019-08-151-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | [Why & How] Support degamma ROM and RAM based on hardware capabilities. Some refactoring into color module Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Gary Kattan <Gary.Kattan@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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