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| * | | crypto: mv_cesa - request registers memory regionBoris BREZILLON2015-05-251-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mv_cesa driver does not request the CESA registers memory region. Since we're about to add a new CESA driver, we need to make sure only one of these drivers probe the CESA device, and requesting the registers memory region is a good way to achieve that. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: nx - Remove unnecessary maxauthsize checkHerbert Xu2015-05-221-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The crypto layer already checks maxauthsize when setauthsize is called. So there is no need to check it again within setauthsize. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: ixp4xx - Use crypto_aead_maxauthsizeHerbert Xu2015-05-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses the helper crypto_aead_maxauthsize instead of directly dereferencing aead_alg. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: caam - Use old_aead_algHerbert Xu2015-05-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch replaces references to aead_alg with old_aead_alg. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: omap-sham - Add support for omap3 devicesPali Rohár2015-05-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | omap3 support is same as omap2, just with different IO address (specified in DT) Signed-off-by: Pali Rohár <pali.rohar@gmail.com> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: n2 - use md5 IV MD5_HX instead of their raw valueLABBE Corentin2015-05-181-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since MD5 IV are now available in crypto/md5.h, use them. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: nx - remove 842-nx null checksDan Streetman2015-05-181-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the null checks for tfm, src, slen, dst, dlen; tfm will never be null and the other fields are always expected to be set correctly. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Dan Streetman <ddstreet@ieee.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: vmx - fix two mistyped textsPaulo Flabiano Smorigo2015-05-152-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | One mistyped description and another mistyped target were corrected. Signed-off-by: Paulo Flabiano Smorigo <pfsmorigo@linux.vnet.ibm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: qat - rm unneeded header includeTadeusz Struk2015-05-151-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't need proc_fs.h Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: qat - remove unused structure membersTadeusz Struk2015-05-151-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleanup unused structure members. Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: omap-sham - Check for return value from pm_runtime_get_syncPali Rohár2015-05-151-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function pm_runtime_get_sync could fail and we need to check return value to prevent kernel crash. Signed-off-by: Pali Rohár <pali.rohar@gmail.com> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - static code checker fixesHoria Geant?2015-05-131-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -change req_ctx->nbuf from u64 to unsigned int to silence checker warnings; this is safe since nbuf value is <= HASH_MAX_BLOCK_SIZE -remove unused value read from TALITOS_CCPSR; there is no requirement to read upper 32b before reading lower 32b of a 64b register; SEC RM mentions: "reads can always be done by byte, word, or dword" -remove unused return value of sg_to_link_tbl() -change "len" parameter of map_single_talitos_ptr() and to_talitos_ptr_len() to unsigned int; later, cpu_to_be16 will __force downcast the value to unsigned short without any checker warning Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - avoid out of bound scatterlist iteratorHoria Geant?2015-05-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check return value of scatterlist_sg_next(), i.e. don't rely solely on number of bytes to be processed or number of scatterlist entries. Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | Revert "crypto: talitos - convert to use be16_add_cpu()"Horia Geant?2015-05-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 7291a932c6e27d9768e374e9d648086636daf61c. The conversion to be16_add_cpu() is incorrect in case cryptlen is negative due to premature (i.e. before addition / subtraction) implicit conversion of cryptlen (int -> u16) leading to sign loss. Cc: <stable@vger.kernel.org> # 3.10+ Cc: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - avoid memleak in talitos_alg_alloc()Horia Geant?2015-05-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Cc: <stable@vger.kernel.org> # 3.2+ Fixes: 1d11911a8c57 ("crypto: talitos - fix warning: 'alg' may be used uninitialized in this function") Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - fix size calculation in talitos_edesc_alloc()Dan Carpenter2015-05-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The + operation has higher precedence than ?: so we need parentheses here. Otherwise we may end up allocating a max of only one "cryptlen" instead of two. Fixes: 6f65f6ac5fb3 ('crypto: talitos - implement scatter/gather copy for SEC1') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: qat - Use crypto_aead_set_reqsize helperHerbert Xu2015-05-131-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses the crypto_aead_set_reqsize helper to avoid directly touching the internals of aead. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: picoxcell - Use crypto_aead_set_reqsize helperHerbert Xu2015-05-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses the crypto_aead_set_reqsize helper to avoid directly touching the internals of aead. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: ixp4xx - Use crypto_aead_set_reqsize helperHerbert Xu2015-05-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses the crypto_aead_set_reqsize helper to avoid directly touching the internals of aead. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: caam - Remove unnecessary reference to crt_aeadHerbert Xu2015-05-131-48/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | crt_aead is an internal implementation detail and must not be used outside of the crypto API itself. This patch replaces the unnecessary uses of crt_aead with crypto_aead_ivsize. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - Include internal/aead.hHerbert Xu2015-05-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All AEAD implementations must include internal/aead.h in order to access required helpers. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: qat - Include internal/aead.hHerbert Xu2015-05-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All AEAD implementations must include internal/aead.h in order to access required helpers. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: nx - Include internal/aead.hHerbert Xu2015-05-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All AEAD implementations must include internal/aead.h in order to access required helpers. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: ixp4xx - Include internal/aead.hHerbert Xu2015-05-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All AEAD implementations must include internal/aead.h in order to access required helpers. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: caam - Include internal/aead.hHerbert Xu2015-05-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All AEAD implementations must include internal/aead.h in order to access required helpers. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: qat - add driver versionAllan, Bruce W2015-05-113-0/+9
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: nx - add hardware 842 crypto comp algDan Streetman2015-05-113-0/+597
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add crypto compression alg for 842 hardware compression and decompression, using the alg name "842" and driver_name "842-nx". This uses only the PowerPC coprocessor hardware for 842 compression. It also uses the hardware for decompression, but if the hardware fails it will fall back to the 842 software decompression library, so that decompression never fails (for valid 842 compressed buffers). A header must be used in most cases, due to the hardware's restrictions on the buffers being specifically aligned and sized. Due to the header this driver adds, compressed buffers it creates cannot be directly passed to the 842 software library for decompression. However, compressed buffers created by the software 842 library can be passed to this driver for hardware 842 decompression (with the exception of buffers containing the "short data" template, as lib/842/842.h explains). Signed-off-by: Dan Streetman <ddstreet@ieee.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: nx - simplify pSeries nx842 driverDan Streetman2015-05-111-626/+153
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify the pSeries NX-842 driver: do not expect incoming buffers to be exactly page-sized; do not break up input buffers to compress smaller blocks; do not use any internal headers in the compressed data blocks; remove the software decompression implementation; implement the pSeries nx842_constraints. This changes the pSeries NX-842 driver to perform constraints-based compression so that it only needs to compress one entire input block at a time. This removes the need for it to split input data blocks into multiple compressed data sections in the output buffer, and removes the need for any extra header info in the compressed data; all that is moved (in a later patch) into the main crypto 842 driver. Additionally, the 842 software decompression implementation is no longer needed here, as the crypto 842 driver will use the generic software 842 decompression function as a fallback if any hardware 842 driver fails. Signed-off-by: Dan Streetman <ddstreet@ieee.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: nx - add PowerNV platform NX-842 driverDan Streetman2015-05-116-10/+737
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for NX-842 hardware on the PowerNV platform. This allows the use of the 842 compression hardware coprocessor on the PowerNV platform. Signed-off-by: Dan Streetman <ddstreet@ieee.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: nx - add nx842 constraintsDan Streetman2015-05-113-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "constraints" for the NX-842 driver. The constraints are used to indicate what the current NX-842 platform driver is capable of. The constraints tell the NX-842 user what alignment, min and max length, and length multiple each provided buffers should conform to. These are required because the 842 hardware requires buffers to meet specific constraints that vary based on platform - for example, the pSeries max length is much lower than the PowerNV max length. Signed-off-by: Dan Streetman <ddstreet@ieee.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: nx - add NX-842 platform frontend driverDan Streetman2015-05-116-44/+238
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add NX-842 frontend that allows using either the pSeries platform or PowerNV platform driver (to be added by later patch) for the NX-842 hardware. Update the MAINTAINERS file to include the new filenames. Update Kconfig files to clarify titles and descriptions, and correct dependencies. Signed-off-by: Dan Streetman <ddstreet@ieee.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: nx - rename nx-842.c to nx-842-pseries.cDan Streetman2015-05-112-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the entire NX-842 driver for the pSeries platform from the file nx-842.c to nx-842-pseries.c. This is required by later patches that add NX-842 support for the PowerNV platform. This patch does not alter the content of the pSeries NX-842 driver at all, it only changes the filename. Signed-off-by: Dan Streetman <ddstreet@ieee.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: qat - do not duplicate string containing firmware nameAllan, Bruce W2015-04-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use ADF_DH895XCC_FW instead of duplicating the string "qat_895xcc.bin" when referring to the DH895xCC firmware. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: nx - Fixing SHA update bugLeonidas Da Silva Barbosa2015-04-264-119/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bug happens when a data size less than SHA block size is passed. Since first attempt will be saved in buffer, second round attempt get into two step to calculate op.inlen and op.outlen. The issue resides in this step. A wrong value of op.inlen and outlen was being calculated. This patch fix this eliminate the nx_sha_build_sg_list, that is useless in SHA's algorithm context. Instead we call nx_build_sg_list directly and pass a previous calculated max_sg_len to it. Signed-off-by: Leonidas S. Barbosa <leosilva@linux.vnet.ibm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: nx - Fixing NX data alignment with nx_sg listLeonidas Da Silva Barbosa2015-04-261-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In NX we need to pass always a 16 multiple size nx_sg_list to co processor. Trim function handle with this assuring all nx_sg_lists are 16 multiple size, although data was not being considerated when crop was done. It was causing an unalignment between size of the list and data, corrupting csbcpb fields returning a -23 H_ST_PARM error, or invalid operation. This patch fix this recalculating how much data should be put back in to_process variable what assures the size of sg_list will be correct with size of the data. Signed-off-by: Leonidas S. Barbosa <leosilva@linux.vnet.ibm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: caam - Remove bogus references to crypto API internalsHerbert Xu2015-04-231-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The caam driver includes algorithm types that it doesn't even use, such as struct rng_alg which has recently been moved to an internal header file and consequently broke the build of caam. This patch removes these bogus references. Reported-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - Add fsl,sec1.0 compatibleLEROY Christophe2015-04-211-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We add a specific compatible for SEC1, to handle the differences between SEC1 and SEC2+ Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - SEC1 bugs on 0 data hashLEROY Christophe2015-04-211-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SEC1 bugs on 0 data hash, so we submit an already padded block representing 0 data Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - implement scatter/gather copy for SEC1LEROY Christophe2015-04-212-38/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SEC1 doesn't support scatter/gather, SEC1 doesn't handle link tables. Therefore, for SEC1 we have to do it by SW. For that, we reserve space at the end of the extended descriptor, in lieu of the space reserved for the link tables on SEC2, and we perform sg_copy() when preparing the descriptors We also adapt the max buffer size which is only 32k on SEC1 while it is 64k on SEC2+ Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - adapt interrupts and reset functions to SEC1LEROY Christophe2015-04-212-67/+199
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adapts the interrupts handling and reset function for SEC1. On SEC1, registers are almost similar to SEC2+, but bits are sometimes located at different places. So we need to define TALITOS1 and TALITOS2 versions of some fields, and manage according to whether it is SEC1 or SEC2. On SEC1, only one interrupt vector is dedicated to the SEC, so only interrupt_4ch is needed. On SEC1, interrupts are enabled by clearing related bits in IMR, while on SEC2, interrupts are enabled by seting the bits in IMR. SEC1 also performs parity verification in the DES Unit. We have to disable this feature because the test vectors provided in the kernel have parity errors. In reset functions, only SEC2 supports continuation after error. For SEC1, we have to reset in all cases. For errors handling, SEC2+ names have been kept, but displayed text have been amended to reflect exact meaning on SEC1. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - base address for Execution UnitsLEROY Christophe2015-04-212-55/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SEC 1.0, 1.2 and 2.x+ have different EU base addresses, so we need to define pointers for each EU in the driver private data structure. The proper address is set by the probe function depending on the SEC type, in order to provide access to the proper address. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - adaptation of talitos_submit() for SEC1LEROY Christophe2015-04-212-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SEC1 descriptor is a bit different to SEC2+ descriptor. talitos_submit() will have to copy hdr field into hdr1 field and send the descriptor starting at hdr1 up to next_desc. For SEC2, it remains unchanged and next_desc is just ignored. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - fill in talitos descriptor iaw SEC1 or SEC2+LEROY Christophe2015-04-211-38/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | talitos descriptor is slightly different for SEC1 and SEC2+, so lets the helper function that fills the descriptor take into account the type of SEC. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - Add a feature to tag SEC1LEROY Christophe2015-04-212-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We add a new feature in the features field, to mark compatible "fsl,sec1.0" We also define a helper function called has_ftr_sec1() to help functions quickly determine if they are running on SEC1 or SEC2+. When only SEC1 or SEC2 is compiled in, has_ftr_sec1() return trivial corresponding value. If both are compiled in, feature field is checked. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - add sub-choice in talitos CONFIG for SEC1LEROY Christophe2015-04-211-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a CONFIG option to select SEC1, SEC2+ or both. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - enhanced talitos_desc struct for SEC1LEROY Christophe2015-04-211-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enhances the talitos_desc struct with fields for SEC1. SEC1 has only one header field, and has a 'next_desc' field in addition. This mixed descriptor will continue to fit SEC2, and for SEC1 we will recopy hdr value into hdr1 value in talitos_submit() Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - helper function for ptr lenLEROY Christophe2015-04-211-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a helper function for reads and writes of the len param of the talitos descriptor. This will help implement SEC1 later. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - remove param 'extent' in map_single_talitos_ptr()LEROY Christophe2015-04-211-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | map_single_talitos_ptr() is always called with extent == 0, so lets remove this unused parameter Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - Add a helper function to clear j_extent fieldLEROY Christophe2015-04-211-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | j_extent field is specific to SEC2 so we add a helper function to clear it so that SEC1 can redefine that function as nop Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | crypto: talitos - talitos_ptr renamed ptr for more lisibilityLEROY Christophe2015-04-211-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux CodyingStyle recommends to use short variables for local variables. ptr is just good enough for those 3 lines functions. It helps keep single lines shorter than 80 characters. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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