| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | | * | clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver | Icenowy Zheng | 2017-03-06 | 3 | -9/+323 | |
| | | * | clk: sunxi-ng: gate: Support common pre-dividers | Chen-Yu Tsai | 2017-03-06 | 1 | -0/+47 | |
| | * | | Merge branch 'clk-fixes' into clk-next | Stephen Boyd | 2017-04-17 | 4 | -0/+74 | |
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| | * | | | clk: cs2000: use existing priv_to_dev() to getting struct device | Kuninori Morimoto | 2017-04-12 | 1 | -5/+3 | |
| | * | | | Merge tag 'meson-clk-for-4.12' of git://github.com/BayLibre/clk-meson into cl... | Michael Turquette | 2017-04-12 | 6 | -13/+322 | |
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| | | * | | | clk: meson: mpll: use 64bit math in rate_from_params | Martin Blumenstingl | 2017-04-07 | 1 | -1/+1 | |
| | | * | | | clk: meson: mpll: fix division by zero in rate_from_params | Martin Blumenstingl | 2017-04-07 | 1 | -11/+15 | |
| | | * | | | clk: meson: gxbb: add cts_i958 clock | Jerome Brunet | 2017-04-07 | 2 | -1/+23 | |
| | | * | | | clk: meson: gxbb: add cts_mclk_i958 | Jerome Brunet | 2017-04-07 | 2 | -1/+56 | |
| | | * | | | clk: meson: gxbb: add cts_amclk | Jerome Brunet | 2017-04-07 | 2 | -1/+71 | |
| | | * | | | clk: meson: add audio clock divider support | Jerome Brunet | 2017-04-07 | 3 | -1/+155 | |
| | | * | | | clk: meson: gxbb: protect against holes in the onecell_data array | Jerome Brunet | 2017-04-07 | 1 | -0/+4 | |
| | * | | | | Merge tag 'amlogic-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/khil... | Michael Turquette | 2017-04-12 | 7 | -55/+854 | |
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| | | * | | | Merge branch 'v4.12/clk-drivers' into v4.12/clk | Kevin Hilman | 2017-04-04 | 7 | -48/+840 | |
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| | | | * | | | clk: meson-gxbb: Add GXL/GXM GP0 Variant | Neil Armstrong | 2017-04-04 | 2 | -28/+275 | |
| | | | * | | | clk: meson-gxbb: Add GP0 PLL init parameters | Neil Armstrong | 2017-04-04 | 1 | -0/+13 | |
| | | | * | | | clk: meson: Add support for parameters for specific PLLs | Neil Armstrong | 2017-04-04 | 2 | -2/+74 | |
| | | | * | | | clk: meson-gxbb: Add MALI clocks | Neil Armstrong | 2017-04-04 | 1 | -0/+139 | |
| | | | * | | | clk: meson: mpll: correct N2 maximum value | Jerome Brunet | 2017-03-27 | 1 | -1/+1 | |
| | | | * | | | clk: meson8b: add the mplls clocks 0, 1 and 2 | Jerome Brunet | 2017-03-27 | 2 | -1/+122 | |
| | | | * | | | clk: meson: gxbb: mpll: use rw operation | Jerome Brunet | 2017-03-27 | 1 | -3/+3 | |
| | | | * | | | clk: meson: mpll: add rw operation | Jerome Brunet | 2017-03-27 | 3 | -6/+180 | |
| | | | * | | | clk: gxbb: put dividers and muxes in tables | Jerome Brunet | 2017-03-27 | 1 | -8/+20 | |
| | | | * | | | clk: meson8b: put dividers and muxes in tables | Jerome Brunet | 2017-03-27 | 1 | -4/+18 | |
| | | | * | | | clk: meson: add missing const qualifiers on gate arrays | Jerome Brunet | 2017-03-27 | 2 | -2/+2 | |
| | | | * | | | clk: meson: fix SET_PARM macro | Jerome Brunet | 2017-03-27 | 1 | -1/+1 | |
| | * | | | | | clk: aggregate return codes of notify chains | Peter De Schrijver | 2017-04-12 | 1 | -0/+2 | |
| | * | | | | | clk: add clk_possible_parents debugfs file | Peter De Schrijver | 2017-04-12 | 1 | -0/+32 | |
| | * | | | | | clk: imx: correct uart4_serial clock name in driver for i.MX6UL | Robin van der Gracht | 2017-04-12 | 1 | -1/+1 | |
| | * | | | | | clk: zte: Mark pll config tables as const | Stephen Boyd | 2017-04-12 | 1 | -2/+2 | |
| | * | | | | | clk: zte: add pll_vga clock for zx296718 | Shawn Guo | 2017-04-12 | 1 | -0/+24 | |
| | * | | | | | clk: zte: pd_bit is not 0 on zx296718 | Shawn Guo | 2017-04-12 | 2 | -2/+16 | |
| | * | | | | | clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks | Shawn Guo | 2017-04-12 | 1 | -3/+3 | |
| | * | | | | | clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock | Robin van der Gracht | 2017-04-12 | 1 | -4/+5 | |
| | * | | | | | Merge tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/g... | Michael Turquette | 2017-04-12 | 14 | -253/+699 | |
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| | | * | | | | | clk: tegra: Don't reset PLL-CX if it is already enabled | Jon Hunter | 2017-04-04 | 1 | -4/+4 | |
| | | * | | | | | clk: tegra: Add missing Tegra210 clocks | Peter De Schrijver | 2017-04-04 | 3 | -0/+19 | |
| | | * | | | | | clk: tegra: Propagate clk_out_x rate to parent | Alex Frid | 2017-04-04 | 1 | -2/+4 | |
| | | * | | | | | clk: tegra: Fix build warnings on Tegra20/Tegra30 | Thierry Reding | 2017-03-20 | 2 | -2/+2 | |
| | | * | | | | | clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on | Peter De Schrijver | 2017-03-20 | 1 | -0/+2 | |
| | | * | | | | | clk: tegra: Add SATA seq input control | Peter De Schrijver | 2017-03-20 | 1 | -0/+25 | |
| | | * | | | | | clk: tegra: Add Tegra210 special resets | Peter De Schrijver | 2017-03-20 | 1 | -0/+85 | |
| | | * | | | | | clk: tegra: Rework pll_u | Peter De Schrijver | 2017-03-20 | 2 | -197/+272 | |
| | | * | | | | | clk: tegra: Implement reset control reset | Mikko Perttunen | 2017-03-20 | 1 | -0/+16 | |
| | | * | | | | | clk: tegra: Fix disable unused for clocks sharing enable bit | Peter De Schrijver | 2017-03-20 | 1 | -0/+3 | |
| | | * | | | | | clk: tegra: Handle UTMIPLL IDDQ | Peter De Schrijver | 2017-03-20 | 1 | -0/+26 | |
| | | * | | | | | clk: tegra: Add aclk | Peter De Schrijver | 2017-03-20 | 1 | -0/+10 | |
| | | * | | | | | clk: tegra: Add super clock mux/divider | Peter De Schrijver | 2017-03-20 | 2 | -5/+89 | |
| | | * | | | | | clk: tegra: Define Tegra210 DMIC clocks | Peter De Schrijver | 2017-03-20 | 3 | -1/+28 | |
| | | * | | | | | clk: tegra: Fix constness for peripheral clocks | Peter De Schrijver | 2017-03-20 | 2 | -4/+4 | |
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