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* clk: tegra: Remove forced clk_enable of uartdPeter De Schrijver2013-04-041-1/+1
| | | | | | | | | The UART driver enables the console uart clock, so we don't need to do that anymore in this file. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: devicetree match for nvidia,tegra114-carPeter De Schrijver2013-04-042-0/+7
| | | | | | Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Implement clocks for Tegra114Peter De Schrijver2013-04-042-0/+2086
| | | | | | | | Implement clocks for Tegra114. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Workaround for Tegra114 MSENC problemPeter De Schrijver2013-04-042-0/+11
| | | | | | | | Workaround a hardware bug in MSENC during clock enable. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Add flags to tegra_clk_periph()Peter De Schrijver2013-04-044-10/+14
| | | | | | | | | We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag, most notably mselect, which is a bridge between AXI and most peripherals. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Add new fields and PLL types for Tegra114Peter De Schrijver2013-04-042-1/+888
| | | | | | | | | Tegra114 introduces new PLL types. This requires new clocktypes as well as some new fields in the pll structure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: move from a lock bit idx to a lock maskPeter De Schrijver2013-04-044-25/+25
| | | | | | | | | PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits. So switch to a lock mask to be able to test both at the same time. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Add PLL post divider tablePeter De Schrijver2013-04-044-6/+59
| | | | | | | | | Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. Introduce a table based approach and switch PLLU to it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLEPeter De Schrijver2013-04-042-0/+7
| | | | | | | | | Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are always functional. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Add TEGRA_PLL_BYPASS flagPeter De Schrijver2013-04-042-4/+10
| | | | | | | | | Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use this bit when available. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Refactor PLL programming codePeter De Schrijver2013-04-044-293/+356
| | | | | | | | | | | | | | | | | | | | Refactor the PLL programming code to make it useable by the new PLL types introduced by Tegra114. The following changes were done: * Split programming the PLL into updating m,n,p and updating cpcon * Move locking from _update_pll_cpcon() to clk_pll_set_rate() * Introduce _get_pll_mnp() helper * Move check for identical m,n,p values to clk_pll_set_rate() * struct tegra_clk_pll_freq_table will always contain the values as defined by the hardware. * Simplify the arguments to clk_pll_wait_for_lock() * Split _tegra_clk_register_pll() Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: provide dummy cpu car opsPeter De Schrijver2013-04-041-1/+2
| | | | | | | | | | | tegra_boot_secondary() relies on some of the car ops. This means having an uninitialized tegra_cpu_car_ops will lead to an early boot panic. Providing a dummy struct avoids this and makes adding Tegra114 clock support in a bisectable way a lot easier. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: defer application of init tableStephen Warren2013-04-044-2/+25
| | | | | | | | | | | | | | | | | The Tegra clock driver is initialized during the ARM machine descriptor's .init_irq() hook. It can't be initialized earlier, since dynamic memory usage is required. It can't be initialized later, since the .init_timer() hook needs the clocks initialized. However, at this time, udelay() doesn't work. The Tegra clock initialization table may enable some PLLs. Enabling a PLL may require usage of udelay(). Hence, this can't happen right when the clock driver is initialized. To solve this, separate the clock driver initialization from the clock table processing, so they can execute at separate times. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Fix cdev1 and cdev2 IDsPrashant Gaikwad2013-04-042-2/+2
| | | | | | | | Correct IDs for cdev1 and cdev2 are 94 and 93 respectively. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: split into separate driver and device-tree patches] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Make gr2d and gr3d clocks children of pll_cThierry Reding2013-04-042-0/+4
| | | | | | | | | | | | | | By default these clocks are children of pll_m, but in downstream kernels they are reparented to pll_c. While at it, decrease their frequencies to 300 MHz because the defaults aren't in the specified range. gr2d can reportedly run at much higher frequencies, but 300 MHz works and is a more conservative default. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Export peripheral reset functionsThierry Reding2013-04-041-0/+3
| | | | | | | | | | | | | The tegra_periph_reset_assert() and tegra_periph_reset_deassert() functions can be used by drivers to reset peripherals. In order to allow such drivers to be built as modules, export the functions. Note that this restores the status quo as the functions were exported before the move to the drivers/clk tree. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Fix periph_clk_to_bit macroYen Lin2013-04-041-1/+1
| | | | | | | | | | | | | | The parameter name should be "gate", not "periph". This worked, however, because it happens that everywhere periph_clk_to_bit is called, "gate" was in the local scope. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Andrew Chew <achew@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Merge remote-tracking branch 'linaro_mturquette_linux/clk-for-3.10' into ↵Stephen Warren2013-04-0416-123/+1422
|\ | | | | | | for-3.10/clk
| * clk: allow reentrant calls into the clk frameworkMike Turquette2013-04-021-2/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reentrancy into the clock framework is necessary for clock operations that result in nested calls to the clk api. A common example is a clock that is prepared via an i2c transaction, such as a clock inside of a discrete audio chip or a power management IC. The i2c subsystem itself will use the clk api resulting in a deadlock: clk_prepare(audio_clk) i2c_transfer(..) clk_prepare(i2c_controller_clk) The ability to reenter the clock framework prevents this deadlock. Other use cases exist such as allowing .set_rate callbacks to call clk_set_parent to achieve the best rate, or to save power in certain configurations. Yet another example is performing pinctrl operations from a clk_ops callback. Calls into the pinctrl subsystem may call clk_{un}prepare on an unrelated clock. Allowing for nested calls to reenter the clock framework enables both of these use cases. Reentrancy is implemented by two global pointers that track the owner currently holding a global lock. One pointer tracks the owner during sleepable, mutex-protected operations and the other one tracks the owner during non-interruptible, spinlock-protected operations. When the clk framework is entered we try to hold the global lock. If it is held we compare the current task against the current owner; a match implies a nested call and we reenter. If the values do not match then we block on the lock until it is released. Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org> Cc: David Brown <davidb@codeaurora.org> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
| * clk: abstract locking out into helper functionsMike Turquette2013-04-021-38/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | Create locking helpers for the global mutex and global spinlock. The definitions of these helpers will be expanded upon in the next patch which introduces reentrancy into the locking scheme. Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org> Cc: David Brown <davidb@codeaurora.org> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
| * clk: zynq: Add missing zynq clk headerMichal Simek2013-03-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | Include zynq clk header where init function is declared. It removes this sparse warning: drivers/clk/clk-zynq.c:373:13: warning: symbol 'xilinx_zynq_clocks_init' was not declared. Should it be static? Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: sunxi: rename compatible stringsEmilio López2013-03-271-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the introduction of the Allwinner SoC platforms, sunxi was initially meant as a generic name for all the variants of the Allwinner SoC. It was ok at the time of the support of only the A10 and A13 that look pretty much the same; but it's beginning to be troublesome with the future addition of the Allwinner A31 (sun6i) that is quite different, and would introduce some weird logic, where sunxi would actually mean in some case sun4i and sun5i but without sun6i... Moreover, it makes the compatible strings naming scheme not consistent with other architectures, where usually for this kind of compability, we just use the oldest SoC name that has this IP, so let's do just this. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: arm: sunxi: Add a new clock driver for sunxi SOCsEmilio López2013-03-275-0/+575
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit implements the base CPU clocks for sunxi devices. It has been tested using a slightly modified cpufreq driver from the linux-sunxi 3.0 tree. Additionally, document the new bindings introduced by this patch. Idling: / # cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc32k 0 0 32768 osc24M_fixed 0 0 24000000 osc24M 0 0 24000000 apb1_mux 0 0 24000000 apb1 0 0 24000000 pll1 0 0 60000000 cpu 0 0 60000000 axi 0 0 60000000 ahb 0 0 60000000 apb0 0 0 30000000 dummy 0 0 0 After "yes >/dev/null &": / # cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc32k 0 0 32768 osc24M_fixed 0 0 24000000 osc24M 0 0 24000000 apb1_mux 0 0 24000000 apb1 0 0 24000000 pll1 0 0 1008000000 cpu 0 0 1008000000 axi 0 0 336000000 ahb 0 0 168000000 apb0 0 0 84000000 dummy 0 0 0 Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: ux500: Fix prcmu clocks registrationMaxime Coquelin2013-03-271-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In clk_reg_prcmu(), clk->hw.init field is assigned with a reference local to clk_reg_prcmu() function. This patch replaces references to clk->hw.init with calls to __clk_get_name when called after clock registration. This patch applies on top of v3.9-rc4. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: resolved trivial merge issues]
| * clk: Add composite clock typePrashant Gaikwad2013-03-262-0/+202
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: add table lookup to muxPeter De Schrijver2013-03-222-19/+58
| | | | | | | | | | | | | | | | | | | | Add a table lookup feature to the mux clock. Also allow arbitrary masks instead of the width. This will be used by some clocks on Tegra114. Also adapt the tegra periph clk because it uses struct clk_mux directly. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: Fix incorrect return type in clk.cSachin Kamat2013-03-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | Return type of function clk_propagate_rate_change is a pointer. But 0 was being returned. Change it to NULL. Silences the following warning: drivers/clk/clk.c:977:24: warning: Using plain integer as NULL pointer Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reviewed-by: Pankaj Jangra <jangra.pankaj9@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: prima2: fix return value check in sirfsoc_of_clk_init()Wei Yongjun2013-03-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | In case of error, the function clk_get() returns ERR_PTR() not NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Barry Song <21cnbao@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: added missing parenthesis to fix compile break]
| * clk:SPEAr1340: Correct parent clock configurationVipul Kumar Samar2013-03-211-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch corrects wrongly configured parent clock for following devices: * Video enc/decoder * Video ip * Pin control * ACP * camx Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Reviewed-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: Add axi-clkgen driverLars-Peter Clausen2013-03-193-0/+340
| | | | | | | | | | | | | | | | | | | | | | | | This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: ux500: Support is_prepared callback for clk-prcmuUlf Hansson2013-03-191-54/+80
| | | | | | | | | | | | | | | | To be able to gate unused prcmu clocks from the clk_disable_unused sequence, clk-prcmu now implements the is_prepared callback. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: Introduce optional unprepare_unused callbackUlf Hansson2013-03-191-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | An unprepare_unused callback is introduced due to the same reasons to why the disable_unused callback was added. During the clk_disable_unused sequence, those clk_hw that needs specific treatment with regards to being unprepared, shall implement the unprepare_unused callback. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: Unprepare the unused prepared slow clocks at late initUlf Hansson2013-03-191-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The unused ungated fast clocks are already being disabled from clk_disable_unused at late init. This patch extend this sequence to the slow unused prepared clocks to be unprepared. Unless the optional .is_prepared callback is implemented by a clk_hw the clk_disable_unused sequence will not unprepare any unused clocks, since it will fall back to use the software prepare counter. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed hlist accessors per b67bfe0d]
| * clk: Introduce optional is_prepared callbackUlf Hansson2013-03-191-0/+21
| | | | | | | | | | | | | | | | | | | | To reflect whether a clk_hw is prepared the clk_hw may implement the optional is_prepared callback. If not implemented we fall back to use the software prepare counter. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: mxs: Fix sparse warningsFabio Estevam2013-03-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warnings: drivers/clk/mxs/clk.c:17:1: warning: symbol 'mxs_lock' was not declared. Should it be static? drivers/clk/mxs/clk.c:19:5: warning: symbol 'mxs_clk_wait' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | Merge branch 'for-3.10/soc' into for-3.10/clkStephen Warren2013-04-041-34/+2
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| * | clk: tegra: No 7.1 super clk dividers on Tegra20Peter De Schrijver2013-03-111-34/+2
| | | | | | | | | | | | | | | | | | | | | | | | Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk. Remove the clocks related to the divider. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | clk: vt8500: Fix "fix device clock divisor calculations"Arnd Bergmann2013-03-141-1/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | Patch 72480014b8 "Fix device clock divisor calculations" was apparently rebased incorrectly before it got upstream, causing a build error. Replacing the "prate" pointer with the local parent_rate is most likely the correct solution. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Tony Prisk <linux@prisktech.co.nz> Cc: Mike Turquette <mturquette@linaro.org>
* | clk: Tegra: Remove duplicate smp_twd clockPrashant Gaikwad2013-03-042-2/+0
|/ | | | | | | | | Remove duplicate smp_twd clocks as these clocks are accessed using DT now. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* hlist: drop the node parameter from iteratorsSasha Levin2013-02-271-37/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I'm not sure why, but the hlist for each entry iterators were conceived list_for_each_entry(pos, head, member) The hlist ones were greedy and wanted an extra parameter: hlist_for_each_entry(tpos, pos, head, member) Why did they need an extra pos parameter? I'm not quite sure. Not only they don't really need it, it also prevents the iterator from looking exactly like the list iterator, which is unfortunate. Besides the semantic patch, there was some manual work required: - Fix up the actual hlist iterators in linux/list.h - Fix up the declaration of other iterators based on the hlist ones. - A very small amount of places were using the 'node' parameter, this was modified to use 'obj->member' instead. - Coccinelle didn't handle the hlist_for_each_entry_safe iterator properly, so those had to be fixed up manually. The semantic patch which is mostly the work of Peter Senna Tschudin is here: @@ iterator name hlist_for_each_entry, hlist_for_each_entry_continue, hlist_for_each_entry_from, hlist_for_each_entry_rcu, hlist_for_each_entry_rcu_bh, hlist_for_each_entry_continue_rcu_bh, for_each_busy_worker, ax25_uid_for_each, ax25_for_each, inet_bind_bucket_for_each, sctp_for_each_hentry, sk_for_each, sk_for_each_rcu, sk_for_each_from, sk_for_each_safe, sk_for_each_bound, hlist_for_each_entry_safe, hlist_for_each_entry_continue_rcu, nr_neigh_for_each, nr_neigh_for_each_safe, nr_node_for_each, nr_node_for_each_safe, for_each_gfn_indirect_valid_sp, for_each_gfn_sp, for_each_host; type T; expression a,c,d,e; identifier b; statement S; @@ -T b; <+... when != b ( hlist_for_each_entry(a, - b, c, d) S | hlist_for_each_entry_continue(a, - b, c) S | hlist_for_each_entry_from(a, - b, c) S | hlist_for_each_entry_rcu(a, - b, c, d) S | hlist_for_each_entry_rcu_bh(a, - b, c, d) S | hlist_for_each_entry_continue_rcu_bh(a, - b, c) S | for_each_busy_worker(a, c, - b, d) S | ax25_uid_for_each(a, - b, c) S | ax25_for_each(a, - b, c) S | inet_bind_bucket_for_each(a, - b, c) S | sctp_for_each_hentry(a, - b, c) S | sk_for_each(a, - b, c) S | sk_for_each_rcu(a, - b, c) S | sk_for_each_from -(a, b) +(a) S + sk_for_each_from(a) S | sk_for_each_safe(a, - b, c, d) S | sk_for_each_bound(a, - b, c) S | hlist_for_each_entry_safe(a, - b, c, d, e) S | hlist_for_each_entry_continue_rcu(a, - b, c) S | nr_neigh_for_each(a, - b, c) S | nr_neigh_for_each_safe(a, - b, c, d) S | nr_node_for_each(a, - b, c) S | nr_node_for_each_safe(a, - b, c, d) S | - for_each_gfn_sp(a, c, d, b) S + for_each_gfn_sp(a, c, d) S | - for_each_gfn_indirect_valid_sp(a, c, d, b) S + for_each_gfn_indirect_valid_sp(a, c, d) S | for_each_host(a, - b, c) S | for_each_host_safe(a, - b, c, d) S | for_each_mesh_entry(a, - b, c, d) S ) ...+> [akpm@linux-foundation.org: drop bogus change from net/ipv4/raw.c] [akpm@linux-foundation.org: drop bogus hunk from net/ipv6/raw.c] [akpm@linux-foundation.org: checkpatch fixes] [akpm@linux-foundation.org: fix warnings] [akpm@linux-foudnation.org: redo intrusive kvm changes] Tested-by: Peter Senna Tschudin <peter.senna@gmail.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Signed-off-by: Sasha Levin <sasha.levin@oracle.com> Cc: Wu Fengguang <fengguang.wu@intel.com> Cc: Marcelo Tosatti <mtosatti@redhat.com> Cc: Gleb Natapov <gleb@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2013-02-213-31/+56
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM SoC device tree conversions from Arnd Bergmann: "These are device tree conversions for a number of platforms, with the intention of turning code from board files into device tree descriptions. Notable changes are: - davinci bindings for pinctrl, MTD, RTC, watchdog and i2c - nomadik bindings for all devices, removing the board files - bcm2835 bindings for mmc and i2c - tegra bindings for hdmi, keyboard, audio, as well as some updates - at91 bindings for hardware ecc and for devices on RM9200 - mxs bindings for cfa100xx - sunxi support for Miniand Hackberry board" * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (72 commits) Revert "sunxi: a10-cubieboard: Add user LEDs to the device tree" Revert "sunxi: a13-olinuxino: Add user LED to the device tree" clk: tegra: initialise parent of uart clocks ARM: tegra: remove clock-frequency properties from serial nodes clk: tegra: fix driver to match DT binding clk: tegra: local arrays should be static clk: tegra: Add missing spinlock for hclk and pclk clk: tegra: Implement locking for super clock clk: tegra: fix wrong clock index between se to sata_cold sunxi: a13-olinuxino: Add user LED to the device tree ARM: davinci: da850 DT: add support for machine reboot ARM: davinci: da850: add wdt DT node ARM: davinci: da850: add DT node for I2C0 ARM: at91: at91sam9n12: add DT parameters to enable PMECC ARM: at91: at91sam9x5: add DT parameters to enable PMECC ARM: at91: add EMAC bindings to RM9200 DT ARM: at91: add SSC bindings to RM9200 DT ARM: at91: add MMC bindings to RM9200 DT ARM: at91: Animeo IP: enable watchdog support ARM: nomadik: fix OF compilation regression ...
| * Merge tag 'tegra-for-3.9-soc-ccf-fixes' of ↵Arnd Bergmann2013-02-193-31/+56
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt ARM: tegra: common clock framework fixes A number of small fixes are included to the new Tegra common clock driver. These are: Missing locking, definition of device tree clock IDs not matching the binding, a static cleanup, missing initialization of some UART clocks. This branch is based on Tegra's previous pull request tegra-for-3.9-dt. This dependency is caused by the one patch that edits the device tree. If this causes a problem, I can drop the final two patches in this pull request for now, and rebase it onto previous tegra-for-3.9-soc-ccf instead. * tag 'tegra-for-3.9-soc-ccf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: clk: tegra: initialise parent of uart clocks ARM: tegra: remove clock-frequency properties from serial nodes clk: tegra: fix driver to match DT binding clk: tegra: local arrays should be static clk: tegra: Add missing spinlock for hclk and pclk clk: tegra: Implement locking for super clock clk: tegra: fix wrong clock index between se to sata_cold (applied to next/dt branch rather than next/soc because of the dependency) Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * clk: tegra: initialise parent of uart clocksLaxman Dewangan2013-02-132-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Initialise the parent of UARTs to PLLP and disabling clock by default. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * clk: tegra: fix driver to match DT bindingStephen Warren2013-02-132-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enum tegra*_clk is intended to match the IDs listed in the Tegra clock bindings. There are a few mismatches, which this patch fixes: 1) pll_s and cop were left out of the Tegra20 enum. 2) spdif_in and spdif_out were swapped relative to the Tegra30 binding. 3) i2cslow was misnamed as i2c_slow, and a duplicate i2cslow clock added to the Tegra30 enum. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
| | * clk: tegra: local arrays should be staticPeter De Schrijver2013-02-121-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cclk_g_parents, cclk_lp_parents and sclk_parents are only accessed from within clk-tegra30.c. Declare them static to avoid namespace polution. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * clk: tegra: Add missing spinlock for hclk and pclkPeter De Schrijver2013-02-122-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hclk and pclk clocks are controlled by the same register. Hence a lock is required to avoid corruption. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * clk: tegra: Implement locking for super clockPeter De Schrijver2013-02-121-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although tegra_clk_register_super_mux() has a lock parameter, the lock is not actually used by the code. Fixed with this patch. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * clk: tegra: fix wrong clock index between se to sata_coldJoseph Lo2013-02-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The index of se should be 127. And the previous clock index was 125. So we need to set up the index for se to get the correct index between se to sata_cold. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2013-02-2115-1/+5542
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM SoC-specific updates from Arnd Bergmann: "This is a larger set of new functionality for the existing SoC families, including: - vt8500 gains support for new CPU cores, notably the Cortex-A9 based wm8850 - prima2 gains support for the "marco" SoC family, its SMP based cousin - tegra gains support for the new Tegra4 (Tegra114) family - socfpga now supports a newer version of the hardware including SMP - i.mx31 and bcm2835 are now using DT probing for their clocks - lots of updates for sh-mobile - OMAP updates for clocks, power management and USB - i.mx6q and tegra now support cpuidle - kirkwood now supports PCIe hot plugging - tegra clock support is updated - tegra USB PHY probing gets implemented diffently" * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits) ARM: prima2: remove duplicate v7_invalidate_l1 ARM: shmobile: r8a7779: Correct TMU clock support again ARM: prima2: fix __init section for cpu hotplug ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3) ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3) arm: socfpga: Add SMP support for actual socfpga harware arm: Add v7_invalidate_l1 to cache-v7.S arm: socfpga: Add entries to enable make dtbs socfpga arm: socfpga: Add new device tree source for actual socfpga HW ARM: tegra: sort Kconfig selects for Tegra114 ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114 ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC ARM: tegra: Fix build error for gic update ARM: tegra: remove empty tegra_smp_init_cpus() ARM: shmobile: Register ARM architected timer ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move ARM: shmobile: r8a7779: Correct TMU clock support ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles ARM: mxs: use apbx bus clock to drive the timers on timrotv2 ...
| * \ \ Merge tag 'mxs-soc-3.9' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Olof Johansson2013-02-091-1/+1
| |\ \ \ | | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/soc From Shawn Guo: mxs soc changes for 3.9 - A couple of optimization on timer - Some updates on mxs_defconfig * tag 'mxs-soc-3.9' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles ARM: mxs: use apbx bus clock to drive the timers on timrotv2 ARM: mxs: Update mxs_defconfig
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