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path: root/drivers/clk/tegra
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2017-11-1713-66/+102
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| * clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Nicolin Chen2017-11-011-2/+2
| * clk: tegra: dfll: Fix drvdata overwriting issueNicolin Chen2017-11-013-13/+11
| * clk: tegra: Fix cclk_lp divisor registerMichał Mirosław2017-11-011-1/+1
| * clk: tegra: Bump SCLK clock rate to 216 MHzDmitry Osipenko2017-11-011-1/+1
| * clk: tegra: Use common definition of APBDMA clock gateDmitry Osipenko2017-11-011-5/+1
| * clk: tegra: Correct parent of the APBDMA clockDmitry Osipenko2017-11-011-1/+1
| * clk: tegra: Add AHB DMA clock entryDmitry Osipenko2017-11-014-0/+4
| * clk: tegra: Mark APB clock as criticalJon Hunter2017-11-011-1/+1
| * clk: tegra: Make tegra_clk_pll_params __ro_after_initBhumika Goyal2017-10-191-8/+8
| * clk: tegra: Fix sor1_out clock implementationThierry Reding2017-10-192-16/+47
| * clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding2017-10-194-13/+4
| * clk: tegra: Add peripheral clock registration helperThierry Reding2017-10-192-0/+11
| * clk: tegra: Check BPMP response return codeTimo Alho2017-10-191-5/+10
* | License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-022-0/+2
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* clk: tegra: Fix Tegra210 PLLU initializationAlex Frid2017-08-231-2/+4
* clk: tegra: Correct Tegra210 UTMIPLL poweron delayAlex Frid2017-08-231-3/+3
* clk: tegra: Fix T210 PLLRE registrationAlex Frid2017-08-231-20/+1
* clk: tegra: Update T210 PLLSS (D2/DP) registrationAlex Frid2017-08-231-39/+9
* clk: tegra: Re-factor T210 PLLX registrationAlex Frid2017-08-234-49/+10
* clk: tegra: don't warn for pll_d2 defaults unnecessarilyPeter De Schrijver2017-08-231-2/+4
* clk: tegra: change post IDDQ release delay to 5usPeter De Schrijver2017-08-231-1/+1
* clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2CAlex Frid2017-08-231-1/+2
* clk: tegra: Fix T210 effective NDIV calculationAlex Frid2017-08-231-4/+5
* clk: tegra: Init cfg structure in _get_pll_mnpPeter De Schrijver2017-08-231-0/+2
* clk: tegra210: remove non-existing VFIR clockPeter De Schrijver2017-08-231-1/+0
* clk: tegra: disable SSC for PLL_D2Peter De Schrijver2017-08-231-1/+1
* clk: tegra: Enable PLL_SS for Tegra210Peter De Schrijver2017-08-231-1/+1
* clk: tegra: fix SS control on PLL enable/disablePeter De Schrijver2017-08-231-20/+24
* clk: Convert to using %pOF instead of full_nameRob Herring2017-07-211-7/+5
* clk: tegra: Don't reset PLL-CX if it is already enabledJon Hunter2017-04-041-4/+4
* clk: tegra: Add missing Tegra210 clocksPeter De Schrijver2017-04-043-0/+19
* clk: tegra: Propagate clk_out_x rate to parentAlex Frid2017-04-041-2/+4
* clk: tegra: Fix build warnings on Tegra20/Tegra30Thierry Reding2017-03-202-2/+2
* clk: tegra: Mark TEGRA210_CLK_DBGAPB as always onPeter De Schrijver2017-03-201-0/+2
* clk: tegra: Add SATA seq input controlPeter De Schrijver2017-03-201-0/+25
* clk: tegra: Add Tegra210 special resetsPeter De Schrijver2017-03-201-0/+85
* clk: tegra: Rework pll_uPeter De Schrijver2017-03-202-197/+272
* clk: tegra: Implement reset control resetMikko Perttunen2017-03-201-0/+16
* clk: tegra: Fix disable unused for clocks sharing enable bitPeter De Schrijver2017-03-201-0/+3
* clk: tegra: Handle UTMIPLL IDDQPeter De Schrijver2017-03-201-0/+26
* clk: tegra: Add aclkPeter De Schrijver2017-03-201-0/+10
* clk: tegra: Add super clock mux/dividerPeter De Schrijver2017-03-202-5/+89
* clk: tegra: Define Tegra210 DMIC clocksPeter De Schrijver2017-03-203-1/+28
* clk: tegra: Fix constness for peripheral clocksPeter De Schrijver2017-03-202-4/+4
* clk: tegra: Define Tegra210 DMIC sync clocksPeter De Schrijver2017-03-203-24/+73
* clk: tegra: Add CEC clockPeter De Schrijver2017-03-206-0/+6
* clk: tegra: Fix type for m fieldPeter De Schrijver2017-03-201-1/+1
* clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculationPeter De Schrijver2017-03-201-1/+7
* clk: tegra: Don't warn for PLL defaults unnecessarilyPeter De Schrijver2017-03-201-6/+12
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