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path: root/drivers/clk/tegra/clk-tegra114.c
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* clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter2018-12-141-1/+8
| | | | | | | | | | | | | | | | | | The maximum frequency supported for I2S on Tegra124 and Tegra210 is 24.576MHz (as stated in the Tegra TK1 data sheet for Tegra124 and the Jetson TX1 module data sheet for Tegra210). However, the maximum I2S frequency is limited to 24MHz because that is the maximum frequency of the audio sync clock. Increase the maximum audio sync clock frequency to 24.576MHz for Tegra124 and Tegra210 in order to support 24.576MHz for I2S. Update the tegra_clk_register_sync_source() function so that it does not set the initial rate for the sync clocks and use the clock init tables to set the initial rate instead. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko2018-05-181-1/+1
| | | | | | | | | | | | | CDEV1 and CDEV2 clocks are a bit special case, their parent clock is created by the pinctrl driver. It should be possible for clk user to request these clocks before pinctrl driver got probed and hence user will get an orphaned clock. That might be undesirable because user may expect parent clock to be enabled by the child, so let's return -EPROBE_DEFER till parent clock appears. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Specify VDE clock rateDmitry Osipenko2018-03-121-0/+1
| | | | | | | | | | Currently VDE clock rate is determined by clock config left from bootloader, let's not rely on it and explicitly specify the clock rate in the CCF driver. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko2018-03-121-2/+1
| | | | | | | | | | Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks as critical. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: <stable@vger.kernel.org> # v4.16 Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding2017-10-191-3/+1
| | | | | | | | Instead of open-coding the same pattern repeatedly, reuse the newly introduced tegra_clk_register_periph_data() helper that will unpack the initialization structure. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Add CEC clockPeter De Schrijver2017-03-201-0/+1
| | | | | | | | | This clock is used to clock the HDMI CEC interface. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2Vince Hsu2016-08-241-2/+2
| | | | | | | | | | | | | | Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when the DIS power domain is during up-powergating process but the clamp to this domain is not removed yet. That causes a timeout and aborts the power sequence, although the PLLD/PLLD2 has already locked. To remove the false alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the clocks as locked. Signed-off-by: Vince Hsu <vinceh@nvidia.com> Tested-by: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker2016-06-301-154/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the UTMI PLL initialization code form clk-tegra<chip>.c files into clk-pll.c. UTMI PLL was being configured and set in HW control right after registration. However, when the clock init_table is processed and child clks of PLLU are enabled, it will call in and enable PLLU as well, and initiate SW enabling sequence even though PLLU is already in HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status. Doing the initialization once during pllu_enable means we configure it properly into HW control. A side effect of the commonization/localization of the UTMI PLL init code, is that it corrects some errors that were present for earlier generations. For instance, in clk-tegra124.c, it used to have: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) when the correct shift to use is present in the new version: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) which matches the Tegra124 TRM register definition. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> [rklein: Merged in some later fixes for potential deadlocks] Signed-off-by: Rhyland Klein <rklein@nvidia.com> [treding: coding style bike-shedding, remove unused variable] Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Special-case mipi-cal parent on Tegra114Thierry Reding2016-04-281-1/+5
| | | | | | | | Starting with Tegra124, the mipi-cal clock uses the 72 MHz clock as its source. On Tegra114 this clock's parent was clk_m, so it is the one-off chip. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Remove CLK_IS_ROOTStephen Boyd2016-03-021-2/+1
| | | | | | | | This flag is a no-op now. Remove usage of the flag. Acked-by: Rhyland Klein <rklein@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: pll: Update PLLM handlingDanny Huang2015-11-201-1/+2
| | | | | | | | | | | | | | | | | | | | | PLLM is fixed for Tegra30 up through Tegra114. Starting with Tegra124 PLLM can change rate. Mark PLLM as TEGRA_PLL_FIXED for the generations where it should be. Modify the check in clk_pll_round_rate() and clk_pll_recalc_rate() to allow for the non-fixed version to return the correct rate. Note that there is no change for Tegra20. This is because PLLM is not distinguished in that driver, and adding either the PLLM or FIXED_RATE flags will cause potential problems. PLLM never supported dynamic ramping. On Tegra20 and Tegra30, there is no dynamic ramping at all, and on Tegra114, Tegra124 and Tegra132, only PLLX and PLLC support dynamic ramping, so we can go ahead and remove the specialized pllm_ops. Signed-off-by: Danny Huang <dahuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein2015-11-201-51/+71
| | | | | | | | | | | | | | | | | | This removes the conversion from pdiv to hw, which is already taken care of by _get_table_rate before this code is run. This avoids incorrectly converting pdiv to hw twice and getting the wrong hw value. Also set the input_rate in the freq cfg in _calc_dynamic_ramp_rate while setting all the other fields. In order to prevent regressions on earlier SoC generations, all of the frequency tables need to be updated so that they contain the actual divider values. If they contain hardware values these would be converted to hardware values again, yielding the wrong value. Signed-off-by: Rhyland Klein <rklein@nvidia.com> [treding@nvidia.com: fix regressions on earlier SoC generations] Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein2015-11-201-10/+13
| | | | | | | | | | | | SoC specific drivers should define the appropriate flags for each PLL rather than relying on the registration functions to automatically set flags on their behalf. This will properly allow for changes between SoC generations where flags might be different and allow sharing the same logic functions. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Constify pdiv-to-hw mappingsThierry Reding2015-11-201-4/+4
| | | | | | This is static data that is never modified, so make it const. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Format tables consistentlyThierry Reding2015-11-181-136/+137
| | | | | | | Use spaces around { and } and pad values so that the cells are properly aligned. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Miscellaneous coding style cleanupsThierry Reding2015-11-181-6/+6
| | | | | | | | | Use unsigned int for loop variables that can never become negative and remove a couple of gratuitous blank lines. Also use single spaces around operators and use a single space instead of a tab to separate comments from code. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Fix 26 MHz oscillator frequencyThierry Reding2015-11-181-1/+1
| | | | | | | | | The OSC_FREQ field of the OSC_CTRL register uses the value 12 for an oscillator frequency of 26 MHz, not 260 MHz. This isn't really critical because I don't think boards with such an oscillator have ever existed, much less been supported upstream. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein2015-10-201-1/+7
| | | | | | | | | | | tegra_audio_clk_init was written expecting a single PLL to be passed in directly. Change this to accept an array which will allow for supporting multiple plls and specifying specific data about them, like their parent, which may change over time. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Properly include clk.hStephen Boyd2015-07-201-2/+0
| | | | | | | | | | | Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h in files that are using it. Also add in a clkdev.h include that was missing in a file using clkdev APIs. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: Use generic tegra_osc_clk_init() on Tegra114Thierry Reding2015-04-101-31/+3
| | | | | | | | | There is no reason why Tegra114 cannot use the same generic code to set up the oscillator, clk_m and pll_ref clocks. The only effective change that this causes is that the CLK_SET_PARENT_RATE flag is dropped, but since these clocks are all fixed it is not needed anyway. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Various whitespace cleanupsThierry Reding2015-04-101-1/+1
| | | | | | Make usage of blank lines as separators more consistent. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang2015-02-021-2/+8
| | | | | | | | | | | | | PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock. So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
* clk: tegra: Implement memory-controller clockThierry Reding2014-11-261-1/+6
| | | | | | | | | The memory controller clock runs either at half or the same frequency as the EMC clock. Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: fix vi_sensor clocks on Tegra124Peter De Schrijver2014-06-251-1/+30
| | | | | | | | vi_sensor and vi_sensor2 have a wrong hw clkid on Tegra124. Fix this by correcting the hw clkid for Tegra124 and creating the Tegra114 vi_sensor clock from its own data. Tegra124 was also using the wrong internal clock id. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: Initialize xusb clocksAndrew Bresticker2014-05-221-1/+6
| | | | | | | | | Initialize the XUSB-related clocks with appropriate parents and rates for both Tegra114 and Tegra124. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker2014-05-221-10/+5
| | | | | | | | | | | Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker2014-02-171-4/+4
| | | | | | | | The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with 6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114 and Tegra124 to use these clocks instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
* clk: tegra: implement a reset driverStephen Warren2013-12-111-1/+2
| | | | | | | | | | | | | The Tegra CAR module implements both a clock and reset controller. So far, the driver exposes the clock feature via the common clock API and the reset feature using a custom API. This patch adds an implementation of the common reset framework API (include/linux/reset*.h). The legacy reset implementation will be removed once all drivers have been converted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: Initialize DSI low-power clocksThierry Reding2013-11-261-0/+2
| | | | | | | | The low-power DSI clocks are used during host-driven transactions on the DSI bus. Documentation recommends that they be children of PLLP and run at a frequency of at least 52 MHz. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: add FUSE clock deviceAlexandre Courbot2013-11-261-0/+1
| | | | | | | This clock is needed to ensure the FUSE registers can be accessed without freezing the system. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* clk: tegra114: Initialize clocks needed for HDMIMikko Perttunen2013-11-261-0/+2
| | | | | | | | Add disp1 and disp2 clocks to the clock initialization table. These clocks are required for display and HDMI support. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: introduce common gen4 super clockPeter De Schrijver2013-11-261-74/+2
| | | | | | | Introduce a common function which performs super clock initialization for Tegra114 and beyond. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: move PMC, fixed clocks to common filesPeter De Schrijver2013-11-261-74/+1
| | | | | | | Introduce new files for fixed and PMC clocks common between several Tegra SoCs and move Tegra114 to this new infrastructure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: move periph clocks to common filePeter De Schrijver2013-11-261-574/+17
| | | | | | | | Introduce a new file for peripheral clocks common between several Tegra SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT clocks will be initialized here. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: move audio clk to common filePeter De Schrijver2013-11-261-208/+182
| | | | | | | | | Move audio clocks and PLLA initialization to a common file so it can be used by multiple Tegra SoCs. Also a new array tegra114_clks is introduced for Tegra114 which specifies which common clocks are available on Tegra114 and what their DT IDs are. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: add clkdev registration infraPeter De Schrijver2013-11-261-159/+163
| | | | | | | Add a common infra for registering clkdev. This allows decoupling clk registration from clkdev registration. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver2013-11-261-31/+43
| | | | | | | Move some fields related to the PLL HW description to the tegra_clk_pll_params. This allows some PLL code to be moved to common files later. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: use pll_ref as the pll_e parentPeter De Schrijver2013-11-261-1/+2
| | | | | | | | | Use pll_ref instead of pll_re_vco as the pll_e parent on Tegra114. Also add a 12Mhz pll_ref table entry for pll_e for Tegra114. This prevents the system from crashing at bootup because of an unsupported pll_re_vco rate. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: move some PLLC and PLLXC init to clk-pll.cPeter De Schrijver2013-11-261-89/+20
| | | | | | | | VCO min clipping, dynamic ramp setup and IDDQ init can be done in the respective PLL clk_register functions if the parent is already registered. This is done for other some PLLs already. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver2013-11-261-41/+16
| | | | | | | | | | This patch makes periph_clk_enb_refcnt a global array, dynamically allocated at boottime. It simplifies the macros somewhat and allows clocks common to several Tegra SoCs to be defined in a separate files. Also the clks array becomes global and dynamically allocated which allows the DT registration to be moved to a generic funcion. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: simplify periph clock dataPeter De Schrijver2013-11-261-235/+141
| | | | | | | | | | This patch determines the register bank for clock enable/disable and reset based on the clock ID instead of hardcoding it in the tables describing the clocks. This results in less data to be maintained in the tables, making the code easier to understand. The full benefit of the change will be realized once also other clocktypes will be table based. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3dThierry Reding2013-11-261-4/+4
| | | | | | | | These clocks were named gr2d and gr3d on Tegra20 and Tegra30, so use the same names on Tegra114 for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Set the clk parent of host1x to pll_pAndrew Chew2013-11-261-0/+1
| | | | | | | | | | The power-on default parent for this clock is pll_m, which turns out to be wrong. Previously, bootloader reparented this clock. We'll do it in the kernel as well, so that there's one less thing that we depend on bootloader to initialize. Signed-off-by: Andrew Chew <achew@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
* clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clksPeter De Schrijver2013-11-261-24/+29
| | | | | | | Perform upwards rounding when calculating dividers for periph clks on Tegra30 and Tegra114. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2Mark Zhang2013-11-251-0/+3
| | | | | | | | | pll_m will be the parent of gr2d/gr3d if we don't do this. And because pll_m runs at a high rate so gr2d/gr3d will be unstable. So change the parent of them to pll_c2. Signed-off-by: Mark Zhang <markz@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: Fix vde/2d/3d clock src offsetMark Zhang2013-11-251-10/+3
| | | | | | | | | | | | | In Tegra114, vde/gr_2d/gr_3d have 3 bits for clock source selection. So change the clock init macro for these clocks from "TEGRA_INIT_DATA_INT" to "TEGRA_INIT_DATA_INT8". Besides, no one uses "TEGRA_INIT_DATA_INT" after this change, so remove this macro. Signed-off-by: Mark Zhang <markz@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: Correct sbc mux width & parentMark Zhang2013-11-251-6/+6
| | | | | | | | | Tegra114 sbc1-sbc6 have more possible parent clocks than Tegra30. So correct the parents and mux width for them. Signed-off-by: Mark Zhang <markz@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: replace enum tegra114_clk by binding headerPeter De Schrijver2013-11-251-233/+198
| | | | | | | As the clock IDs are now specified in a header file, we can use those definitions instead of maintaining an internal enum. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds2013-09-091-13/+25
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull clock framework changes from Michael Turquette: "The common clk framework changes for 3.12 are dominated by clock driver patches, both new drivers and fixes to existing. A high percentage of these are for Samsung platforms like Exynos. Core framework fixes and some new features like automagical clock re-parenting round out the patches" * tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits) clk: only call get_parent if there is one clk: samsung: exynos5250: Simplify registration of PLL rate tables clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clocksource: samsung_pwm_timer: Get clock from device tree ARM: dts: exynos4: Specify PWM clocks in PWM node pwm: samsung: Update DT bindings documentation to cover clocks clk: Move symbol export to proper location clk: fix new_parent dereference before null check clk: wm831x: Initialise wm831x pointer on init ...
| * clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan2013-08-191-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes being reparented during clk_set_rate. To avoid breaking existing platforms, all callers of clk_register_mux() are adjusted to pass the new flag. Platform maintainers are encouraged to remove the flag if they wish to allow mux reparenting on set_rate. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Chao Xie <xiechao.mail@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Andrew Chew <achew@nvidia.com> Cc: Doug Anderson <dianders@chromium.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Tomasz Figa <t.figa@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: spear-devel@list.st.com Cc: linux-tegra@vger.kernel.org Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> [tegra] Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi] Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq] Signed-off-by: Mike Turquette <mturquette@linaro.org>
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