blackbird-op-linux - Blackbird™ Linux sources for OpenPOWER

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc	Linus Torvalds	2012-12-14	1	-0/+1
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\| *	ARM: SPEAr1310: Move 1310 specific misc register into machine specific files	Vipul Kumar Samar	2012-11-26	1	-0/+1
* \|	CLK: SPEAr: Remove unused dummy apb_pclk	Vipul Kumar Samar	2012-11-21	4	-12/+0
* \|	CLK: SPEAr: Correct index scanning done for clock synths	Deepak Sikri	2012-11-21	1	-0/+3
* \|	CLK: SPEAr: Update clock rate table	Deepak Sikri	2012-11-21	4	-21/+89
* \|	CLK: SPEAr: Add missing clocks	Vipul Kumar Samar	2012-11-21	3	-0/+16
* \|	CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks	Vipul Kumar Samar	2012-11-21	5	-114/+133
* \|	CLK: SPEAr13xx: fix parent names of multiple clocks	Shiraz Hashim	2012-11-21	2	-4/+4
* \|	CLK: SPEAr13xx: Fix mux clock names	Shiraz Hashim	2012-11-21	2	-12/+12
* \|	CLK: SPEAr: Fix dev_id & con_id for multiple clocks	Rajeev Kumar	2012-11-21	4	-41/+49
* \|	clk: spear: Add stub functions for spear3[0\|1\|2]0_clk_init()	Axel Lin	2012-11-15	1	-0/+6
* \|	clk: SPEAr: Vco-pll: Fix compilation warning	Viresh Kumar	2012-10-29	1	-1/+1
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*	Clk: SPEAr1340: Update sys clock parent array	Vipul Kumar Samar	2012-07-18	1	-2/+2
*	clk: SPEAr1340: Fix clk enable register for uart1 and i2c1.	Vipul Kumar Samar	2012-07-18	1	-2/+2
*	Clk:spear6xx:Fix: Rename clk ids within predefined limit	Vipul Kumar Samar	2012-07-18	1	-62/+60
*	Clk:spear3xx:Fix: Rename clk ids within predefined limit	Vipul Kumar Samar	2012-07-18	1	-94/+86
*	clk:spear1310:Fix: Rename clk ids within predefined limit	Vipul Kumar Samar	2012-07-18	1	-157/+155
*	clk:spear1340:Fix: Rename clk ids within predefined limit	Vipul Kumar Samar	2012-07-18	1	-138/+135
*	clk: SPEAr600: Fix ethernet clock name for DT based probing	Stefan Roese	2012-06-25	1	-1/+1
*	Viresh has moved	Viresh Kumar	2012-06-20	10	-10/+10
*	SPEAr13xx: Add common clock framework support	Viresh Kumar	2012-05-14	3	-0/+2072
*	SPEAr: Switch to common clock framework	Viresh Kumar	2012-05-12	3	-0/+957
*	SPEAr: clk: Add General Purpose Timer Synthesizer clock	Viresh Kumar	2012-05-12	3	-1/+172
*	SPEAr: clk: Add Fractional Synthesizer clock	Viresh Kumar	2012-05-12	3	-1/+182
*	SPEAr: clk: Add Auxiliary Synthesizer clock	Viresh Kumar	2012-05-12	3	-1/+242
*	SPEAr: clk: Add VCO-PLL Synthesizer clock	Viresh Kumar	2012-05-12	4	-0/+462