summaryrefslogtreecommitdiffstats
path: root/drivers/clk/samsung
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds2013-09-0911-508/+1702
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull clock framework changes from Michael Turquette: "The common clk framework changes for 3.12 are dominated by clock driver patches, both new drivers and fixes to existing. A high percentage of these are for Samsung platforms like Exynos. Core framework fixes and some new features like automagical clock re-parenting round out the patches" * tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits) clk: only call get_parent if there is one clk: samsung: exynos5250: Simplify registration of PLL rate tables clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clocksource: samsung_pwm_timer: Get clock from device tree ARM: dts: exynos4: Specify PWM clocks in PWM node pwm: samsung: Update DT bindings documentation to cover clocks clk: Move symbol export to proper location clk: fix new_parent dereference before null check clk: wm831x: Initialise wm831x pointer on init ...
| * clk: samsung: exynos5250: Simplify registration of PLL rate tablesTomasz Figa2013-09-061-10/+2
| | | | | | | | | | | | | | | | | | | | | | Since the _get_rate() helper has been modified to use __clk_lookup() internally, checking of PLL input rates can be done using it and so the registration code can be simplified. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Register PLL rate tables for Exynos4x12Tomasz Figa2013-09-061-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4x12 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Register PLL rate tables for Exynos4210Tomasz Figa2013-09-061-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4210 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Reorder registration of mout_vpllsrcTomasz Figa2013-09-061-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since PLL input frequency must be known before PLL registration, mout_vpllsrc clock which is a reference clock of VPLL must be registered before VPLL. This patch reorders clock registration to register mout_vpllsrc before VPLL. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: pll: Add support for rate configuration of PLL46xxTomasz Figa2013-09-062-1/+135
| | | | | | | | | | | | | | | | | | | | This patch implements round_rate and set_rate callbacks of PLL46xx driver to allow reconfiguration of PLL at runtime. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: pll: Use new registration method for PLL46xxTomasz Figa2013-09-063-65/+14
| | | | | | | | | | | | | | | | | | | | This patch modifies PLL46xx support code and its users to use the recently introduced common PLL registration helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: pll: Add support for rate configuration of PLL45xxTomasz Figa2013-09-062-1/+119
| | | | | | | | | | | | | | | | | | | | This patch implements round_rate and set_rate callbacks of PLL45xx driver to allow reconfiguration of PLL at runtime. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: pll: Use new registration method for PLL45xxTomasz Figa2013-09-063-62/+20
| | | | | | | | | | | | | | | | | | | | This patch modifies PLL45xx support code and its users to use the recently introduced common PLL registration helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_pllsTomasz Figa2013-09-061-3/+3
| | | | | | | | | | | | | | | | | | | | This array defines PLLs specific to Exynos 4x12 SoCs and not for all Exynos 4 SoCs, so the name should represent that. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Remove checks for DT nodeTomasz Figa2013-09-061-7/+4
| | | | | | | | | | | | | | | | | | | | Exynos 4 supports only DT based bootup, so non-DT cases does not need to be handled anymore. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Remove unused static clkdev aliasesTomasz Figa2013-09-061-184/+172
| | | | | | | | | | | | | | | | | | | | | | Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: Modify _get_rate() helper to use __clk_lookup()Tomasz Figa2013-09-063-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to use clkdev inside the clock driver to retrieve the clocks for internal use. Instead __clk_lookup() helper can be used to look up clocks by their platform name. This patch modifies the behavior of _get_rate() helper to look up clocks by platform name and adjusts all users of it to pass platform names instead of clkdev aliases. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Use separate aliases for cpufreq related clocksTomasz Figa2013-09-061-8/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos cpufreq driver is the only remaining piece of code that needs static clkdev aliases for operation, because it can not do device tree based clock lookups yet. This patch moves clock alias definitions for those clocks to separate arrays that can be used with samsung_clk_register_alias() helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: assign dout_pixel id to pixel clock dividerRahul Sharma2013-08-291-1/+4
| | | | | | | | | | | | | | | | | | | | dout_pixel is a new ID allocated for pixel clock divider. It is queried in the driver to pass as the parent to hdmi clock while switching between parents. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: add hdmi mux to change parents in hdmi driverRahul Sharma2013-08-291-1/+4
| | | | | | | | | | | | | | | | | | | | | | hdmi driver needs to change the parent of hdmi clock to pixel clock or hdmiphy clock, based on the stability of hdmiphy. This patch is exposing the mux for changing the parent. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: fix the order of parents of hdmi muxRahul Sharma2013-08-291-1/+1
| | | | | | | | | | | | | | | | | | Listing sclk_hdmiphy at 0th position in the list of parents is causing wrong configuration in reg SRC_DISP10. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: add gate clock for mixer sysmmuRahul Sharma2013-08-291-1/+2
| | | | | | | | | | | | | | | | Adding sysmmu clock for mixer for exynos5420. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: add sclk_hdmiphy to the list of special clocksRahul Sharma2013-08-291-2/+2
| | | | | | | | | | | | | | | | | | Add sclk_hdmiphy to the list of exposed clocks. This is required by hdmi driver to change the parent of hdmi clock. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystemRahul Sharma2013-08-281-2/+2
| | | | | | | | | | | | | | | | | | parent of hdmi and mixer block is mentioned as aclk200 which is not correct. It is clocked by the ouput of aclk200_disp1. Hence parent for mixer and hdmi clocks is changed to aclk200_disp1. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: s3c64xx: Fix incorrect placement of __initdataSachin Kamat2013-08-271-2/+2
| | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * Merge branch 'clk-next-s3c64xx-delta' into clk-nextMike Turquette2013-08-272-98/+13
| |\
| | * clk: samsung: pll: Use new registration method for PLL6552 and PLL6553Tomasz Figa2013-08-262-98/+13
| | | | | | | | | | | | | | | | | | | | | | | | This patch modifies PLL6552 and PLL6553 clock drivers to use recently added common Samsung PLL registration method. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan2013-08-192-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes being reparented during clk_set_rate. To avoid breaking existing platforms, all callers of clk_register_mux() are adjusted to pass the new flag. Platform maintainers are encouraged to remove the flag if they wish to allow mux reparenting on set_rate. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Chao Xie <xiechao.mail@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Andrew Chew <achew@nvidia.com> Cc: Doug Anderson <dianders@chromium.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Tomasz Figa <t.figa@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: spear-devel@list.st.com Cc: linux-tegra@vger.kernel.org Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> [tegra] Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi] Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq] Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: exynos5440: Fix incorrect placement of __initdataSachin Kamat2013-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: exynos5420: Fix incorrect placement of __initdataSachin Kamat2013-08-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: exynos5250: Fix incorrect placement of __initdataSachin Kamat2013-08-081-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: exynos4: Fix incorrect placement of __initdataSachin Kamat2013-08-081-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: exynos5420: Make exynos5420_plls staticSachin Kamat2013-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | 'exynos5420_plls' is used only in this file. Make is static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: exynos5250: Make exynos5250_plls staticSachin Kamat2013-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | exynos5250_plls is used only in this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: exynos4: Make exynos4_plls staticSachin Kamat2013-08-081-1/+1
| |/ | | | | | | | | | | | | 'exynos4_plls' is used only in this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * Merge branch 'clk-next-s3c64xx' into clk-nextMike Turquette2013-08-084-0/+640
| |\
| | * clk: samsung: Add clock driver for S3C64xx SoCsTomasz Figa2013-08-052-0/+476
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds new, Common Clock Framework-based clock driver for Samsung S3C64xx SoCs. The driver is just added, without actually letting the platforms use it yet, since this requires more intermediate steps. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| | * clk: samsung: pll: Add support for PLL6552 and PLL6553Tomasz Figa2013-08-052-0/+164
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for PLL6552 and PLL6553 PLLs present on Samsung S3C64xx SoCs. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoCVikas Sajjan2013-08-022-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | Adds the EPLL and VPLL freq table for exynos5250 SoC. Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: samsung: Reorder MUX registration for mout_vpllsrcVikas Sajjan2013-08-021-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the "fout_vpll" (child), we found get rate was failing. So this patch moves the mout_vpllsrc MUX out of the existing common list and registers the mout_vpllsrc MUX before the PLL registrations. Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: samsung: Add set_rate() clk_ops for PLL36xxVikas Sajjan2013-08-021-1/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds set_rate and round_rate clk_ops for PLL36xx Reviewed-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: samsung: Add set_rate() clk_ops for PLL35xxYadwinder Singh Brar2013-08-021-1/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add set_rate() and round_rate() for PLL35xx Reviewed-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: samsung: Add support to register rate_table for samsung pllsYadwinder Singh Brar2013-08-026-28/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch defines a common rate_table which will contain recommended p, m, s, k values for supported rates that needs to be changed for changing corresponding PLL's rate. Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: samsung: Remove unused pll registeration code for pll35xx and pll36xxYadwinder Singh Brar2013-08-022-74/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes samsung_clk_register_pll35xx() and samsung_clk_register_pll36xx() registaration functions as users migrated to new samsung_clk_register_pll(). Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: samsung: Migrate exynos5420 to use common samsung_clk_register_pll()Yadwinder Singh Brar2013-08-021-28/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch migrates exynos5420 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to unique id list of clocks. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: samsung: Migrate exynos4 to use common samsung_clk_register_pll()Yadwinder Singh Brar2013-08-021-14/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch migrates exynos4 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: samsung: Migrate exynos5250 to use common samsung_clk_register_pll()Yadwinder Singh Brar2013-08-021-19/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch migrates exynos5250 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to unique id list of clocks. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: samsung: Define a common samsung_clk_register_pll()Yadwinder Singh Brar2013-08-023-0/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch defines a common samsung_clk_register_pll() Since pll2550 & pll35xx and pll2650 & pll36xx have exactly same clk ops implementation, added pll2550 and pll2650 also. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: samsung: Introduce a common samsung_clk_pll structYadwinder Singh Brar2013-08-021-18/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch unifies clk strutures used for PLL35xx & PLL36xx and adding an extra member lock_reg, so that common code can be factored out. Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: exynos4: Add clock entries for TMUSachin Kamat2013-07-301-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Added clock entries for thermal management unit (TMU) for Exynos4 SoCs. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk/exynos5250: add sclk_hdmiphy in the list of special clocksRahul Sharma2013-07-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | hdmi driver needs hdmiphy clock which is one of the parent for hdmi mux clock. This is required while changing the parent of mux clock. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk/exynos5250: add mout_hdmi mux clock for hdmiRahul Sharma2013-07-301-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hdmi driver needs to change the parent of hdmi clock frequently between pixel clock and hdmiphy clock. hdmiphy is not stable after power on and for a short interval while changing the phy configuration. For this duration pixel clock is used to clock hdmi. This patch is exposing the mux for changing parent. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: exynos5250: Add G2D gate clockSachin Kamat2013-07-291-1/+4
| | | | | | | | | | | | | | | | | | | | | Adds gate clock for G2D IP for Exynos5250 SoC. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: exynos-audss: Staticize exynos_audss_clk_initSachin Kamat2013-07-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | exynos_audss_clk_init() is used only in this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
OpenPOWER on IntegriCloud