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path: root/drivers/clk/samsung
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* Merge branch 'clk-next-s3c64xx' into clk-nextMike Turquette2013-08-084-0/+640
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| * clk: samsung: Add clock driver for S3C64xx SoCsTomasz Figa2013-08-052-0/+476
| | | | | | | | | | | | | | | | | | This patch adds new, Common Clock Framework-based clock driver for Samsung S3C64xx SoCs. The driver is just added, without actually letting the platforms use it yet, since this requires more intermediate steps. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: pll: Add support for PLL6552 and PLL6553Tomasz Figa2013-08-052-0/+164
| | | | | | | | | | | | | | | | This patch adds support for PLL6552 and PLL6553 PLLs present on Samsung S3C64xx SoCs. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoCVikas Sajjan2013-08-022-0/+40
| | | | | | | | | | | | | | | | Adds the EPLL and VPLL freq table for exynos5250 SoC. Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: samsung: Reorder MUX registration for mout_vpllsrcVikas Sajjan2013-08-021-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the "fout_vpll" (child), we found get rate was failing. So this patch moves the mout_vpllsrc MUX out of the existing common list and registers the mout_vpllsrc MUX before the PLL registrations. Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: samsung: Add set_rate() clk_ops for PLL36xxVikas Sajjan2013-08-021-1/+78
| | | | | | | | | | | | | | | | | | This patch adds set_rate and round_rate clk_ops for PLL36xx Reviewed-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: samsung: Add set_rate() clk_ops for PLL35xxYadwinder Singh Brar2013-08-021-1/+104
| | | | | | | | | | | | | | | | | | This patch add set_rate() and round_rate() for PLL35xx Reviewed-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: samsung: Add support to register rate_table for samsung pllsYadwinder Singh Brar2013-08-026-28/+75
| | | | | | | | | | | | | | | | | | | | This patch defines a common rate_table which will contain recommended p, m, s, k values for supported rates that needs to be changed for changing corresponding PLL's rate. Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: samsung: Remove unused pll registeration code for pll35xx and pll36xxYadwinder Singh Brar2013-08-022-74/+0
| | | | | | | | | | | | | | | | | | This patch removes samsung_clk_register_pll35xx() and samsung_clk_register_pll36xx() registaration functions as users migrated to new samsung_clk_register_pll(). Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: samsung: Migrate exynos5420 to use common samsung_clk_register_pll()Yadwinder Singh Brar2013-08-021-28/+58
| | | | | | | | | | | | | | | | | | | | This patch migrates exynos5420 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to unique id list of clocks. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: samsung: Migrate exynos4 to use common samsung_clk_register_pll()Yadwinder Singh Brar2013-08-021-14/+26
| | | | | | | | | | | | | | | | | | This patch migrates exynos4 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: samsung: Migrate exynos5250 to use common samsung_clk_register_pll()Yadwinder Singh Brar2013-08-021-19/+41
| | | | | | | | | | | | | | | | | | | | This patch migrates exynos5250 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to unique id list of clocks. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: samsung: Define a common samsung_clk_register_pll()Yadwinder Singh Brar2013-08-023-0/+125
| | | | | | | | | | | | | | | | | | This patch defines a common samsung_clk_register_pll() Since pll2550 & pll35xx and pll2650 & pll36xx have exactly same clk ops implementation, added pll2550 and pll2650 also. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: samsung: Introduce a common samsung_clk_pll structYadwinder Singh Brar2013-08-021-18/+12
| | | | | | | | | | | | | | | | | | This patch unifies clk strutures used for PLL35xx & PLL36xx and adding an extra member lock_reg, so that common code can be factored out. Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: exynos4: Add clock entries for TMUSachin Kamat2013-07-301-1/+3
| | | | | | | | | | | | | | | | Added clock entries for thermal management unit (TMU) for Exynos4 SoCs. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk/exynos5250: add sclk_hdmiphy in the list of special clocksRahul Sharma2013-07-301-2/+2
| | | | | | | | | | | | | | | | | | hdmi driver needs hdmiphy clock which is one of the parent for hdmi mux clock. This is required while changing the parent of mux clock. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk/exynos5250: add mout_hdmi mux clock for hdmiRahul Sharma2013-07-301-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | hdmi driver needs to change the parent of hdmi clock frequently between pixel clock and hdmiphy clock. hdmiphy is not stable after power on and for a short interval while changing the phy configuration. For this duration pixel clock is used to clock hdmi. This patch is exposing the mux for changing parent. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: exynos5250: Add G2D gate clockSachin Kamat2013-07-291-1/+4
| | | | | | | | | | | | | | Adds gate clock for G2D IP for Exynos5250 SoC. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: exynos-audss: Staticize exynos_audss_clk_initSachin Kamat2013-07-251-1/+1
| | | | | | | | | | | | | | | | | | | | exynos_audss_clk_init() is used only in this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: exynos5440: Staticize local symbolsSachin Kamat2013-07-251-7/+7
| | | | | | | | | | | | | | | | | | Symbols referenced only in this file are made static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: exynos5420: Staticize local symbolsSachin Kamat2013-07-251-7/+7
| | | | | | | | | | | | | | | | | | Symbols referenced only in this file are made static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: exynos5250: Staticize local symbolsSachin Kamat2013-07-251-7/+7
| | | | | | | | | | | | | | | | | | Symbols referenced only in this file are made static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: exynos4: Remove unused functionSachin Kamat2013-07-251-14/+0
| | | | | | | | | | | | | | | | | | | | Subsequent to the cleanup in commit 3c70348c7c ("ARM: EXYNOS: Remove legacy timer initialization code"), this function has no more users. Hence remove it. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: exynos4: Staticize local symbolsSachin Kamat2013-07-251-13/+15
|/ | | | | | | | Symbols referenced only in this file are made static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds2013-07-032-10/+14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull clock framework updates from Mike Turquette: "The common clock framework changes for 3.11 include new clock drivers across several different platforms and architectures, fixes to existing drivers, a MAINTAINERS file fix and improvements to the basic clock types that allow them to be of use to more platforms than before. Only a few fixes to the core framework are included with most all of the changes landing in the various clock drivers themselves." * tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux: (55 commits) clk: tegra: fix ifdef for tegra_periph_reset_assert inline clk: tegra: provide tegra_periph_reset_assert alternative clk: exynos4: Fix clock aliases for cpufreq related clocks clk: samsung: Add MUX_FA macro to pass flag and alias clk: add support for Rockchip gate clocks clk: vexpress: Make the clock drivers directly available for arm64 clk: vexpress: Use full node name to identify individual clocks clk: tegra: T114: add DFLL DVCO reset control clk: tegra: T114: add DFLL source clocks clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL clk: gate: add CLK_GATE_HIWORD_MASK clk: divider: add CLK_DIVIDER_HIWORD_MASK flag clk: mux: add CLK_MUX_HIWORD_MASK clk: Always notify whole subtree when reparenting MAINTAINERS: make drivers/clk entry match subdirs clk: honor CLK_GET_RATE_NOCACHE in clk_set_rate clk: use clk_get_rate() for debugfs clk: tegra: Use override bits when needed clk: tegra: override bits for Tegra30 PLLM clk: tegra: override bits for Tegra114 PLLM ...
| * clk: exynos4: Fix clock aliases for cpufreq related clocksTushar Behera2013-06-221-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpufreq driver for EXYNOS4 based SoCs are not platform drivers, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. Clock alias modifications for EXYNOS4 specific clocks are as below. Alias for clock 'arm_clk' is 'armclk'. Alias for clock 'mout_apll' is 'mout_apll'. Alias for clock 'mout_core' is 'moutcore'. For EXYNOS4210, alias for clock 'sclk_mpll' is 'mout_mpll'. For EXYNOS4412, alias for clock 'mout_mpll_user_c' is 'mout_mpll'. Some of the clock aliases are newly defined and some are fixed up. While at it, also modify the debug messages to print the clock values appropriately. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: Add MUX_FA macro to pass flag and aliasTushar Behera2013-06-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Cpufreq driver for some Samsung platforms have not yet been designed as a platform driver, thereby they can only access clocks with an alias name. For EXYNOS4210, one such clock also requires a flag to be set, hence there is a need to create another macro that can handle both flag and alias. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clockTushar Behera2013-05-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 'mout_mpll' is added the list of parent clocks for 'mout_cpu'. 'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll' should be added to the list of parent clocks. This results in an error when cpufreq driver for EXYNOS5250 tries to set 'mout_mpll' as a parent for 'mout_cpu'. clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: exynos5250: Update cpufreq related clocks for EXYNOS5250Tushar Behera2013-05-291-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | Merge tag 'late-for-linus' of ↵Linus Torvalds2013-07-022-0/+763
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late changes from Arnd Bergmann: "These are changes that arrived a little late before the merge window or that have multiple dependencies on previous branches so they did not fit into one of the earlier ones. There are 10 branches merged here, a total of 39 non-merge commits. Contents are a mixed bag for the above reasons: * Two new SoC platforms: ST microelectronics stixxxx and the TI 'Nspire' graphing calculator. These should have been in the 'soc' branch but were a little late * Support for the Exynos 5420 variant in mach-exynos, which is based on the other exynos branches to avoid conflicts. * Various small changes for sh-mobile, ux500 and davinci * Common clk support for MSM" * tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits) ARM: ux500: bail out on alien cpus ARM: davinci: da850: adopt to pinctrl-single change for configuring multiple pins serial: sh-sci: Initialise variables before access in sci_set_termios() ARM: stih41x: Add B2020 board support ARM: stih41x: Add B2000 board support ARM: sti: Add DEBUG_LL console support ARM: sti: Add STiH416 SOC support ARM: sti: Add STiH415 SOC support ARM: msm: Migrate to common clock framework ARM: msm: Make proc_comm clock control into a platform driver ARM: msm: Prepare clk_get() users in mach-msm for clock-pcom driver ARM: msm: Remove clock-7x30.h include file ARM: msm: Remove custom clk_set_{max,min}_rate() API ARM: msm: Remove custom clk_set_flags() API msm: iommu: Use clk_set_rate() instead of clk_set_min_rate() msm: iommu: Convert to clk_prepare/unprepare msm_sdcc: Convert to clk_prepare/unprepare usb: otg: msm: Convert to clk_prepare/unprepare msm_serial: Use devm_clk_get() and properly return errors msm_serial: Convert to clk_prepare/unprepare ...
| * | clk: exynos5420: register clocks using common clock frameworkChander Kashyap2013-06-192-0/+763
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EXYNOS5420 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | Merge tag 'drivers-for-linus' of ↵Linus Torvalds2013-07-023-2/+137
|\ \ \ | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver specific changes from Arnd Bergmann: "These changes are all driver specific and cross over between arm-soc contents and some other subsystem, in these cases cpufreq, crypto, dma, pinctrl, mailbox and usb, and the subsystem owners agreed to have these changes merged through arm-soc. As we proceed to untangle the dependencies between platform code and driver code, the amount of changes in this category is fortunately shrinking, for 3.11 we have 16 branches here and 101 non-merge changesets, the majority of which are for the stedma40 dma engine driver used in the ux500 platform. Cleaning up that code touches multiple subsystems, but gets rid of the dependency in the end. The mailbox code moved out from mach-omap2 to drivers/mailbox is an intermediate step and is still omap specific at the moment. Patches exist to generalize the subsystem and add other drivers with the same API, but those did not make it for 3.11." * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits) crypto: ux500: use dmaengine_submit API crypto: ux500: use dmaengine_prep_slave_sg API crypto: ux500: use dmaengine_device_control API crypto: ux500/crypt: add missing __iomem qualifiers crypto: ux500/hash: add missing static qualifiers crypto: ux500/hash: use readl on iomem addresses dmaengine: ste_dma40: Declare memcpy config as static ARM: ux500: Remove mop500_snowball_ethernet_clock_enable() ARM: ux500: Correct the EN_3v3 regulator's on/off GPIO ARM: ux500: Provide a AB8500 GPIO Device Tree node gpio: rcar: fix gpio_rcar_of_table gpio-rcar: Remove #ifdef CONFIG_OF around OF-specific sections gpio-rcar: Reference core gpio documentation in the DT bindings clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2 ARM: dts: Update Samsung I2S documentation ARM: dts: add clock provider information for i2s controllers in Exynos5250 ARM: dts: add Exynos audio subsystem clock controller node clk: samsung: register audio subsystem clocks using common clock framework ARM: dts: use #include for all device trees for Samsung pinctrl: s3c24xx: use correct header for chained_irq functions ...
| * | clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2Padmavathi Venna2013-06-191-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds enum entries for div_i2s1 and div_i2s2 which are required for i2s1 and i2s2 controllers. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | clk: samsung: register audio subsystem clocks using common clock frameworkPadmavathi Venna2013-06-192-0/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Audio subsystem is introduced in s5pv210 and exynos platforms. This has seperate clock controller which can control i2s0 and pcm0 clocks. This patch registers the audio subsystem clocks with the common clock framework on Exynos family. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | Merge tag 'dt-for-linus' of ↵Linus Torvalds2013-07-021-2/+7
|\ \ \ | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree changes from Arnd Bergmann: "These changes from 30 individual branches for the most part update device tree files, but there are also a few source code changes that have crept in this time, usually in order to atomically move over a driver from using hardcoded data to DT probing. A number of platforms change their DT files to use the C preprocessor, which is causing a bit of churn, but that is hopefully only this once" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (372 commits) ARM: at91: dt: rm9200ek: add spi support ARM: at91: dt: rm9200: add spi support ARM: at91/DT: at91sam9n12: add SPI DMA client infos ARM: at91/DT: sama5d3: add SPI DMA client infos ARM: at91/DT: fix SPI compatibility string ARM: Kirkwood: Fix the internal register ranges translation ARM: dts: bcm281xx: change comment to C89 style ARM: mmc: bcm281xx SDHCI driver (dt mods) ARM: nomadik: add the new clocks to the device tree clk: nomadik: implement the Nomadik clocks properly ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency ARM: dts: omap4-panda: Fix DVI EDID reads ARM: dts: omap4-panda: Add USB Host support arm: mvebu: enable mini-PCIe connectors on Armada 370 RD ARM: shmobile: irqpin: add a DT property to enable masking on parent ARM: dts: AM43x EPOS EVM support ARM: dts: OMAP5: Add bandgap DT entry ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ...
| * | clk: exynos4: Add additional G2D clocksSachin Kamat2013-06-121-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D IP. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | clk: exynos5250: Add CLK_IGNORE_UNUSED flag for pmu clockTushar Behera2013-06-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently 'pmu' clock is not handled by any of the drivers. Also before the introduction of CCF, this clock was not defined, hence was left enabled always. When this clock is disabled, software reset register becomes inaccessible and system reboot doesn't work. Upon restoring the default behaviour, system reboot starts working. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properlyDoug Anderson2013-06-111-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The KDIV value is often listed as unsigned but it needs to be treated as a 16-bit signed value when using it in calculations. Fix our rate recalculation to do this correctly. Before doing this, I tried setting EPLL on exynos5250 to: rate, m, p, s, k = 80000000, 107, 2, 4, 43691 This rate is exactly from the table in the exynos5250 user manual. I read this back as 80750003 with: cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate After this patch, it reads back as 80000003 Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clockTushar Behera2013-06-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'mout_mpll' is added the list of parent clocks for 'mout_cpu'. 'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll' should be added to the list of parent clocks. This results in an error when cpufreq driver for EXYNOS5250 tries to set 'mout_mpll' as a parent for 'mout_cpu'. clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: exynos5250: Update cpufreq related clocks for EXYNOS5250Tushar Behera2013-06-101-3/+3
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: samsung: Add CLK_IGNORE_UNUSED flag for the sysreg clocksSylwester Nawrocki2013-05-291-2/+4
|/ | | | | | | | | | | | | | | | | | | | | Currently no driver *) handles the sysreg clock, with an assumption that this clock is always left in its default state (enabled). Before commit 6e6aac7590f902d14d90bace3fd499 ARM: EXYNOS: Migrate clock support to common clock framework the sysreg clock was not even defined and hence wasn't handled explicitly in the kernel. To restore the previous behaviour disable masking the sysreg clock off in the clock core by default. *) Except the Exynos4x12 FIMC-IS driver, which will be modified to not touch the sysreg clock. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Merge tag 'multiplatform-for-linus-2' of ↵Linus Torvalds2013-05-074-55/+42
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull late ARM Exynos multiplatform changes from Arnd Bergmann: "These continue the multiplatform support for exynos, adding support for building most of the essential drivers (clocksource, clk, irqchip) when combined with other platforms. As a result, it should become really easy to add full multiplatform exynos support in 3.11, although we don't yet enable it for 3.10. The changes were not included in the earlier multiplatform series in order to avoid clashes with the other Exynos updates. This also includes work from Tomasz Figa to fix the pwm clocksource code on Exynos, which is not strictly required for multiplatform, but related to the other patches in this set and needed as a bug fix for at least one board." * tag 'multiplatform-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits) ARM: dts: exynops4210: really add universal_c210 dts ARM: dts: exynos4210: Add basic dts file for universal_c210 board ARM: dts: exynos4: Add node for PWM device ARM: SAMSUNG: Do not register legacy timer interrupts on Exynos clocksource: samsung_pwm_timer: Work around rounding errors in clockevents core clocksource: samsung_pwm_timer: Correct programming of clock events clocksource: samsung_pwm_timer: Use proper clockevents max_delta clocksource: samsung_pwm_timer: Add support for non-DT platforms clocksource: samsung_pwm_timer: Drop unused samsung_pwm struct clocksource: samsung_pwm_timer: Keep all driver data in a structure clocksource: samsung_pwm_timer: Make PWM spinlock global clocksource: samsung_pwm_timer: Let platforms select the driver Documentation: Add device tree bindings for Samsung PWM timers clocksource: add samsung pwm timer driver irqchip: exynos: look up irq using irq_find_mapping irqchip: exynos: pass irq_base from platform irqchip: exynos: localize irq lookup for ATAGS irqchip: exynos: allocate combiner_data dynamically irqchip: exynos: pass max combiner number to combiner_init ARM: exynos: add missing properties for combiner IRQs ...
| * clk: exynos: prepare for multiplatformArnd Bergmann2013-04-194-55/+42
| | | | | | | | | | | | | | | | | | | | | | | | The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
* | clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}Tushar Behera2013-04-231-8/+8
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 688f7d8c9fef ("clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}") incorrectly sets the divider for sclk_mmc{0,1,2,3} to fix the wrong clock value. Though this fixed issue with Arndale, it created regressions for other boards like Snow. On Exynos5250, sclk_mmc<n> is generated like below (as per the clock names in drivers/clk/samsung/clk-exynos5250.c) mout_group1_p ==> mout_mmc<n> ==> div_mmc<n> ==> div_mmc_pre<n> => sclk_mmc<n> Earlier div_mmc<n> was set as the parent for sclk_mmc<n>, hence div_mmc_pre<n> was not getting referred in kernel code and depending on its value set during preboot, sclk_mmc<n> value was different for various boards. Setting the correct clock generation path should fix the issues reported in above referenced commit. The changes committed during the earlier patch has also been reverted here. Reported-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Tested-by: Doug Anderson <dianders@chromium.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}Tushar Behera2013-04-081-4/+4
| | | | | | | | | | | | | | | | | | In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide) instead of RATIO bit-field (4-bit wide) for dividing clock rate. With current common clock setup, we are using RATIO bit-field which is creating FIFO read errors while accessing eMMC. Changing over to use PRE_RATIO bit-field fixes this issue. dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020) mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0 end_request: I/O error, dev mmcblk0, sector 1 Signed-off-by: Tushar Behera <tushar.behera@linaro.org> CC: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: exynos4: export clocks required for fimc-isSylwester Nawrocki2013-04-081-7/+13
| | | | | | | | | | | | | | This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1, ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1, DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are available to the consumers (Exynos4x12 FIMC-IS subsystem). While at it, indentation of the mux clocks table is corrected. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: samsung: Fix compilation errorSachin Kamat2013-04-081-0/+2
| | | | | | | | | | Fixes the below compilation error during non-dt build. drivers/clk/samsung/clk.c: In function 'samsung_clk_of_register_fixed_ext': drivers/clk/samsung/clk.c:252:2: error: implicit declaration of function 'for_each_matching_node_and_match' [-Werror=implicit-function-declaration] drivers/clk/samsung/clk.c:252:60: error: expected ';' before '{' token Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: exynos5250: register display block gate clocks to common clock frameworkLeela Krishna Amudala2013-04-041-1/+9
| | | | | | | | Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi. Register it to common clock framework. Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: exynos4: Add support for SoC-specific register save listTomasz Figa2013-04-045-8/+39
| | | | | | | | | | | This patch extends suspend/resume support for SoC-specific registers to handle differences in register sets on particular SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: exynos4: Add missing registers to suspend save listTomasz Figa2013-04-041-0/+33
| | | | | | | | | | | This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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