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* Merge tag 'v4.8-rockchip-clk1' of ↵Stephen Boyd2016-07-012-52/+84
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: Placeholder for the rk3399 watchdog pclk, some newly exported rk3228 clockids and a small fix for the not yet used spdif to displayport clock on the rk3399. * tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits clk: rockchip: export rk3228 MAC clocks clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk clk: rockchip: export rk3228 audio clocks clk: rockchip: include rk3228 downstream muxes into fractional dividers clk: rockchip: fix incorrect rk3228 clock registers clk: rockchip: add clock-ids for rk3228 MAC clocks clk: rockchip: add clock-ids for rk3228 audio clocks clk: rockchip: add a dummy clock for the watchdog pclk on rk3399
| * clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bitsXing Zheng2016-07-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx, it should be bit_8, let's fix it. Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399") Reported-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Cc: stable@vger.kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: export rk3228 MAC clocksXing Zheng2016-07-011-11/+11
| | | | | | | | | | | | | | This patch exports related MAC clocks for dts reference. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclkXing Zheng2016-07-011-3/+3
| | | | | | | | | | | | | | | | The sclk_macphy_50m is confusing, the sclk_mac_extclk describes a external clock clearly. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: export rk3228 audio clocksXing Zheng2016-07-011-4/+4
| | | | | | | | | | | | | | This patch exports related i2s/spdif clocks for dts reference. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: include rk3228 downstream muxes into fractional dividersXing Zheng2016-07-011-29/+52
| | | | | | | | | | | | | | | | During the initial conversion to the newly introduced combined fractional dividers+muxes the rk3228 clocks were left out, so convert them now. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: fix incorrect rk3228 clock registersXing Zheng2016-06-221-9/+9
| | | | | | | | | | | | | | | | Due to copy and paste carelessly, RK3288_CLKxxx references are incorrect, we need to fix them. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: add a dummy clock for the watchdog pclk on rk3399Xing Zheng2016-05-301-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Like rk3288, the pclk supplying the watchdog is controlled via the SGRF register area. Additionally the SGRF isn't even writable in every boot mode. But still the clock control is available and in the future someone might want to use it. Therefore define a simple clock for the time being so that the watchdog driver can read its rate. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Reviewed-by: Stephen Barber <smbarber@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | clk: rockchip: release io resource when failing to init clk on rk3399Shawn Lin2016-06-031-0/+2
| | | | | | | | | | | | | | | | | | | | We should call iounmap to relase reg_base since it's not going to be used any more if failing to init clk. This was missing on the newly added rk3399 clock tree. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | clk: rockchip: fix cpuclk registration error handlingXing Zheng2016-05-301-2/+2
| | | | | | | | | | | | | | | | | | It maybe due to a copy-paste error the error handing should be cclk not clk when checking if the cpuclk registration succeeded. Reported-by: Lin Huang <lin.huang@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | clk: rockchip: Revert "clk: rockchip: reset init state before mmc card ↵Douglas Anderson2016-05-301-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | initialization" This reverts commit 7a03fe6f48f3 ("clk: rockchip: reset init state before mmc card initialization"). Though not totally obvious from the commit message nor from the source code, that commit appears to be trying to reset the "_drv" MMC clocks to 90 degrees (note that the "_sample" MMC clocks have a shift of 0 so are not touched). The major problem here is that it doesn't properly reset things. The phase is a two bit field and the commit only touches one of the two bits. Thus the commit had the following affect: - phase 0 => phase 90 - phase 90 => phase 90 - phase 180 => phase 270 - phase 270 => phase 270 Things get even weirder if you happen to have a bootloader that was actually using delay elements (should be no reason to, but you never know), since those are additional bits that weren't touched by the original patch. This is unlikely to be what we actually want. Checking on rk3288-veyron devices, I can see that the bootloader leaves these clocks as: - emmc: phase 180 - sdmmc: phase 90 - sdio0: phase 90 Thus on rk3288-veyron devices the commit we're reverting had the effect of changing the eMMC clock to phase 270. This probably explains the scattered reports I've heard of eMMC devices not working on some veyron devices when using the upstream kernel. The original commit was presumably made because previously the kernel didn't touch the "_drv" phase at all and relied on whatever value was there when the kernel started. If someone was using a bootloader that touched the "_drv" phase then, indeed, we should have code in the kernel to fix that. ...and also, to get ideal timings, we should also have the kernel change the phase depending on the speed mode. In fact, that's the subject of a recent patch I posted at <https://patchwork.kernel.org/patch/9075141/>. Ideally, we should take both the patch posted to dw_mmc and this revert. Since those will likely go through different trees, here I describe behavior with the combos: 1. Just this revert: likely will fix rk3288-veyron eMMC on some devices + other cases; might break someone with a strange bootloader that sets the phase to 0 or one that uses delay elements (pretty unpredicable what would happen in that case). 2. Just dw_mmc patch: fixes everyone. Effectly the dw_mmc patch will totally override the broken patch and fix everything. 3. Both patches: fixes everyone. Once dw_mmc is initting properly then any defaults from the clock code doesn't mattery. Fixes: 7a03fe6f48f3 ("clk: rockchip: reset init state before mmc card initialization") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> [emmc and sdmmc still work on all current boards in mainline after this revert, so they should take precedence over any out-of-tree board that will hopefully again get fixed with the better upcoming dw_mmc change.] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_srcXing Zheng2016-05-301-2/+2
| | | | | | | | | | | | | | | | | | There was a typo, swapping 'c' <--> 'g'. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | clk: rockchip: mark rk3399 GIC clocks as criticalBrian Norris2016-05-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We never want to kill the GIC. Noticed when making other clock fixups, and seeing the newly-constructed clock tree try to disable cpll, where we had this parent structure: aclk_gic <------\ |--- aclk_gic_pre <-- cpll <-- pll_cpll aclk_gic_noc <--/ Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | clk: rockchip: initialize flags of clk_init_data in mmc-phase clockHeiko Stuebner2016-05-301-0/+1
|/ | | | | | | | | | The flags element of clk_init_data was never initialized for mmc- phase-clocks resulting in the element containing a random value and thus possibly enabling unwanted clock flags. Fixes: 89bf26cbc1a0 ("clk: rockchip: Add support for the mmc clock phases using the framework") Cc: stable@vger.kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* Merge tag 'v4.7-rockchip-clk4' of ↵Stephen Boyd2016-05-124-47/+14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk updates from Heiko Stuebner: Another small rk3399 fixup as well as simplifications around our handling of the General-Register-Files syscon. * tag 'v4.7-rockchip-clk4' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: drop old_rate calculation on pll rate changes clk: rockchip: simplify GRF handling in pll clocks clk: rockchip: lookup General Register Files in rockchip_clk_init clk: rockchip: fix the rk3399 sdmmc sample / drv name
| * clk: rockchip: drop old_rate calculation on pll rate changesHeiko Stuebner2016-05-091-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously when everything happened in the set_rate callbacks itself we needed the old_rate value for the possible rate rollback, so that made it easy to also use it in the debug output. Now with the param-handling being done in separate functions, reading and recalculating the current pll rate only to use it in a debug message that won't get displayed in regular cases anyway is quite a waste. Therefore drop that value from the debug output. In the worst case that previous rate will have been displayed on the rate change before. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: simplify GRF handling in pll clocksHeiko Stuebner2016-05-093-33/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | With the previous commit, the clock drivers now know at init time if the GRF regmap is available. That means if it isn't available then, it also won't become available later and we can therefore switch PLLs, that need the GRF for the lock-status, to read-only mode - similar behaviour as the aborting of rate changes we did before. This saves some conditionals on every rate change and we can also drop the rockchip_clk_get_grf function completely. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: lookup General Register Files in rockchip_clk_initHeiko Stuebner2016-05-091-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the distant past syscons were initialized pretty late and weren't available at the time the clock init ran. As the GRF is mainly needed for PLL lock-status checking, we had this lazy init that tried to grab the syscon on PLL rate changes and denied these changes if it was not available. These days syscons are available very early and recent addition to rockchip clocks, like the PLL clk_init actually also rely on them being available at that time, so there is no need to keep that lazy init around, as it will also result in some more simplifications in other parts of the clock-code. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: fix the rk3399 sdmmc sample / drv nameDouglas Anderson2016-05-081-2/+2
| | | | | | | | | | | | | | | | | | | | The rk3399 clock table had a simple typo in it, calling the SDMMC sample and drive clocks by the wrong name. Fix this minor typo. Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Brian Norris <briannorris@chromium.org> Acked-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | Merge tag 'v4.7-rockchip-clk3' of ↵Stephen Boyd2016-05-022-169/+179
|\ \ | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk updates from Heiko Stuebner: A spelling fix and a bunch of rk3399 clock fixes. * tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix the rk3399 cifout clock clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399 clk: rockchip: add some frequencies on the rk3399 PLL table clk: rockchip: assign more necessary rk3399 clock ids clk: rockchip: export some necessary rk3399 clock ids clk: rockchip: rename rga clock-id on rk3399 clk: rockchip: add general gpu soft-reset on rk3399 clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399 clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type
| * clk: rockchip: fix the rk3399 cifout clockXing Zheng2016-04-251-5/+6
| | | | | | | | | | | | | | | | The cifout clock is incorrect due to the manual error, we need to fix it. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399Xing Zheng2016-04-251-157/+157
| | | | | | | | | | | | | | | | We don't need to many clocks enable after startup, to reduce some power consumption. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: add some frequencies on the rk3399 PLL tableXing Zheng2016-04-251-1/+10
| | | | | | | | | | | | | | This patch add some necessary frequencies for the RK3399 clock. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: assign more necessary rk3399 clock idsXing Zheng2016-04-251-6/+6
| | | | | | | | | | | | | | Assign newly added clock ids. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399Xing Zheng2016-04-251-2/+2
| | | | | | | | | | | | | | | | The gate bits of the i2c4 and i2c8 are incorrect due to the manual error, we need to fix them. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: fix of spelling mistake on unsuccessful in pll clock typeColin Ian King2016-04-251-2/+2
| | | | | | | | | | | | | | fix spelling mistake, unsucessful -> unsuccessful Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | Merge tag 'v4.7-rockchip-clk2' of ↵Stephen Boyd2016-04-204-81/+108
|\ \ | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull some checkpatch silencers from Heiko Stuebner: Fix quite some checkpatch warnings in the newly added rk3399 header and also in the clock code itself. * tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix checkpatch warning in core code clk: rockchip: drop unnecessary header comment clk: rockchip: reign in some overly long lines in the rk3399 controller clk: rockchip: fix checkpatch errors in rk3399 dt-binding header
| * clk: rockchip: fix checkpatch warning in core codeHeiko Stuebner2016-04-203-22/+27
| | | | | | | | | | | | | | | | | | We seem to have accumulated a bunch of checkpatch warnings, with mainly overlong lines and two unnecessary allocation error messages. Most were introduced with the recent multi-controller-support but some were quite a bit older. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: drop unnecessary header commentHeiko Stuebner2016-04-191-1/+0
| | | | | | | | | | | | | | | | | | The internal clk header did contain a comment indicating that some of the defined registers were shared over multiple clock controller variants. In recent times, it was simply extended all the time and stopped providing any meaningful information, so drop it and it's overlong line. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: reign in some overly long lines in the rk3399 controllerHeiko Stuebner2016-04-191-58/+81
| | | | | | | | | | | | | | | | | | | | We allow overlong lines in the array portitions describing the clock trees to ease readability by having each element always at the same position. But the rest of the code should honor the 80 char limit. Fix the newly added rk3399 clock code to respect that. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | Merge tag 'v4.7-rockchip-clk1' of ↵Stephen Boyd2016-04-1511-136/+2131
|\ \ | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk updates from Heiko Stuebner: This is first big chunk of Rockchip clock-related changes for 4.7. Main change is probably the added support for the new rk3399 soc and necessary infrastructure changes surrounding it. The biggest chunk is probably that clock code is now able to handle multiple clock providers in one system, as the rk3399 has two of those. A general one and another smaller one in a separate power domain. The rk3399 also uses another new pll type. Thankfully it just fits nicely into our current structure. It also needs some parts like the cpuclk mux parameters to be a bit more flexible and an new fractional divider subtype without gate. Apart from this big change we have some more fixes and removal of forgotten variables. * tag 'v4.7-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: add clock controller for the RK3399 dt-bindings: add bindings for rk3399 clock controller clk: rockchip: add dt-binding header for rk3399 clk: rockchip: release io resource when failing to init clk clk: rockchip: remove redundant checking of device_node clk: rockchip: fix warning reported by kernel-doc clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_data clk: rockchip: add new pll-type for rk3399 and similar socs clk: rockchip: Add support for multiple clock providers clk: rockchip: allow varying mux parameters for cpuclk pll-sources clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type
| * clk: rockchip: add clock controller for the RK3399Xing Zheng2016-03-283-1/+1562
| | | | | | | | | | | | | | Add the clock tree definition for the new RK3399 SoC. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: release io resource when failing to init clkShawn Lin2016-03-275-0/+5
| | | | | | | | | | | | | | | | We should call iounmap to relase reg_base since it's not going to be used any more if failing to init clk. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: remove redundant checking of device_nodeShawn Lin2016-03-271-5/+3
| | | | | | | | | | | | | | | | | | | | rockchip_clk_of_add_provider is used by sub-clk driver which already call of_iomap before calling it. If device_node does not exist, of_iomap returns NULL which will fail to init the sub-clk driver. So really it's redundant. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: fix warning reported by kernel-docShawn Lin2016-03-271-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ./scripts/kernel-doc -man -v drivers/clk/rockchip/clk.h > /dev/null drivers/clk/rockchip/clk.h:133: warning: missing initial short description on line: * struct rockchip_clk_provider: information about clock provider drivers/clk/rockchip/clk.h:133: info: Scanning doc for struct drivers/clk/rockchip/clk.h:164: warning: missing initial short description on line: * struct rockchip_pll_clock: information about pll clock drivers/clk/rockchip/clk.h:164: info: Scanning doc for struct drivers/clk/rockchip/clk.h:194: warning: No description found for parameter 'parent_names' drivers/clk/rockchip/clk.h:194: warning: No description found for parameter 'num_parents' drivers/clk/rockchip/clk.h:194: warning: Excess struct/union/enum/typedef member 'parent_name' description in 'rockchip_pll_clock' drivers/clk/rockchip/clk.h:235: warning: missing initial short description on line: * struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_dataShawn Lin2016-03-271-1/+0
| | | | | | | | | | | | | | mux_core_reg isn't been used anywhere, let's remove it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: add new pll-type for rk3399 and similar socsXing Zheng2016-03-272-2/+272
| | | | | | | | | | | | | | | | | | | | The rk3399's pll and clock are similar with rk3036's, it different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: Add support for multiple clock providersXing Zheng2016-03-278-118/+229
| | | | | | | | | | | | | | | | | | | | | | There are need to support Multi-CRUs probability in future, but it is not supported on the current Rockchip Clock Framework. Therefore, this patch add support a provider as the parameter handler when we call the clock register functions for per CRU. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: allow varying mux parameters for cpuclk pll-sourcesXing Zheng2016-03-277-11/+45
| | | | | | | | | | | | | | | | | | | | | | | | Thers are only two parent PLLs that APLL and GPLL for core on the previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed GPLL as alternate parent when core is switching freq. Since RK3399 big.LITTLE architecture, we need to select and adapt more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE typeXing Zheng2016-03-271-0/+16
| | | | | | | | | | | | | | | | Because there are some frac clock mux nodes don't have a gate node on the RK3399. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | clk: rockchip: Make reset_control_ops constPhilipp Zabel2016-03-291-1/+1
|/ | | | | | | | The rockchip_softrst_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2016-03-2311-212/+238
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The clk changes for this release cycle are mostly dominated by new device support in terms of LoC, but there has been some cleanup in the core as well as the usual minor clk additions to various drivers. Core: - parent tracking has been simplified - CLK_IS_ROOT is now a no-op flag, cleaning up drivers has started - of_clk_init() doesn't consider disabled DT nodes anymore - clk_unregister() had an error path bug squashed - of_clk_get_parent_count() has been fixed to only return unsigned ints - HAVE_MACH_CLKDEV is removed now that the last arch user (ARM) is gone New Drivers: - NXP LPC18xx creg - QCOM IPQ4019 GCC - TI dm814x ADPLL - i.MX6QP Updates: - Cyngus audio clks found on Broadcom iProc devices - Non-critical fixes for BCM2385 PLLs - Samsung exynos5433 updates for clk id errors, HDMI support, suspend/resume simplifications - USB, CAN, LVDS, and FCP clks on shmobile devices - sunxi got support for more clks on new SoCs and went through a minor refactoring/rewrite to use a simpler factor clk construct - rockchip added some more clk ids and added suport for fraction dividers - QCOM GDSCs in msm8996 - A new devm helper to make adding custom actions simpler (acked by Greg)" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (197 commits) clk: bcm2835: fix check of error code returned by devm_ioremap_resource() clk: renesas: div6: use RENESAS for #define clk: renesas: Rename header file renesas.h clk: max77{686,802}: Remove CLK_IS_ROOT clk: versatile: Remove CLK_IS_ROOT clk: sunxi: Remove use of variable length array clk: fixed-rate: Remove CLK_IS_ROOT clk: qcom: Remove CLK_IS_ROOT doc: dt: add documentation for lpc1850-creg-clk driver clk: add lpc18xx creg clk driver clk: lpc32xx: fix compilation warning clk: xgene: Add missing parenthesis when clearing divider value clk: mb86s7x: Remove CLK_IS_ROOT clk: x86: Remove clkdev.h and clk.h includes clk: x86: Remove CLK_IS_ROOT clk: mvebu: Remove CLK_IS_ROOT clk: renesas: move drivers to renesas directory clk: si5{14,351,70}: Remove CLK_IS_ROOT clk: scpi: Remove CLK_IS_ROOT clk: s2mps11: Remove CLK_IS_ROOT ...
| * Merge tag 'v4.6-rockchip-clk2' of ↵Stephen Boyd2016-03-046-61/+83
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull second batch of rockchip clk updates from Heiko Stuebner: Inclusion of the rk3368 fractional dividers into our handling scheme, fixes for missing error-handling in mmc-phase, inverters and cpu-clocks and some more clock-ids. * tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: include downstream muxes into fractional dividers on rk3368 clk: rockchip: set the clock ids for RK3228 HDMI clk: rockchip: set the clock ids for RK3228 VOP clk: rockchip: add the tsadc clocks found on rk3228 SoCs clk: rockchip: add the new clock ids for RK3228 HDMI clk: rockchip: add the new clock ids for RK3228 VOP clk: rockchip: add id of the tsadc clock found on rk3228 SoCs clk: rockchip: fix coding style for clk-cpu.c clk: rockchip: don't return NULL when registering mmc branch fails clk: rockchip: don't return NULL when registering inverter fails clk: rockchip: check grf when waiting pll lock clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
| | * clk: rockchip: include downstream muxes into fractional dividers on rk3368Elaine Zhang2016-02-261-37/+60
| | | | | | | | | | | | | | | | | | | | | | | | During the initial conversion to the newly introduced combined fractional dividers+muxes the rk3368 clocks were left out, so convert them now. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: set the clock ids for RK3228 HDMIYakir Yang2016-02-261-4/+4
| | | | | | | | | | | | | | | Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: set the clock ids for RK3228 VOPYakir Yang2016-02-261-3/+3
| | | | | | | | | | | | | | | Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: add the tsadc clocks found on rk3228 SoCsCaesar Wang2016-02-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the needed clocks for rk3228 tsadc. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: fix coding style for clk-cpu.cShawn Lin2016-02-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the issue reported by checkpatch: ERROR: space prohibited before that ',' (ctx:WxW) + writel(clksel->val , cpuclk->reg_base + clksel->reg); Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: don't return NULL when registering mmc branch failsShawn Lin2016-02-151-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid return NULL if rockchip_clk_register_mmc fails, otherwise rockchip_clk_register_branches print "unknown clock type". The acutal case is that it's a known clock type but we fail to regiser it, which may makes user confuse the reason of failure. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: don't return NULL when registering inverter failsShawn Lin2016-02-151-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid return NULL if rockchip_clk_register_inverter fails, otherwise rockchip_clk_register_branches print "unknown clock type". The acutal case is that it's a known clock type but we fail to regiser it, which may makes user confuse the reason of failure. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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