| Commit message (Collapse) | Author | Age | Files | Lines |
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This was killed off in generic code some time ago, kill off the left over
symbol.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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sh64 can use these as well, so tie them up there as well.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This adds page fault instrumentation for the software performance
counters. Follows the x86 and powerpc changes.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Fixes up a recently introduced build error.
Reported-by: Kyle McMartin <kyle@mcmartin.ca>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Fix the incorrect "select" directives by dropping the "CONFIG_"
prefixes, and correcting the typo "H8S2768" to "H8S2678".
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Acked-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6:
sh: Fix up HAVE_PERF_COUNTERS typo.
sh: Fix up more dma-mapping fallout.
sh: SH7786 SMP support.
sh: Wire up the uncached fixmap on sh64 as well.
sh: Use local TLB flush in set_pte_phys().
sh: Provide cpu_idle_wait() to fix up cpuidle/SMP build.
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That's HAVE_PERF_COUNTERS not HAVE_PERF_COUNTER. This was right
initially but I seem to have screwed it up while re-typing it out
by hand on another machine when I checked it in. Hmph.
Reported-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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commit dbe6f1869188b6e04e38aa861dd198befb08bcd7
("dma-mapping: mark dma_sync_single and dma_sync_sg as deprecated"
conveniently broke every single SH build.
In the future it would be great if people could at least bother
figuring out how to use grep.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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SH7786 is roughly identical to SH-X3 proto SMP, though there are only 2
CPUs. This just wraps in to the existing SH-X3 SMP code with some minor
changes for SH7786, including wiring up the IPIs properly, enabling
IRQ_PER_CPU, and so forth.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Now that sh64 also can use the uncached section, wire up the fixmap for
it as well.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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set_pte_phys() presently uses the global flush_tlb_one(), which locks on
SMP trying to do the IPI. As we have not even initialized the other CPUs
at this point, switch to the local_ variant so the flush happens on the
boot CPU.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Crib the x86 cpu_idle_wait() implementation and shove it in with the
idle code, subsequently enabling ARCH_HAS_CPU_IDLE_WAIT.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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* 'for-linus' of git://www.jni.nu/cris:
CRISv10: remove redundant tests on unsigned
CRISv32: irq.c - Move end brace outside #endif
CRISv32: Fix potential null reference in cryptocop driver.
CRISv32: Add arch optimized strcmp.
CRIS: assignment/is equal confusion
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Since dmanr is unsigned, negatives are wrapped and caught by the other test.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
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The end brace for a larger for statement was placed inside the #else
part of #ifdef TIMER_VECT1. However, for all current chips, the
define TIMER_VECT1 is always unset, and the error was never triggered.
Move the brace down below the #endif.
Fixes:
http://bugzilla.kernel.org/show_bug.cgi?id=13476
Reported-by: Martin Ettl <ettl.martin@gmx.de>
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Mikael Starvik <mikael.starvik@axis.com>
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The code didn't test the pointer to the newly allocated
memory, but a parameter sent in as value.
Since the input parameter was most often set, the code
would have used a null pointer if the kmalloc failed.
If the input parameter was not set, the code would
leak the allocated buffer.
http://bugzilla.kernel.org/show_bug.cgi?id=11363
Reported-by: Daniel Marjamäki <danielm77@spray.se>
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
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Add an optimized strcmp for CRISv32. This improves strcmp performance
with about 25% when comparing a 55 character string with itself.
Signed-off-by: Edgar Iglesias <edgar@axis.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
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Somehow, the assignments of rw->lock got written as comparisons.
The effect probably was that the read-write spinlocks never locked.
However, since the locks are only used in CONFIG_SMP and SMP CRIS is
experimental, it has never been identified as a problem.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (27 commits)
Blackfin: fix dma-mapping build errors
Blackfin: hook up new perf_counter_open syscall
Blackfin: drop BF535-specific text for exception 0x2A (unaligned instruction)
Blackfin: fix early crash when booting on wrong cpu
Blackfin: fix GPTMR0_CLOCKSOURCE dependency on BFIN_GPTIMERS
Blackfin: drop unused ISP1760 port1_disable from board resources
Blackfin: bf526-ezbrd: handle different SDRAM chips
Blackfin: fix typo in TRAS define in mem_init.h header
Blackfin: unify memory map headers
Blackfin: stick the CPU name into boot image name
Blackfin: update defconfigs
Blackfin: decouple unrelated cache settings to get exact behavior
Blackfin: update I-pipe patch level
Blackfin: remove obsolete mcount support from I-pipe code
Blackfin: allow CONFIG_TICKSOURCE_GPTMR0 with interrupt pipeline
Blackfin: convert interrupt pipeline to irqflags
Blackfin: allow people to select BF51x-0.1 silicon rev
Blackfin: bf526-ezbrd: set SPI flash resources to SST device
Blackfin: fix accidental reset in some boot modes
Blackfin: abstract irq14 lowering in do_irq
...
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The recent deprecation of dma_sync_{sg,single} ironically broke Blackfin
systems. This is because we don't define dma_sync_sg_for_cpu at all, so
until the DMA asm-generic conversion/cleanup is done after the next
release, simply stub out the dma_sync_sg_for_{cpu,device} functions.
Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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We don't support the BF535 at all, and the exception 0x2A text specific to
it is pretty verbose and confusing (since the behavior is simply odd), so
punt it to keep the noise down.
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Make sure we process the kernel command line before poking the hardware,
so that we can process early printk. This helps ensure that if you boot
a kernel configured for a different processor, something will be left in
the log buffer.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The GPTMR0_CLOCKSOURCE Kconfig option requires the gptimers framework, so
make sure it is selected when this option is enabled.
Reported-by: Peter Meerwald <pmeerw@pmeerw.net>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The port1 disable stuff was dropped from the USB ISP1760, so update the
Blackfin boards accordingly.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The BF526-EZBRD changed SDRAM chips between board revisions, so create a
timing table that can accommodate both.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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We defined SDRAM_tRAS to TRAS_4, but then wrongly defined SDRAM_tRAS_num
to 3.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Many aspects of the Blackfin memory map is exactly the same across all
variants. Rather than copy and paste all of these duplicated values in
each header, unify all of these into the common Blackfin memory map header
file. In the process, push down BF561 SMP specific stuff to the BF561
specific header to keep the noise down.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Rather than use "Linux" in the boot image name (as this is redundant --
the image type is already set to "linux"), use the CPU name. This makes
it fairly obvious when a wrong image is accidentally booted. Otherwise
there is no kernel output and you waste time scratching your head
wondering wtf just happened.
Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The current cache options don't really represent the hardware features.
They end up setting different aspects of the hardware so that the end
result is to turn on/off the cache. Unfortunately, when we hit cache
problems with the hardware, it's difficult to test different settings to
root cause the problem. The current settings also don't cleanly allow for
different caching behaviors with different regions of memory.
So split the configure options such that they properly reflect the settings
that are applied to the hardware.
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Philippe Gerum <rpm@xenomai.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Philippe Gerum <rpm@xenomai.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Philippe Gerum <rpm@xenomai.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Philippe Gerum <rpm@xenomai.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Now that 0.1 of the BF51x is coming out, allow people to build for it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The BF526-EZBRD has a SST SPI flash on it, not a ST Micro.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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We read the SWRST (Software Reset) register to get at the last reset
state, and then we may configure the DOUBLE_FAULT bit to control behavior
when a double fault occurs. But if the lower bits of the register is
already set (like UART boot mode on a BF54x), we inadvertently make the
system reset by writing to the SYSTEM_RESET field at the same time. So
make sure the lower 4 bits are always cleared.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Split out the optional IRQ14 lowering code to further simplify the
asm_do_IRQ() function and keep the ifdef nest under control.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Take a page from x86 and abstract the stack checking out of the
asm_do_IRQ() function so that the result is easier to digest.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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With the common IRQ code initializing much more of the irq_desc state, we
can't blindly initialize it ourselves to the local bad_irq state. If we
do, we end up wrongly clobbering many fields. So punt most of the bad irq
code as the common layers will handle the default state, and simply call
handle_bad_irq() directly when the IRQ we are processing is invalid.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Update anomaly headers to match latest released anomaly sheets.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The BF533-EZKIT has two Flash In-System Programming devices hooked up to
the async memory bus, so add resources for the primary flashes and the
SRAMs on the devices.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The common DSA code changed structure layout, so update the BF518F-EZBRD
resources accordingly.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The kgdb (in multiple places) and traps code developed pretty much
identical checks for how to access different regions of the Blackfin
memory map, but each wasn't 100%, so unify them to avoid duplication,
bitrot, and bugs with edge cases.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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* git://git.infradead.org/~dwmw2/iommu-2.6.31:
intel-iommu: Fix one last ia64 build problem in Pass Through Support
VT-d: support the device IOTLB
VT-d: cleanup iommu_flush_iotlb_psi and flush_unmaps
VT-d: add device IOTLB invalidation support
VT-d: parse ATSR in DMA Remapping Reporting Structure
PCI: handle Virtual Function ATS enabling
PCI: support the ATS capability
intel-iommu: dmar_set_interrupt return error value
intel-iommu: Tidy up iommu->gcmd handling
intel-iommu: Fix tiny theoretical race in write-buffer flush.
intel-iommu: Clean up handling of "caching mode" vs. IOTLB flushing.
intel-iommu: Clean up handling of "caching mode" vs. context flushing.
VT-d: fix invalid domain id for KVM context flush
Fix !CONFIG_DMAR build failure introduced by Intel IOMMU Pass Through Support
Intel IOMMU Pass Through Support
Fix up trivial conflicts in drivers/pci/{intel-iommu.c,intr_remapping.c}
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On ia64 with CONFIG_DMAR=n and CONFIG_SWIOTLB=y (as used in
arch/ia64/configs/tiger_defconfig) there is still a link
error with iommu_pass_through listed as an undefined symbol:
arch/ia64/kernel/built-in.o: In function `pci_swiotlb_init':
(.init.text+0x7f70): undefined reference to `iommu_pass_through'
Fix it by #defining iommu_pass_through away in asm/iommu.h
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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This updated patch should fix the compiling errors and remove the extern
iommu_pass_through from drivers/pci/intel-iommu.c file.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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The patch adds kernel parameter intel_iommu=pt to set up pass through
mode in context mapping entry. This disables DMAR in linux kernel; but
KVM still runs on VT-d and interrupt remapping still works.
In this mode, kernel uses swiotlb for DMA API functions but other VT-d
functionalities are enabled for KVM. KVM always uses multi level
translation page table in VT-d. By default, pass though mode is disabled
in kernel.
This is useful when people don't want to enable VT-d DMAR in kernel but
still want to use KVM and interrupt remapping for reasons like DMAR
performance concern or debug purpose.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Acked-by: Weidong Han <weidong@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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