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* x86 setup: be more verbose when probing EDDdevzero@web.de2008-01-301-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On early boot, probing the Bios for EDD happens without any message. Enhanced Disk Drive Services (EDD) is a mechanism to match x86 BIOS device names (int13 device 80h) to Linux device names (e.g. /dev/sda, /dev/hda) There are buggy Bios out there having problems with EDD. This can be problems with the Bios itself or with addon cards, too. This patch is adds an informational message on early boot. CONFIG_EDD is not set with defconfig, but with allmodconfig (i.e. CONFIG_EDD=m) so the EDD probe may be active on early boot on many systems nowadays. I can tell, that the probe is active on SuSE distro and with that I have seen more than one system hanging endlessly with those "black screen with a blinking cursor in the the upper left" on installation, making it difficult for the end- user to find out, what`s the issue. For sure I have seen this on FujitsuSiemens PCs with i810 and with i815 chipset. This one also honours the "quiet" bootparam. Also see: http://marc.info/?l=linux-kernel&m=119781937207969&w=2 http://marc.info/?l=linux-kernel&m=119783934032326&w=2 http://marc.info/?l=linux-kernel&m=119783678529100&w=2 Signed-off-by: Roland Kletzing <devzero@web.de> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86 setup: early cmdline parser handle boolean optionsdevzero@web.de2008-01-301-0/+65
| | | | | | | | | | | | | This patch extends the early commandline parser to support boolean options. The current version in mainline only supports parsing "option=arg" value pairs. With this it should be easy making other messages like "Uncompressing kernel" honour the "quiet" parameter, too. Signed-off-by: Roland Kletzing <devzero@web.de> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86 setup: fix constraints in segment accessor functionsH. Peter Anvin2008-01-301-8/+8
| | | | | | | | | | Fix the operand constraints for the segment accessor functions, {rd,wr}{fs,gs}*. In particular, the 8-bit functions used "r" constraints instead of "q" constraints. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86 setup: display VESA graphics modes in vga=ask menuH. Peter Anvin2008-01-305-24/+61
| | | | | | | | | | | | | Display VESA graphics modes, with their mode IDs, in the vga=ask menu. Most VESA mode numbers are platform-dependent, so it helps to have an easy way to display them. Based in part on a patch by Petr Vandrovec <petr@vandrovec.name>. Cc: Petr Vandrovec <petr@vandrovec.name> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86 setup: use X86_CR0_PE macro instead of hard-coded constantH. Peter Anvin2008-01-301-1/+2
| | | | | | | | | To set CR0.PE, use the X86_CR0_PE macro defined in <asm/processor-flags.h> instead of hardcoding it as a constant (1). Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86 setup: initialize LDTR and TR to make life easier to Intel VTH. Peter Anvin2008-01-302-0/+11
| | | | | | | | | | | Intel VT doesn't like to engage when the protected-mode state isn't fully initialized. Make life easier for it by initializing LDTR (to null) and TR (to a dummy hunk of low memory which will never actually be touched.) Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86 setup: make PM transition more paranoid; cleanup 32-bit entryH. Peter Anvin2008-01-301-12/+32
| | | | | | | | | | | | | | | | Make the transition to protected mode more paranoid by having back-to-back near jump (to synchronize the 386/486 prefetch queue) and far jump (to set up the code segment.) While we're at it, zero as many registers as practical (for future expandability of the 32-bit entry interface) and enter 32-bit mode with a valid stack. Note that the 32-bit code cannot rely on this stack, or we'll break all other existing users of the 32-bit entrypoint, but it may make debugging hacks easier to write. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: trivial whitespace in kprobes.cHarvey Harrison2008-01-301-3/+3
| | | | | | | Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Acked-by: Masami Hiramatsu <mhiramat@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: move get_segment_eip() to step.cHarvey Harrison2008-01-303-154/+81
| | | | | | | | | | get_segment_eip has similarities to convert_rip_to_linear(), and is used in a similar context. Move get_segment_eip to step.c to allow easier consolidation. Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: move out tick_nohz_stop_sched_tick() call from the loopHiroshi Shimamoto2008-01-301-2/+1
| | | | | | | | | Move out tick_nohz_stop_sched_tick() call from the loop in cpu_idle same as 32-bit version. Signed-off-by: Hiroshi Shimamoto <h-shimamoto@ct.jp.nec.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: coding style fixes in arch/x86/pci/fixup.cPaolo Ciarrocchi2008-01-301-15/+15
| | | | | | | | | | | | | | | | | | Simple coding style fixes. no code changed: text data bss dec hex filename 3139 576 194 3909 f45 fixup.o.before 3139 576 194 3909 f45 fixup.o.after md5: 9a3467057478b2d99962bdd448282eeb fixup.o.before.asm 9a3467057478b2d99962bdd448282eeb fixup.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: use fixup_exception() in traps_64.cHarvey Harrison2008-01-301-32/+15
| | | | | | | | | Use the fixup_exception() helper instead of the open-coded search_extable() users. Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: more users of PF_ constants in fault_32|64.cHarvey Harrison2008-01-302-4/+5
| | | | | | | | | Should be the last of the error_code tests that could use the PF_ defines. Makes X86_32|64 a little closer. Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: introduce __die helper to X86_32Harvey Harrison2008-01-301-34/+42
| | | | | | | | | | | | | Small step towards unifying traps_32|64.c. No functional changes. Pull out a small helper from an if() statement in die(). Marked as __kprobes as eventually we will want to call this from do_page_fault similar to how X86_64 does it. Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: change x86 machine check handler to use unlocked_ioctl insteadNikanth Karthikesan2008-01-301-3/+2
| | | | | | | | | | | | | | | | | | The machine check handler registers ioctl handler that is called with the BKL held. Changing to register unlocked_ioctl instead. Also mce ioctl handler does not seem to need any lock protection. To: Andi Kleen <andi@firstfloor.org> Cc: linux-kernel@vger.kernel.org Cc: kernel-janitors@vger.kernel.org Change the Machine check handler to use unlocked_ioctl instead of ioctl handler. Also the mce ioctl handler does not need any lock protection. Signed-off-by: Nikanth Karthikesan <knikanth@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* xen: mask out PWT tooJeremy Fitzhardinge2008-01-301-1/+1
| | | | | | | | | The hypervisor doesn't allow PCD or PWT to be set on guest ptes, so make sure they're masked out. Also, fix up some previous mispatching. Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86/vmi: fix compilation as a result of pte_t changesJeremy Fitzhardinge2008-01-301-4/+4
| | | | | | | | | Fix various compilation problems as a result of changing pte_t. Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Cc: Zachary Amsden <zach@vmware.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: page.h: make pte_t a union to always includeJeremy Fitzhardinge2008-01-301-3/+1
| | | | | | | | | | | | Make sure pte_t, whatever its definition, has a pte element with type pteval_t. This allows common code to access it without needing to be specifically parameterised on what pagetable mode we're compiling for. For 32-bit, this means that pte_t becomes a union with "pte" and "{ pte_low, pte_high }" (PAE) or just "pte_low" (non-PAE). Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: unify pgtable accessors which useJeremy Fitzhardinge2008-01-301-2/+3
| | | | | | | | | | | Make users of supported_pte_mask common. This has the side-effect of introducing the variable for 32-bit non-PAE, but I think its a pretty small cost to simplify the code. Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: avoid name conflict for Voyager leave_mmJeremy Fitzhardinge2008-01-301-5/+5
| | | | | | | | Avoid a conflict between Voyager's leave_mm and asm-x86/mmu.h's leave_mm. Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: coding style fixes in arch/x86/ia32/audit.cPaolo Ciarrocchi2008-01-301-1/+1
| | | | | | | | | | | Fix one error reported by checkpatch, it now reports: total: 0 errors, 0 warnings, 42 lines checked Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: make NUMA work on 32-bit againMel Gorman2008-01-301-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 32-bit NUMA, the memmap representing struct pages on each node is allocated from node-local memory if possible. As only node-0 has memory from ZONE_NORMAL, the memmap must be mapped into low memory. This is done by reserving space in the Kernel Virtual Area (KVA) for the memmap belonging to other nodes by taking pages from the end of ZONE_NORMAL and remapping the other nodes memmap into those virtual addresses. The node boundaries are then adjusted so that the region of pages is not used and it is marked as reserved in the bootmem allocator. This reserved portion of the KVA is PMD aligned althought strictly speaking that requirement could be lifted (see thread at http://lkml.org/lkml/2007/8/24/220). The problem is that when aligned, there may be a portion of ZONE_NORMAL at the end that is not used for memmap and does not have an initialised memmap nor is it marked reserved in the bootmem allocator. Later in the boot process, these pages are freed and a storm of Bad page state messages result. This patch marks these pages reserved that are wasted due to alignment in the bootmem allocator so they are not accidently freed. It is worth noting that memory from node-0 is wasted where it could have been put into ZONE_HIGHMEM on NUMA machines. Worse, the KVA is always reserved from the location of real memory even when there is plenty of spare virtual address space. This patch also makes sure that reserve_bootmem() is not called with a 0-length size in numa_kva_reserve(). When this happens, it usually means that a kernel built for Summit is being booted on a normal machine. The resulting BUG_ON() is misleading so it is caught here. Signed-off-by: Mel Gorman <mel@csn.ul.ie> Signed-off-by: Andy Whitcroft <apw@shadowen.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86, ptrace: add bts_struct size to status commandMarkus Metzger2008-01-301-0/+2
| | | | | | | | | Return the size of bts_struct in the PTRACE_BTS_STATUS command. Change types to u32. Signed-off-by: Markus Metzger <markus.t.metzger@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: unify arch/x86/kernel/acpi/sleep*.cPavel Machek2008-01-304-188/+88
| | | | | | | | | | | | | Unify arch/x86/kernel/acpi/sleep*.c Pretty trivial unification; when two functions differed, it was usually in error handling, and better of the two was picked up. Signed-off-by: Pavel Machek <pavel@suse.cz> Looks-okay-to: Rafael J. Wysocki <rjw@sisk.pl> Tested-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: clean up arch/x86/mm/fault_64.cIngo Molnar2008-01-301-3/+3
| | | | | | | clean up arch/x86/mm/fault_64.c a bit. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* percpu: make the asm-generic/percpu.h more "generic"travis@sgi.com2008-01-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add support for PER_CPU_ATTRIBUTES - fix generic smp percpu_modcopy to use per_cpu_offset() macro. Add the ability to use generic/percpu even if the arch needs to override several aspects of its operations. This will enable the use of generic percpu.h for all arches. An arch may define: __per_cpu_offset Do not use the generic pointer array. Arch must define per_cpu_offset(cpu) (used by x86_64, s390). __my_cpu_offset Can be defined to provide an optimized way to determine the offset for variables of the currently executing processor. Used by ia64, x86_64, x86_32, sparc64, s/390. SHIFT_PTR(ptr, offset) If an arch defines it then special handling of pointer arithmentic may be implemented. Used by s/390. (Some of these special percpu arch implementations may be later consolidated so that there are less cases to deal with.) Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Mike Travis <travis@sgi.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* percpu: use a kconfig variable to signal arch specific percpu setuptravis@sgi.com2008-01-304-0/+12
| | | | | | | | | | | | | The use of the __GENERIC_PERCPU is a bit problematic since arches may want to run their own percpu setup while using the generic percpu definitions. Replace it through a kconfig variable. Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Mike Travis <travis@sgi.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* i386: handle an initrd in highmem (version 2)H. Peter Anvin2008-01-303-27/+112
| | | | | | | | | | | | | | | | The boot protocol has until now required that the initrd be located in lowmem, which makes the lowmem/highmem boundary visible to the boot loader. This was exported to the bootloader via a compile-time field. Unfortunately, the vmalloc= command-line option breaks this part of the protocol; instead of adding yet another hack that affects the bootloader, have the kernel relocate the initrd down below the lowmem boundary inside the kernel itself. Note that this does not rely on HIGHMEM being enabled in the kernel. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86 boot : export boot_params via debugfs for debuggingHuang, Ying2008-01-305-1/+81
| | | | | | | | | | | | | | | | | | | This patch export the boot parameters via debugfs for debugging. The files added are as follow: boot_params/data : binary file for struct boot_params boot_params/version : boot protocol version This patch is based on 2.6.24-rc5-mm1 and has been tested on i386 and x86_64 platform. This patch is based on the Peter Anvin's proposal. Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: reboot_{32|64}.c unificationMiguel Boton2008-01-303-315/+160
| | | | | | | | | | | | | | | | | | reboot_{32|64}.c unification patch. This patch unifies the code from the reboot_32.c and reboot_64.c files. It has been tested in computers with X86_32 and X86_64 kernels and it looks like all reboot modes work fine (EFI restart system hasn't been tested yet). Probably I made some mistakes (like I usually do) so I hope we can identify and fix them soon. Signed-off-by: Miguel Boton <mboton@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: kprobes change kprobe_handler flowAbhishek Sagar2008-01-301-67/+86
| | | | | | | Signed-off-by: Abhishek Sagar <sagar.abhishek@gmail.com> Signed-off-by: Quentin Barnes <qbarnes@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: make arch/x86/kernel/acpi/wakeup_32.S use a separateEric Dumazet2008-01-302-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While examining vmlinux namelist on i386 (nm -v vmlinux) I noticed : c01021d0 t es7000_rename_gsi c010221a T es7000_start_cpu <Big Hole> c0103000 T thread_saved_pc and c0113218 T acpi_restore_state_mem c0113219 T acpi_save_state_mem <Big Hole> c0114000 t wakeup_code This is because arch/x86/kernel/acpi/wakeup_32.S forces a .text alignment of 4096 bytes. (I have no idea if it is really needed, since arch/x86/kernel/acpi/wakeup_64.S uses a 16 bytes alignment *only*) So arch/x86/kernel/built-in.o also has this alignment arch/x86/kernel/built-in.o: file format elf32-i386 Sections: Idx Name Size VMA LMA File off Algn 0 .text 00018c94 00000000 00000000 00001000 2**12 CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE But as arch/x86/kernel/acpi/wakeup_32.o is not the first object linked into arch/x86/kernel/built-in.o, linker had to build several holes to meet alignement requirements, because of .o nestings in the kbuild process. This can be solved by using a special section, .text.page_aligned, so that no holes are needed. # size vmlinux.before vmlinux.after text data bss dec hex filename 4619942 422838 458752 5501532 53f25c vmlinux.before 4610534 422838 458752 5492124 53cd9c vmlinux.after This saves 9408 bytes Signed-off-by: Eric Dumazet <dada1@cosmosbay.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: mark memory_setup __initAndi Kleen2008-01-301-1/+1
| | | | | | | | | | Otherwise WARNING: vmlinux.o(.text+0x64a9): Section mismatch: reference to .init.text:machine_specific_memory_setup (between 'memory_setup' and 'show_cpuinfo') Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: Set CFQ as default in 32-bit defconfigAndi Kleen2008-01-301-2/+2
| | | | | | | | | Someone complained that the 32-bit defconfig contains AS as default IO scheduler. Change that to CFQ. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: compile apm and voyager module only when selected in KconfigAndi Kleen2008-01-304-9/+9
| | | | | | | | | | | | Previously the complete files were #ifdef'ed, but now handle that in the Makefile. May save a minor bit of compilation time. [ Stephen Rothwell <sfr@canb.auug.org.au>: build dependency fix ] Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: document fdimage/isoimage completely in make helpAndi Kleen2008-01-301-8/+12
| | | | | | | | | | Add missing targets and missing options in x86 make help [ mingo@elte.hu: more whitespace cleanups ] Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: remove CPU capabitilites printks on 32-bitAndi Kleen2008-01-301-19/+1
| | | | | | | | I don't know of any case where they have been useful and they look ugly. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86/efi: fix improper use of lvalueJeremy Fitzhardinge2008-01-301-1/+1
| | | | | | | | | | | | | | | # HG changeset patch # User Jeremy Fitzhardinge <jeremy@xensource.com> # Date 1199391030 28800 # Node ID 5d35c92fdf0e2c52edbb6fc4ccd06c7f65f25009 # Parent 22f6a5902285b58bfc1fbbd9e183498c9017bd78 x86/efi: fix improper use of lvalue pgd_val is no longer valid as an lvalue, so don't try to assign to it. Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: fix detection of CONSTANT_TSC bit for AMD CPUsAndreas Herrmann2008-01-301-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commits - c52f61fcbdb2aa84f0e4d831ef07f375e6b99b2c (x86: allow TSC clock source on AMD Fam10h and some cleanup) - e30436f05d456efaff77611e4494f607b14c2782 (x86: move X86_FEATURE_CONSTANT_TSC into early cpu feature detection) are supposed to fix the detection of contant TSC for AMD CPUs. Unfortunately on x86_64 it does still not work with current x86/mm. For a Phenom I still get: ... TSC calibrated against PM_TIMER Marking TSC unstable due to TSCs unsynchronized time.c: Detected 2288.366 MHz processor. ... We have to set c->x86_power in early_identify_cpu to properly detect the CONSTANT_TSC bit in early_init_amd. Attached patch fixes this issue. Following the relevant boot messages when the fix is used: ... TSC calibrated against PM_TIMER time.c: Detected 2288.279 MHz processor. ... Initializing CPU#1 ... checking TSC synchronization [CPU#0 -> CPU#1]: passed. ... Initializing CPU#2 ... checking TSC synchronization [CPU#0 -> CPU#2]: passed. ... Booting processor 3/4 APIC 0x3 ... checking TSC synchronization [CPU#0 -> CPU#3]: passed. Brought up 4 CPUs ... Patch is against x86/mm (v2.6.24-rc8-672-ga9f7faa). Please apply. Set c->x86_power in early_identify_cpu. This ensures that X86_FEATURE_CONSTANT_TSC can properly be set in early_init_amd. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: remove explicit C3 TSC check on 64bitAndi Kleen2008-01-301-8/+1
| | | | | | | | | | | | | | | | | | | Trust the ACPI code to disable TSC instead when C3 is used. AMD Fam10h does not disable TSC in any C states so the check was incorrect there anyways after the change to handle this like Intel on AMD too. This allows to use the TSC when C3 is disabled in software (acpi.max_c_state=2), but the BIOS supports it anyways. Match i386 behaviour. Cc: lenb@kernel.org Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: allow TSC clock source on AMD Fam10h and some cleanupAndi Kleen2008-01-302-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After a lot of discussions with AMD it turns out that TSC on Fam10h CPUs is synchronized when the CONSTANT_TSC cpuid bit is set. Or rather that if there are ever systems where that is not true it would be their BIOS' task to disable the bit. So finally use TSC gettimeofday on Fam10h by default. Or rather it is always used now on CPUs where the AMD specific CONSTANT_TSC bit is set. This gives a nice speed bost for gettimeofday() on these systems which tends to be by far the most common v/syscall. On a Fam10h system here TSC gtod uses about 20% of the CPU time of acpi_pm based gtod(). This was measured on 32bit, on 64bit it is even better because TSC gtod() can use a vsyscall and stay in ring 3, which acpi_pm doesn't. The Intel check simply checks for CONSTANT_TSC too without hardcoding Intel vendor. This is equivalent on 64bit because all 64bit capable Intel CPUs will have CONSTANT_TSC set. On Intel there is no CPU supplied CONSTANT_TSC bit currently, but we synthesize one based on hardcoded knowledge which steppings have p-state invariant TSC. So the new logic is now: On CPUs which have the AMD specific CONSTANT_TSC bit set or on Intel CPUs which are new enough to be known to have p-state invariant TSC always use TSC based gettimeofday() Cc: lenb@kernel.org Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: move X86_FEATURE_CONSTANT_TSC into early cpu feature detectionAndi Kleen2008-01-305-24/+59
| | | | | | | | | | | | Need this in the next patch in time_init and that happens early. This includes a minor fix on i386 where early_intel_workarounds() [which is now called early_init_intel] really executes early as the comments say. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: fix sched_clock()Ingo Molnar2008-01-301-9/+4
| | | | | | | [ andi@firstfloor.org: build fix ] Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: remove get_cycles_syncAndi Kleen2008-01-303-9/+9
| | | | | | | | | | | rdtsc is now speculation-safe, so no need for the sync variants of the APIs. [ mingo@elte.hu: removed the nsec_barrier() complication. ] Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: read_tsc syncIngo Molnar2008-01-301-0/+3
| | | | | | | make native_read_tsc() always non-speculative. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: map vsyscalls early enoughIngo Molnar2008-01-302-2/+3
| | | | | | | | map vsyscalls early enough. This is important if a __vsyscall_fn function is used by other kernel code too. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: move native_read_tsc() offlineIngo Molnar2008-01-301-0/+10
| | | | | | | move native_read_tsc() offline. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: lfence fixIngo Molnar2008-01-301-1/+1
| | | | | | | | | LFENCE is available on XMM2 or higher Intel CPUs - not XMM or higher... this caused boot failures on XMM1 & !XMM1 capable CPUs. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: Implement support to synchronize RDTSC with LFENCE on Intel CPUsAndi Kleen2008-01-302-5/+3
| | | | | | | | | | | | | According to Intel RDTSC can be always synchronized with LFENCE on all current CPUs. Implement the necessary CPUID bit for that. It is unclear yet if that is true for all future CPUs too, but if there's another way the kernel can be always updated. Cc: asit.k.mallick@intel.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: implement support to synchronize RDTSC through MFENCE on AMD CPUsAndi Kleen2008-01-302-2/+5
| | | | | | | | | | According to AMD RDTSC can be synchronized through MFENCE. Implement the necessary CPUID bit for that. Cc: andreas.herrmann3@amd.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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