| Commit message (Collapse) | Author | Age | Files | Lines |
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http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
* 'devel-stable' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm: (178 commits)
ARM: 7139/1: fix compilation with CONFIG_ARM_ATAG_DTB_COMPAT and large TEXT_OFFSET
ARM: gic, local timers: use the request_percpu_irq() interface
ARM: gic: consolidate PPI handling
ARM: switch from NO_MACH_MEMORY_H to NEED_MACH_MEMORY_H
ARM: mach-s5p64x0: remove mach/memory.h
ARM: mach-s3c64xx: remove mach/memory.h
ARM: plat-mxc: remove mach/memory.h
ARM: mach-prima2: remove mach/memory.h
ARM: mach-zynq: remove mach/memory.h
ARM: mach-bcmring: remove mach/memory.h
ARM: mach-davinci: remove mach/memory.h
ARM: mach-pxa: remove mach/memory.h
ARM: mach-ixp4xx: remove mach/memory.h
ARM: mach-h720x: remove mach/memory.h
ARM: mach-vt8500: remove mach/memory.h
ARM: mach-s5pc100: remove mach/memory.h
ARM: mach-tegra: remove mach/memory.h
ARM: plat-tcc: remove mach/memory.h
ARM: mach-mmp: remove mach/memory.h
ARM: mach-cns3xxx: remove mach/memory.h
...
Fix up mostly pretty trivial conflicts in:
- arch/arm/Kconfig
- arch/arm/include/asm/localtimer.h
- arch/arm/kernel/Makefile
- arch/arm/mach-shmobile/board-ap4evb.c
- arch/arm/mach-u300/core.c
- arch/arm/mm/dma-mapping.c
- arch/arm/mm/proc-v7.S
- arch/arm/plat-omap/Kconfig
largely due to some CONFIG option renaming (ie CONFIG_PM_SLEEP ->
CONFIG_ARM_CPU_SUSPEND for the arm-specific suspend code etc) and
addition of NEED_MACH_MEMORY_H next to HAVE_IDE.
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TEXT_OFFSET
If TEXT_OFFSET is too large (e.g. like on MSM) the resulting immediate
argument gets wider than 8 bits.
Noticed by David Brown <davidb@codeaurora.org>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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git://github.com/mzyngier/arm-platforms into devel-stable
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This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).
PPIs are now useable for more than just the local timers.
Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).
Cc: David Brown <davidb@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).
Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.
This also allows the removal of some duplicated code.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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devel-stable
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Given that we want the default to not have any <mach/memory.h> and given
that there are now fewer cases where it is still provided than the cases
where it is not at this point, this makes sense to invert the logic and
just identify the exception cases.
The word "need" instead of "have" was chosen to construct the config
symbol so not to suggest that having a mach/memory.h file is actually
a feature that one should aim for.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Move some DDR2 related defines into a private <mach/ddr2.h> beforehand.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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This also removes the mach/s3c2400 version which was probably never used
due to the fact that we have this line in arch/arm/Makefile:
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 [...]
This is later used to construct the search path for:
The compiler would be looking into mach-s3c2410 and picking up this
version first. Any config that was actually expecting the mach-s3c2400
version was therefore producing a broken kernel binary. Not relying on
any of them anymore would fix that issue.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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When the CONFIG_NO_MACH_MEMORY_H symbol is selected by a particular
machine class, the machine specific memory.h include file is no longer
used and can be removed. In that case the equivalent information can
be obtained dynamically at runtime by enabling CONFIG_ARM_PATCH_PHYS_VIRT
or by specifying the physical memory address at kernel configuration time.
If/when all instances of mach/memory.h are removed then this symbol could
be removed.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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This achieves two goals:
1) Get rid of davinci_uart_v2p() and davinci_uart_p2v() which were the
last users of PLAT_PHYS_OFFSET.
2) Remove the probing of the M bit in the CP15 control reg and make
the access to the .data variables completely position independent.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
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This is the first step to remove PLAT_PHYS_OFFSET usage from the debug
UART code.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
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This achieves two goals:
1) Get rid of omap_uart_v2p() and omap_uart_p2v() which were the last users
of PLAT_PHYS_OFFSET.
2) Remove the probing of the M bit in the CP15 control reg and make
the access to the .data variables completely position independent.
There is a catch though: the busyuart macro needs to know where the LSR
register is which might be at a different offset depending on the hardware.
Given that this macro is given only two registers and that one of them
must be preserved, the trick is to always pass the LSR register address
around, and deduce the base address for the THR register by masking out
the LSR offset in senduart instead.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Tested-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
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This achieves two goals:
1) Get rid of omap_uart_v2p() and omap_uart_p2v() which were the last users
of PLAT_PHYS_OFFSET.
2) Remove the probing of the M bit in the CP15 control reg and make
the access to the .data variables completely position independent.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Tested-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
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