| Commit message (Collapse) | Author | Age | Files | Lines |
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The default linker behavior is to optimize identical literal values
and remove unnecessary overhead. However, because of a bug in the
linker, this currently results in an error ('call target out of range').
Disable link-time optimizations per default until there is a fix
for the linker and add the option to iss_defconfig.
Signed-off-by: Chris Zankel <chris@zankel.net>
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TLB sanity checking code depends on full MMU presence and may not be
built in noMMU confgiuration.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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- check that user TLB mappings correspond to the current page table;
- check that TLB mapping VPN is in the kernel/user address range
in accordance with its ASID.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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Add a brief sanity test of S32C1I functionality. This instruction
is needed by the kernel and userland as part of the base ABI
(including GCC atomic builtins, certain threading packages, future
atomic support in the C++ standard, etc). However, correct operation
of this instruction requires some cooperation by hardware external to
the processor (such as bus bridge, bus fabric, or memory controller).
Minimally exercising this mechanism and reporting explicit status
early in the boot process is helpful to chip vendors using the Linux
kernel as a benchmark of correctness of hardware.
As it turns out, S32C1I is not exercised by the kernel and by uClibc
based userland as of early June 2008. This is expected to change
soon as both incorporate more recent open source developments.
Signed-off-by: Marc Gauthier <marc@tensilica.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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The default linker behavior is to optimize identical literal values and
remove unnecessary overhead from assembler-generated "longcall" sequences
to reduce code size. Provide an option to disable this behavior to improve
compile time.
Signed-off-by: Chris Zankel <chris@zankel.net>
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The attached patches provides part 1 of an architecture implementation for the
Tensilica Xtensa CPU series.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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