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* Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tileLinus Torvalds2013-09-0649-880/+5515
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull Tile arch updates from Chris Metcalf: "These changes bring in a bunch of new functionality that has been maintained internally at Tilera over the last year, plus other stray bits of work that I've taken into the tile tree from other folks. The changes include some PCI root complex work, interrupt-driven console support, support for performing fast-path unaligned data fixups by kernel-based JIT code generation, CONFIG_PREEMPT support, vDSO support for gettimeofday(), a serial driver for the tilegx on-chip UART, KGDB support, more optimized string routines, support for ftrace and kprobes, improved ASLR, and many bug fixes. We also remove support for the old TILE64 chip, which is no longer buildable" * git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: (85 commits) tile: refresh tile defconfig files tile: rework <asm/cmpxchg.h> tile PCI RC: make default consistent DMA mask 32-bit tile: add null check for kzalloc in tile/kernel/setup.c tile: make __write_once a synonym for __read_mostly tile: remove support for TILE64 tile: use asm-generic/bitops/builtin-*.h tile: eliminate no-op "noatomichash" boot argument tile: use standard tile_bundle_bits type in traps.c tile: simplify code referencing hypervisor API addresses tile: change <asm/system.h> to <asm/switch_to.h> in comments tile: mark pcibios_init() as __init tile: check for correct compiler earlier in asm-offsets.c tile: use standard 'generic-y' model for <asm/hw_irq.h> tile: use asm-generic version of <asm/local64.h> tile PCI RC: add comment about "PCI hole" problem tile: remove DEBUG_EXTRA_FLAGS kernel config option tile: add virt_to_kpte() API and clean up and document behavior tile: support FRAME_POINTER tile: support reporting Tilera hypervisor statistics ...
| * tile PCI RC: make default consistent DMA mask 32-bitChris Metcalf2013-09-032-11/+25
| | | | | | | | | | | | | | | | | | This change sets the PCI devices' initial DMA capabilities conservatively and promotes them at the request of the driver, as opposed to assuming advanced DMA capabilities. The old design runs the risk of breaking drivers that assume default capabilities. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: add null check for kzalloc in tile/kernel/setup.cWang Sheng-Hui2013-09-031-0/+4
| | | | | | | | | | | | | | | | | | Should check the return value of kzalloc first to avoid the null pointer. Then can dereference the non-null pointer to access the fields of struct resource. Signed-off-by: Wang Sheng-Hui <shhuiw@gmail.com> Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: make __write_once a synonym for __read_mostlyChris Metcalf2013-09-032-13/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was really only useful for TILE64 when we mapped the kernel data with small pages. Now we use a huge page and we really don't want to map different parts of the kernel data in different ways. We retain the __write_once name in case we want to bring it back to life at some point in the future. Note that this change uncovered a latent bug where the "smp_topology" variable happened to always be aligned mod 8 so we could store two "int" values at once, but when we eliminated __write_once it ended up only aligned mod 4. Fix with an explicit annotation. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: remove support for TILE64Chris Metcalf2013-09-038-132/+6
| | | | | | | | | | | | | | | | | | | | | | This chip is no longer being actively developed for (it was superceded by the TILEPro64 in 2008), and in any case the existing compiler and toolchain in the community do not support it. It's unlikely that the kernel works with TILE64 at this point as the configuration has not been tested in years. The support is also awkward as it requires maintaining a significant number of ifdefs. So, just remove it altogether. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: use standard tile_bundle_bits type in traps.cChris Metcalf2013-09-031-9/+3
| | | | | | | | | | | | We were rolling our own bundle_bits, which is unnecessary. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: simplify code referencing hypervisor API addressesChris Metcalf2013-09-031-17/+8
| | | | | | | | | | | | | | | | There's no need to make up new ways of computing the addresses of the Tilera hypervisor APIs; just use the standard method of relying on the symbols to provide the addresses. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: change <asm/system.h> to <asm/switch_to.h> in commentsChris Metcalf2013-09-032-4/+4
| | | | | | | | | | | | Also fix mentions of it in #error statements. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: mark pcibios_init() as __initChris Metcalf2013-09-032-2/+2
| | | | | | | | | | | | | | It was bombed away because it was previously marked as __devinit, but it should be an __init function. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: check for correct compiler earlier in asm-offsets.cChris Metcalf2013-09-031-8/+8
| | | | | | | | | | | | | | | | If we wait until after including a bunch of other files, we will have generated so much warning spew that it's hard to notice the error about using the wrong compiler. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: add virt_to_kpte() API and clean up and document behaviorChris Metcalf2013-09-031-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | We use virt_to_pte(NULL, va) a lot, which isn't very obvious. I added virt_to_kpte(va) as a more obvious wrapper function, that also validates the va as being a kernel adddress. And, I fixed the semantics of virt_to_pte() so that we handle the pud and pmd the same way, and we now document the fact that we handle the final pte level differently. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: support reporting Tilera hypervisor statisticsChris Metcalf2013-09-031-0/+76
| | | | | | | | | | | | | | | | Newer hypervisors have an API for reporting per-cpu statistics information. This change allows seeing that information via /sys/devices/system/cpu/cpuN/hv_stats file for each core. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tilegx: support KGDBChris Metcalf2013-09-033-0/+505
| | | | | | | | | | | | | | | | | | | | Enter kernel debugger at boot with: --hvd UART_1=1 --hvx kgdbwait --hvx kgdboc=ttyS1,115200 or at runtime with: echo ttyS1,115200 > /sys/module/kgdboc/parameters/kgdboc echo g > /proc/sysrq-trigger Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: parameterize VA and PA space more cleanlyChris Metcalf2013-09-037-21/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing code relied on the hardware definition (<arch/chip.h>) to specify how much VA and PA space was available. It's convenient to allow customizing this for some configurations, so provide symbols MAX_PA_WIDTH and MAX_VA_WIDTH in <asm/page.h> that can be modified if desired. Additionally, move away from the MEM_XX_INTRPT nomenclature to define the start of various regions within the VA space. In fact the cleaner symbol is, for example, MEM_SV_START, to indicate the start of the area used for supervisor code; the actual address of the interrupt vectors is not as important, and can be changed if desired. As part of this change, convert from "intrpt1" nomenclature (which built in the old privilege-level 1 model) to a simple "intrpt". Also strip out some tilepro-specific code supporting modifying the PL the kernel could run at, since we don't actually support using different PLs in tilepro, only tilegx. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: don't assume user privilege is zeroChris Metcalf2013-09-032-7/+18
| | | | | | | | | | | | | | | | | | | | Technically, user privilege is anything less than kernel privilege. We modify the existing user_mode() macro to have this semantic (and use it in a couple of places it wasn't being used before), and add an IS_KERNEL_EX1() macro to the assembly code as well. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: clean up relocate_kernel_64 debug codeChris Metcalf2013-09-031-2/+7
| | | | | | | | | | | | | | | | We remove some debug code in relocate_kernel_64.S that made raw calls to the hv_console_putc Tilera hypervisor API, since everything should funnel through the early_hv_write() API. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tilegx: change how we find the kernel stackChris Metcalf2013-08-305-23/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we used a special-purpose register (SPR_SYSTEM_SAVE_K_0) to hold the CPU number and the top of the current kernel stack by using the low bits to hold the CPU number, and using the high bits to hold the address of the page just above where we'd want the kernel stack to be. That way we could initialize a new SP when first entering the kernel by just masking the SPR value and subtracting a couple of words. However, it's actually more useful to be able to place an arbitrary kernel-top value in the SPR. This allows us to create a new stack context (e.g. for virtualization) with an arbitrary top-of-stack VA. To make this work, we now store the CPU number in the high bits, above the highest legal VA bit (42 bits in the current tilegx microarchitecture). The full 42 bits are thus available to store the top of stack value. Getting the current cpu (a relatively common operation) is still fast; it's now a shift rather than a mask. We make this change only for tilegx, since tilepro has too few SPR bits to do this, and we don't need this support on tilepro anyway. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: don't call show_regs_print_info() with corrupt currentChris Metcalf2013-08-301-3/+5
| | | | | | | | | | | | | | | | | | We use the validate_current() API to make sure that "current" seems plausible before using it. With the new show_regs_print_info() API, we want to check that current is OK before calling it, since otherwise we will end up in a recursive panic. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: group .hottext* sections properly in vmlinux.ldsChris Metcalf2013-08-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | With this change such sections are grouped with regular text in the vmlinux image; this change puts them at the front, which is where the standard Linux includes .text.hot*. This change should fix a recently-observed bug where a bunch of symbols were being omitted from the /proc/kallsyms output because they fell between _etext and _sinittext. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: do less L1 I-cache evictionChris Metcalf2013-08-301-1/+7
| | | | | | | | | | | | | | | | | | We had been doing an automatic full eviction of the L1 I$ everywhere whenever we did a kernel-space TLB flush. It turns out this isn't necessary, since all the callers already handle doing a flush if necessary. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: allow "initrd" boot argument for kexecChris Metcalf2013-08-301-0/+42
| | | | | | | | | | | | This enables support for "kexec --initrd" for tile. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: correct r1 value during syscall tracingChris Metcalf2013-08-301-0/+15
| | | | | | | | | | | | | | | | | | The r1 value is set based on the r0 value as we return to user space. So tracing tools won't automatically see the right value. Fix this by generating the correct r1 value in do_syscall_trace_exit() rather than trying to tamper with the hot path in syscall return. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: fix panic with large IRQ numberChris Metcalf2013-08-301-1/+2
| | | | | | | | | | | | | | | | The "available_irqs" value needs to actually reflect the IRQs available, not just start as an all-ones mask, since we only have 32 IRQs available even on a 64-bit platform. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: support kprobes on tilegxTony Lu2013-08-305-4/+585
| | | | | | | | | | | | | | | | This change includes support for Kprobes, Jprobes and Return Probes. Reviewed-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Signed-off-by: Tony Lu <zlu@tilera.com> Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: support ftrace on tilegxTony Lu2013-08-304-0/+477
| | | | | | | | | | | | | | | | This commit adds support for static ftrace, graph function support, and dynamic tracer support. Signed-off-by: Tony Lu <zlu@tilera.com> Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: provide traceability for hypervisor callsChris Metcalf2013-08-139-72/+356
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds infrastructure (CONFIG_TILE_HVGLUE_TRACE) that provides C code wrappers for the calls the kernel makes to the Tilera hypervisor. This allows standard kernel infrastructure like FTRACE to be able to instrument hypervisor calls. To allow direct calls to the true API, we export their names with a leading underscore as well. This is important for the few contexts where we need to make hypervisor calls without touching the stack. As part of this change, we also switch from creating the symbols with linker magic to creating them with assembler magic. This lets us provide a symbol type and generally make them appear more as symbols and less as just random values in the Elf namespace. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: implement gettimeofday() via vDSOChris Metcalf2013-08-1313-22/+656
| | | | | | | | | | | | | | | | | | | | | | | | | | This change creates the framework for vDSO calls, makes the existing rt_sigreturn() mechanism use it, and adds a fast gettimeofday(). Now that we need to expose the vDSO address to userspace, we add AT_SYSINFO_EHDR to the set of aux entries provided to userspace. (You can disable any extra vDSO support by booting with vdso=0, but the rt_sigreturn vDSO page will still be provided.) Note that glibc has supported the tile vDSO since release 2.17. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: improve illegal translation interrupt handlingChris Metcalf2013-08-132-11/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | First, don't re-enable interrupts blindly in the Linux trap handler. We already handle page faults this way; synchronous interrupts like ILL_TRANS will fire even when interrupts are disabled, and we don't want to re-enable interrupts in that case. For ILL_TRANS, we now pass the ILL_VA_PC reason into the trap handler so we can report it properly; this is the address that caused the illegal translation trap. We print the address as part of the pr_alert() message now if it's coming from the kernel. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: make register dumps more readableChris Metcalf2013-08-131-10/+10
| | | | | | | | | | | | | | | | It's much easier to read register dumps if you read vertically rather than horizontally, since the register numbers line up and lead the eye down more than to the right. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: improve big-endian supportChris Metcalf2013-08-131-10/+14
| | | | | | | | | | | | | | | | | | | | | | | | First, fix a bug in asm/unaligned.h; we need to just use the asm-generic unaligned.h so we properly choose endian-correct flavors. Second, keep the hv/hypervisor.h ABI fully "native" in the sense that we don't have __BIG_ENDIAN__ ifdefs there. Instead, we use macros in the head_NN.S assembly code to properly extract two 32-bit structure members from a 64-bit register holding the structure. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: support CONFIG_PREEMPTChris Metcalf2013-08-139-29/+67
| | | | | | | | | | | | | | | | | | | | This change adds support for CONFIG_PREEMPT (full kernel preemption). In addition to the core support, this change includes a number of places where we fix up uses of smp_processor_id() and per-cpu variables. I also eliminate the PAGE_HOME_HERE and PAGE_HOME_UNKNOWN values for page homing, as it turns out they weren't being used. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: avoid recursive backtrace faultsChris Metcalf2013-08-131-2/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | This change adds support for avoiding recursive backtracer crashes; we haven't seen this in practice other than when things are seriously corrupt, but it may help avoid losing the root cause of a crash. Also, don't abort kernel backtracers for invalid userspace PC's. If we do, we lose the ability to backtrace through a userspace call to a bad address above PAGE_OFFSET, even though that it can be perfectly reasonable to continue the backtrace in such a case. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: fast-path unaligned memory access for tilegxChris Metcalf2013-08-139-66/+1927
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change enables unaligned userspace memory access via a kernel fast path on tilegx. The kernel tracks user PC/instruction pairs per-thread using a direct-mapped cache in userspace. The cache maps those PC/instruction pairs to JIT'ed instruction sequences that load or store using byte-wide load store intructions and then synthesize 2-, 4- or 8-byte load or store results. Once an instruction has been seen to generate an unaligned access once, subsequent hits on that instruction typically require overhead of only around 50 cycles if cache and TLB is hot. We support the prctl() PR_GET_UNALIGN / PR_SET_UNALIGN sys call to enable or disable unaligned fixups on a per-process basis. To do this we pull some of the tilepro unaligned support out of the single_step.c file; tilepro uses instruction disassembly for both single-step and unaligned access support. Since tilegx actually has hardware singlestep support, though, it's cleaner to keep the tilegx unaligned access code in a separate file. While we're at it, properly rename the tilepro-specific types, etc., to have tilepro suffixes instead of generic tile suffixes. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: remove unnecessary backslashes in asm-offsets.cChris Metcalf2013-08-121-14/+14
| | | | | | | | | | | | | | Pointed out by checkpatch. A few of the DEFINE() lines were properly written without backslash continuation; fix the rest. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: fix comment bug in sys_cmpxchg descriptionChris Metcalf2013-08-121-1/+1
| | | | | | | | Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: support "memmap" boot parameterChris Metcalf2013-08-121-4/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds support for the "memmap" boot parameter similar to what x86 provides. The tile version supports "memmap=1G$5G", for example, as a way to reserve a 1 GB range starting at PA 5GB. The memory is reserved via bootmem during startup, and we create a suitable "struct resource" marked as "Reserved" so you can see the range reported by /proc/iomem. Up to 64 such regions can currently be reserved on the boot command line. We do not support the x86 options "memmap=nn@ss" (force some memory to be available at the given address) since it's pointless to try to have Linux use memory the Tilera hypervisor hasn't given it. We do not support "memmap=nn#ss" to add an ACPI range for later processing, since we don't support ACPI. We do not support "memmap=exactmap" since we don't support reading the e820 information from the BIOS like x86 does. I did add support for "memmap=nn" (and the synonym "mem=nn") which cap the highest PA value at "nn"; these are both just a synonym for the existing tile boot option "maxmem". Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: various console improvementsChris Metcalf2013-08-123-39/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change improves and cleans up the tile console. - We enable HVC_IRQ support on tilegx, with the addition of a new Tilera hypervisor API for tilegx to allow a console IPI. If IPI support is not available we fall back to the previous polling mode. - We simplify the earlyprintk code to use CON_BOOT and eliminate some of the other supporting earlyprintk code. - A new tile_console_write() primitive is used to send output to the console and is factored out of the hvc_tile driver. This lets us support a "sim_console" boot argument to allow using simulator hooks to send output to the "console" as a slightly faster alternative to emulating the hardware more directly. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * tile PCI RC: reduce driver's vmalloc space usageChris Metcalf2013-08-061-2/+8
| | | | | | | | | | | | | | | | | | | | We can take advantage of the fact that bit 29 is hard-wired to zero in register TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR. This is handy since at the moment we only allocate one 4GB region for vmalloc, and with this change we can allocate four or more TRIO MACs without using up all the vmalloc space. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile PCI RC: support PCIe TRIO 0 MAC 0 on Gx72 systemChris Metcalf2013-08-061-3/+30
| | | | | | | | | | | | | | On Tilera Gx72 systems, the logic for figuring out whether a given port is root complex is slightly different. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile PCI DMA: fix bug in non-page-aligned accessorsChris Metcalf2013-08-061-2/+2
| | | | | | | | | | | | | | | | The code incorrectly masked with PAGE_OFFSET instead of PAGE_SIZE-1. This only matters when trying to do a non page-aligned DMA; it was noticed during code inspection. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile PCI RC: add dma_get_required_mask()Chris Metcalf2013-08-061-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | The standard kernel function dma_get_required_mask() uses the highest DRAM address to determine if 32-bit or 64-bit DMA addressing is needed. This only works on architectures that have direct mapping between the PA and the PCI address space, i.e. those that don't have I/O TLBs or have I/O TLB but choose to use direct mapping. Neither of these are true for tilegx. Whether to use 64-bit DMA should depend on the PCI device's capability only, not on the amount of DRAM installeds, so we now advertise a 64-bit DMA mask unconditionally. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile PCI RC: use proper accessor functionChris Metcalf2013-08-061-13/+11
| | | | | | | | | | | | | | | | Using the low-level hv_dev_pread() API makes assumptions about the layout of datastructures in the Tilera hypervisor API; it's better to use the gxio_XXX accessor and the pcie_trio_ports_property struct. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile PCI RC: bomb comments and whitespace formatChris Metcalf2013-08-061-124/+56
| | | | | | | | | | | | | | This change is purely stylistic but improves the readability of the tile PCI RC driver. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile PCI RC: eliminate pci_controller.mem_resources fieldChris Metcalf2013-08-061-59/+12
| | | | | | | | | | | | | | The .mem_resources[] field in the pci_controller struct is now obsoleted by the .mem_space and .io_space fields. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile PCI RC: restructure TRIO initializationChris Metcalf2013-08-061-92/+117
| | | | | | | | | | | | | | | | | | | | The TRIO shim initialization is shared with other kernel drivers such as the endpoint and StreamIO drivers, so reorganize the initialization flow to ensure that the root complex driver properly initializes TRIO state regardless of what kind of TRIO driver will end up using the shim. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile PCI DMA: handle a NULL dev argument properlyChris Metcalf2013-08-061-2/+3
| | | | | | | | Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile PCI RC: support I/O space accessChris Metcalf2013-08-061-8/+120
| | | | | | | | | | | | | | | | | | | | To enable this functionality, configure CONFIG_TILE_PCI_IO. Without this flag, the kernel still assigns I/O address ranges to the devices, but no TRIO resource and mapping support is provided. We assign disjoint I/O address ranges to separate PCIe domains. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile PCI RC: gentler warning for missing plug-in PCIChris Metcalf2013-08-061-2/+8
| | | | | | | | | | | | | | Besides using pr_info() to print the linkdown status for a plug-in slot, add extra indication that this is expected if the slot is empty. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile PCI RC: support more MSI-X interrupt vectorsChris Metcalf2013-08-061-20/+39
| | | | | | | | | | | | | | | | | | To support PCIe devices with higher number of MSI-X interrupt vectors, e.g. 16 for the LSI RAID card, enhance the Gx RC stack to provide more MSI-X vectors by using the TRIO Scatter Queues, which provide 8 more vectors in addition to ~10 from the Map Mem regions. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * tile: support LSI MEGARAID SAS HBA hybrid dma_opsChris Metcalf2013-08-061-9/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LSI MEGARAID SAS HBA suffers from the problem where it can do 64-bit DMA to streaming buffers but not to consistent buffers. In other words, 64-bit DMA is used for disk data transfers and 32-bit DMA must be used for control message transfers. According to LSI, the firmware is not fully functional yet. This change implements a kind of hybrid dma_ops to support this. Note that on most other platforms, the 64-bit DMA addressing space is the same as the 32-bit DMA space and they overlap the physical memory space. No special arrangement is needed to support this kind of mixed DMA capability. On TILE-Gx, the 64-bit DMA space is completely separate from the 32-bit DMA space. Due to the use of the IOMMU, the 64-bit DMA space doesn't overlap the physical memory space. On the other hand, the 32-bit DMA space overlaps the physical memory space under 4GB. The separate address spaces make it necessary to have separate dma_ops. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
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