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* arch/tile: export only COMMAND_LINE_SIZE to userspace.Chris Metcalf2010-08-151-2/+6
| | | | | | | This fixes a failure in "make headers_check" for tile. I hadn't realized this file was exported to userspace by default. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
* arch/tile: rename ARCH_KMALLOC_MINALIGN to ARCH_DMA_MINALIGNChris Metcalf2010-08-151-3/+2
| | | | | | | See commit a6eb9fe105d5de0053b261148cee56c94b4720ca. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
* arch/tile: Rename the hweight() implementations to __arch_hweight()Chris Metcalf2010-08-131-4/+5
| | | | | | See commit 1527bc8b928dd1399c3d3467dd47d9ede210978a. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
* Merge branch 'master' into for-linusChris Metcalf2010-08-131-9/+0
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| * dma-mapping: remove dma_is_consistent APIFUJITA Tomonori2010-08-111-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Architectures implement dma_is_consistent() in different ways (some misinterpret the definition of API in DMA-API.txt). So it hasn't been so useful for drivers. We have only one user of the API in tree. Unlikely out-of-tree drivers use the API. Even if we fix dma_is_consistent() in some architectures, it doesn't look useful at all. It was invented long ago for some old systems that can't allocate coherent memory at all. It's better to export only APIs that are definitely necessary for drivers. Let's remove this API. Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Cc: James Bottomley <James.Bottomley@HansenPartnership.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * dma-mapping: unify dma_get_cache_alignment implementationsFUJITA Tomonori2010-08-111-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dma_get_cache_alignment returns the minimum DMA alignment. Architectures defines it as ARCH_DMA_MINALIGN (formally ARCH_KMALLOC_MINALIGN). So we can unify dma_get_cache_alignment implementations. Note that some architectures implement dma_get_cache_alignment wrongly. dma_get_cache_alignment() should return the minimum DMA alignment. So fully-coherent architectures should return 1. This patch also fixes this issue. Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | arch/tile: Various cleanups.Chris Metcalf2010-08-134-44/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change rolls up random cleanups not representing any actual bugs. - Remove a stale CONFIG_ value from the default tile_defconfig - Remove unused tns_atomic_xxx() family of methods from <asm/atomic.h> - Optimize get_order() using Tile's "clz" instruction - Fix a bad hypervisor upcall name (not currently used in Linux anyway) - Use __copy_in_user_inatomic() name for consistency, and export it - Export some additional hypervisor driver I/O upcalls and some homecache calls - Remove the obfuscating MEMCPY_TEST_WH64 support code - Other stray comment cleanups, #if 0 removal, etc. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
* | arch/tile: support backtracing on TILE-GxChris Metcalf2010-08-131-1/+3
| | | | | | | | | | | | | | | | | | This functionality was stubbed out until recently. Now we support our normal backtracing API on TILE-Gx as well as on TILE64/TILEPro. This change includes a tweak to the instruction encoding caused by adding addxli for compat mode. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
* | arch/tile: Fix a couple of issues with the COMPAT code for TILE-Gx.Chris Metcalf2010-08-132-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | First, the siginfo preamble wasn't quite right; we need to indicate that we are padding up to 4 ints of preamble for 64-bit code, and then for compat mode we need to pad differently, using only 3 ints. Second, the C ABI requires a save area of two registers, not two pointers, since in compat mode we have 64-bit registers all of which we need to save, even though we only have 32-bit VAs. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
* | arch/tile: support new kunmap_atomic() naming convention.Chris Metcalf2010-08-111-1/+1
| | | | | | | | | | | | See commit 597781f3e51f48ef8e67be772196d9e9673752c4. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
* | tile: remove unused ISA_DMA_THRESHOLD defineFUJITA Tomonori2010-08-111-21/+0
|/ | | | | | | | No need to define ISA_DMA_THRESHOLD Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> [cmetcalf@tilera.com: converted to a single-line #include file] Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
* arch/tile: catch up on various minor cleanups.Chris Metcalf2010-07-066-32/+7
| | | | | | | | | | | | | None of these changes fix any actual bugs, but are just various cleanups that fell out along the way. In particular, some unused #defines and includes are removed, PREFETCH_STRIDE is added (the default is right for our shipping chips, but wrong for our next generation), our tile-specific prefetching code is removed so the (identical) generic prefetching code can be used instead, a comment is fixed to be proper GPL and not just a "paste GPL here" token, a "//" comment is converted to "/* */", etc. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* tile: set ARCH_KMALLOC_MINALIGNFUJITA Tomonori2010-07-061-0/+8
| | | | | | | | | Architectures that handle DMA-non-coherent memory need to set ARCH_KMALLOC_MINALIGN to make sure that kmalloc'ed buffer is DMA-safe: the buffer doesn't share a cache with the others. Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Acked-by: Chris Metcalf <cmetcalf@tilera.com>
* tile: remove homegrown L1_CACHE_ALIGN macroFUJITA Tomonori2010-07-061-1/+0
| | | | | | | Let's use the standard L1_CACHE_ALIGN macro instead. Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Acked-by: Chris Metcalf <cmetcalf@tilera.com>
* arch/tile: Miscellaneous cleanup changes.Chris Metcalf2010-07-0620-122/+265
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is primarily changes caused by reviewing "sparse" and "checkpatch" output on our sources, so is somewhat noisy, since things like "printk() -> pr_err()" (or whatever) throughout the codebase tend to get tedious to read. Rather than trying to tease apart precisely which things changed due to which type of code review, this commit includes various cleanups in the code: - sparse: Add declarations in headers for globals. - sparse: Fix __user annotations. - sparse: Using gfp_t consistently instead of int. - sparse: removing functions not actually used. - checkpatch: Clean up printk() warnings by using pr_info(), etc.; also avoid partial-line printks except in bootup code. - checkpatch: Use exposed structs rather than typedefs. - checkpatch: Change some C99 comments to C89 comments. In addition, a couple of minor other changes are rolled in to this commit: - Add support for a "raise" instruction to cause SIGFPE, etc., to be raised. - Remove some compat code that is unnecessary when we fully eliminate some of the deprecated syscalls from the generic syscall ABI. - Update the tile_defconfig to reflect current config contents. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* arch/tile: Split the icache flush code off to a generic <arch> header.Chris Metcalf2010-07-062-7/+96
| | | | | | | | | | | This code is used in other places in our system than in Linux, so to share it we now implement it as an inline function in our low-level <arch> headers, and instantiate it in one file in Linux's arch/tile/lib. The file is now cacheflush.c and is C code rather than the strangely-named and assembler-implemented __invalidate_icache.S. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* arch/tile: Shrink the tile-opcode files considerably.Chris Metcalf2010-07-062-184/+2
| | | | | | | | | | | The C file (tile-desc_{32,64}.c) was about 300KB before this change, and is now shrunk down to 100K. The original file included support for BFD in the binutils toolchain, which is not necessary in the kernel; the kernel version only needs to include enough support to enable the single-stepper and backtracer. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* arch/tile: Add driver to enable access to the user dynamic network.Chris Metcalf2010-07-063-4/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This network (the "UDN") connects all the cpus on the chip in a wormhole-routed dynamic network. Subrectangles of the chip can be allocated by a "create" ioctl on /dev/hardwall, and then to access the UDN in that rectangle, tasks must perform an "activate" ioctl on that same file object after affinitizing themselves to a single cpu in the region. Sending a wormhole-routed message that tries to leave that subrectangle causes all activated tasks to receive a SIGILL (just as they would if they tried to access the UDN without first activating themselves to a hardwall rectangle). The original submission of this code to LKML had the driver instantiated under /proc/tile/hardwall. Now we just use a character device for this, conventionally /dev/hardwall. Some futures planning for the TILE-Gx chip suggests that we may want to have other types of devices that share the general model of "bind a task to a cpu, then 'activate' a file descriptor on a pseudo-device that gives access to some hardware resource". As such, we are using a device rather than, for example, a syscall, to set up and activate this code. As part of this change, the compat_ptr() declaration was fixed and used to pass the compat_ioctl argument to the normal ioctl. So far we limit compat code to 2GB, so the difference between zero-extend and sign-extend (the latter being correct, eventually) had been overlooked. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* arch/tile: Enable more sophisticated IRQ model for 32-bit chips.Chris Metcalf2010-07-066-63/+181
| | | | | | | | | | | | This model is based on the on-chip interrupt model used by the TILE-Gx next-generation hardware, and interacts much more cleanly with the Linux generic IRQ layer. The change includes modifications to the Tilera hypervisor, which are reflected in the hypervisor headers in arch/tile/include/arch/. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Thomas Gleixner <tglx@linutronix.de>
* Revert adding some arch-specific signal syscalls to <linux/syscalls.h>.Chris Metcalf2010-06-071-21/+1
| | | | | | | | | | | It turns out there is some variance on the calling conventions for these syscalls, and <asm-generic/syscalls.h> is already the mechanism used to handle this. Switch arch/tile over to using that mechanism and tweak the calling conventions for a couple of tile syscalls to match <asm-generic/syscalls.h>. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
* arch/tile: core support for Tilera 32-bit chips.Chris Metcalf2010-06-04128-0/+16093
This change is the core kernel support for TILEPro and TILE64 chips. No driver support (except the console driver) is included yet. This includes the relevant Linux headers in asm/; the low-level low-level "Tile architecture" headers in arch/, which are shared with the hypervisor, etc., and are build-system agnostic; and the relevant hypervisor headers in hv/. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Reviewed-by: Paul Mundt <lethal@linux-sh.org>
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